Lines Matching +full:adc +full:- +full:dev
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
9 mcu_conf: scm-conf@40f00000 {
10 compatible = "syscon", "simple-mfd";
12 #address-cells = <1>;
13 #size-cells = <1>;
17 compatible = "ti,am654-phy-gmii-sel";
19 #phy-cells = <1>;
25 compatible = "pinctrl-single";
27 #pinctrl-cells = <1>;
28 pinctrl-single,register-width = <32>;
29 pinctrl-single,function-mask = <0x00000101>;
34 compatible = "pinctrl-single";
36 #pinctrl-cells = <1>;
37 pinctrl-single,register-width = <32>;
38 pinctrl-single,function-mask = <0x00000003>;
42 compatible = "ti,am654-uart";
45 clock-frequency = <96000000>;
46 current-speed = <115200>;
47 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
52 compatible = "mmio-sram";
55 #address-cells = <1>;
56 #size-cells = <1>;
60 compatible = "ti,am654-i2c", "ti,omap4-i2c";
63 #address-cells = <1>;
64 #size-cells = <0>;
65 clock-names = "fck";
67 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
72 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
76 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
77 #address-cells = <1>;
78 #size-cells = <0>;
83 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
87 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
88 #address-cells = <1>;
89 #size-cells = <0>;
94 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
98 power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>;
99 #address-cells = <1>;
100 #size-cells = <0>;
105 compatible = "ti,am654-tscadc", "ti,am3359-tscadc";
109 assigned-clocks = <&k3_clks 0 2>;
110 assigned-clock-rates = <60000000>;
111 clock-names = "fck";
114 dma-names = "fifo0", "fifo1";
117 adc {
118 #io-channel-cells = <1>;
119 compatible = "ti,am654-adc", "ti,am3359-adc";
124 compatible = "ti,am654-tscadc", "ti,am3359-tscadc";
128 assigned-clocks = <&k3_clks 1 2>;
129 assigned-clock-rates = <60000000>;
130 clock-names = "fck";
133 dma-names = "fifo0", "fifo1";
136 adc {
137 #io-channel-cells = <1>;
138 compatible = "ti,am654-adc", "ti,am3359-adc";
148 compatible = "ti,am654-timer";
151 clock-names = "fck";
152 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
153 ti,timer-pwm;
158 compatible = "ti,am654-timer";
161 clock-names = "fck";
162 power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>;
163 ti,timer-pwm;
168 compatible = "ti,am654-timer";
171 clock-names = "fck";
172 power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>;
173 ti,timer-pwm;
178 compatible = "ti,am654-timer";
181 clock-names = "fck";
182 power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>;
183 ti,timer-pwm;
188 compatible = "simple-bus";
189 #address-cells = <2>;
190 #size-cells = <2>;
192 dma-coherent;
193 dma-ranges;
195 ti,sci-dev-id = <119>;
198 compatible = "ti,am654-navss-ringacc";
204 reg-names = "rt", "fifos", "proxy_gcfg",
206 ti,num-rings = <286>;
207 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
209 ti,sci-dev-id = <195>;
210 msi-parent = <&inta_main_udmass>;
213 mcu_udmap: dma-controller@285c0000 {
214 compatible = "ti,am654-navss-mcu-udmap";
221 reg-names = "gcfg", "rchanrt", "tchanrt",
223 msi-parent = <&inta_main_udmass>;
224 #dma-cells = <1>;
227 ti,sci-dev-id = <194>;
230 ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */
232 ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */
234 ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */
239 compatible = "ti,am654-secure-proxy";
240 #mbox-cells = <1>;
241 reg-names = "target_data", "rt", "scfg";
248 * firmware on non-MPU processors
257 reg-names = "m_can", "message_ram";
258 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
260 clock-names = "hclk", "cclk";
261 interrupt-parent = <&gic500>;
264 interrupt-names = "int0", "int1";
265 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
273 reg-names = "m_can", "message_ram";
274 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
276 clock-names = "hclk", "cclk";
277 interrupt-parent = <&gic500>;
280 interrupt-names = "int0", "int1";
281 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
286 compatible = "simple-bus";
287 #address-cells = <2>;
288 #size-cells = <2>;
292 compatible = "ti,am654-ospi", "cdns,qspi-nor";
296 cdns,fifo-depth = <256>;
297 cdns,fifo-width = <4>;
298 cdns,trigger-address = <0x0>;
300 assigned-clocks = <&k3_clks 248 0>;
301 assigned-clock-parents = <&k3_clks 248 2>;
302 assigned-clock-rates = <166666666>;
303 power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>;
304 #address-cells = <1>;
305 #size-cells = <0>;
310 compatible = "ti,am654-ospi", "cdns,qspi-nor";
314 cdns,fifo-depth = <256>;
315 cdns,fifo-width = <4>;
316 cdns,trigger-address = <0x0>;
318 power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
319 #address-cells = <1>;
320 #size-cells = <0>;
326 compatible = "ti,am654-cpsw-nuss";
327 #address-cells = <2>;
328 #size-cells = <2>;
330 reg-names = "cpsw_nuss";
332 dma-coherent;
334 clock-names = "fck";
335 power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>;
346 dma-names = "tx0", "tx1", "tx2", "tx3",
350 ethernet-ports {
351 #address-cells = <1>;
352 #size-cells = <0>;
356 ti,mac-only;
358 ti,syscon-efuse = <&mcu_conf 0x200>;
364 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
366 #address-cells = <1>;
367 #size-cells = <0>;
369 clock-names = "fck";
375 compatible = "ti,am65-cpts";
378 clock-names = "cpts";
379 interrupts-extended = <&gic500 GIC_SPI 570 IRQ_TYPE_LEVEL_HIGH>;
380 interrupt-names = "cpts";
381 ti,cpts-ext-ts-inputs = <4>;
382 ti,cpts-periodic-outputs = <2>;
384 mcu_cpsw_cpts_mux: refclk-mux {
385 #clock-cells = <0>;
390 assigned-clocks = <&mcu_cpsw_cpts_mux>;
391 assigned-clock-parents = <&k3_clks 118 5>;
397 compatible = "ti,am654-r5fss";
398 ti,cluster-mode = <1>;
399 #address-cells = <1>;
400 #size-cells = <1>;
403 power-domains = <&k3_pds 129 TI_SCI_PD_EXCLUSIVE>;
406 compatible = "ti,am654-r5f";
409 reg-names = "atcm", "btcm";
411 ti,sci-dev-id = <159>;
412 ti,sci-proc-ids = <0x01 0xff>;
414 firmware-name = "am65x-mcu-r5f0_0-fw";
415 ti,atcm-enable = <1>;
416 ti,btcm-enable = <1>;
421 compatible = "ti,am654-r5f";
424 reg-names = "atcm", "btcm";
426 ti,sci-dev-id = <245>;
427 ti,sci-proc-ids = <0x02 0xff>;
429 firmware-name = "am65x-mcu-r5f0_1-fw";
430 ti,atcm-enable = <1>;
431 ti,btcm-enable = <1>;
437 compatible = "ti,j7-rti-wdt";
440 power-domains = <&k3_pds 135 TI_SCI_PD_SHARED>;
441 assigned-clocks = <&k3_clks 135 0>;
442 assigned-clock-parents = <&k3_clks 135 4>;