Lines Matching +full:0 +full:xc400
12 reg = <0x0 0x70000000 0x0 0x200000>;
15 ranges = <0x0 0x0 0x70000000 0x200000>;
17 atf-sram@0 {
18 reg = <0x0 0x20000>;
22 reg = <0xf0000 0x10000>;
26 reg = <0x100000 0x100000>;
37 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
38 <0x00 0x01880000 0x00 0x90000>, /* GICR */
39 <0x00 0x6f000000 0x00 0x2000>, /* GICC */
40 <0x00 0x6f010000 0x00 0x1000>, /* GICH */
41 <0x00 0x6f020000 0x00 0x2000>; /* GICV */
50 reg = <0x00 0x01820000 0x00 0x10000>;
51 socionext,synquacer-pre-its = <0x1000000 0x400000>;
59 reg = <0x0 0x900000 0x0 0x2000>;
69 mux-controls = <&serdes_mux 0>;
74 reg = <0x0 0x910000 0x0 0x2000>;
89 reg = <0x00 0x02800000 0x00 0x100>;
99 reg = <0x00 0x02810000 0x00 0x100>;
108 reg = <0x00 0x02820000 0x00 0x100>;
117 reg = <0x0 0x4e00000 0x0 0x1200>;
121 ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>;
123 dmas = <&main_udmap 0xc001>, <&main_udmap 0x4002>,
124 <&main_udmap 0x4003>;
129 reg = <0x0 0x4e10000 0x0 0x7d>;
138 reg = <0x0 0x104200 0x0 0x30>;
141 pinctrl-single,function-mask = <0x0000001ff>;
147 reg = <0x0 0x104280 0x0 0x20>;
150 pinctrl-single,function-mask = <0x0000000f>;
155 reg = <0x0 0x11c000 0x0 0x2e4>;
158 pinctrl-single,function-mask = <0xffffffff>;
163 reg = <0x0 0x11c2e8 0x0 0x24>;
166 pinctrl-single,function-mask = <0xffffffff>;
171 reg = <0x0 0x2000000 0x0 0x100>;
174 #size-cells = <0>;
183 reg = <0x0 0x2010000 0x0 0x100>;
186 #size-cells = <0>;
195 reg = <0x0 0x2020000 0x0 0x100>;
198 #size-cells = <0>;
207 reg = <0x0 0x2030000 0x0 0x100>;
210 #size-cells = <0>;
220 reg = <0x0 0x03100000 0x0 0x60>;
222 clocks = <&k3_clks 39 0>;
229 reg = <0x0 0x2100000 0x0 0x400>;
234 #size-cells = <0>;
235 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
242 reg = <0x0 0x2110000 0x0 0x400>;
247 #size-cells = <0>;
255 reg = <0x0 0x2120000 0x0 0x400>;
260 #size-cells = <0>;
266 reg = <0x0 0x2130000 0x0 0x400>;
271 #size-cells = <0>;
277 reg = <0x0 0x2140000 0x0 0x400>;
282 #size-cells = <0>;
288 reg = <0x00 0x2400000 0x00 0x400>;
290 clocks = <&k3_clks 23 0>;
292 assigned-clocks = <&k3_clks 23 0>;
300 reg = <0x00 0x2410000 0x00 0x400>;
302 clocks = <&k3_clks 24 0>;
304 assigned-clocks = <&k3_clks 24 0>;
312 reg = <0x00 0x2420000 0x00 0x400>;
314 clocks = <&k3_clks 27 0>;
316 assigned-clocks = <&k3_clks 27 0>;
324 reg = <0x00 0x2430000 0x00 0x400>;
326 clocks = <&k3_clks 28 0>;
328 assigned-clocks = <&k3_clks 28 0>;
336 reg = <0x00 0x2440000 0x00 0x400>;
338 clocks = <&k3_clks 29 0>;
340 assigned-clocks = <&k3_clks 29 0>;
348 reg = <0x00 0x2450000 0x00 0x400>;
350 clocks = <&k3_clks 30 0>;
352 assigned-clocks = <&k3_clks 30 0>;
360 reg = <0x00 0x2460000 0x00 0x400>;
362 clocks = <&k3_clks 31 0>;
363 assigned-clocks = <&k3_clks 31 0>;
372 reg = <0x00 0x2470000 0x00 0x400>;
374 clocks = <&k3_clks 32 0>;
376 assigned-clocks = <&k3_clks 32 0>;
384 reg = <0x00 0x2480000 0x00 0x400>;
386 clocks = <&k3_clks 33 0>;
388 assigned-clocks = <&k3_clks 33 0>;
396 reg = <0x00 0x2490000 0x00 0x400>;
398 clocks = <&k3_clks 34 0>;
400 assigned-clocks = <&k3_clks 34 0>;
408 reg = <0x00 0x24a0000 0x00 0x400>;
410 clocks = <&k3_clks 25 0>;
412 assigned-clocks = <&k3_clks 25 0>;
420 reg = <0x00 0x24b0000 0x00 0x400>;
422 clocks = <&k3_clks 26 0>;
424 assigned-clocks = <&k3_clks 26 0>;
432 reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
434 clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;
439 ti,otap-del-sel-legacy = <0x0>;
440 ti,otap-del-sel-mmc-hs = <0x0>;
441 ti,otap-del-sel-sd-hs = <0x0>;
442 ti,otap-del-sel-sdr12 = <0x0>;
443 ti,otap-del-sel-sdr25 = <0x0>;
444 ti,otap-del-sel-sdr50 = <0x8>;
445 ti,otap-del-sel-sdr104 = <0x7>;
446 ti,otap-del-sel-ddr50 = <0x5>;
447 ti,otap-del-sel-ddr52 = <0x5>;
448 ti,otap-del-sel-hs200 = <0x5>;
449 ti,otap-del-sel-hs400 = <0x0>;
450 ti,trm-icp = <0x8>;
457 reg = <0x0 0x4fa0000 0x0 0x260>, <0x0 0x4fb0000 0x0 0x134>;
459 clocks = <&k3_clks 48 0>, <&k3_clks 48 1>;
462 ti,otap-del-sel-legacy = <0x0>;
463 ti,otap-del-sel-mmc-hs = <0x0>;
464 ti,otap-del-sel-sd-hs = <0x0>;
465 ti,otap-del-sel-sdr12 = <0x0>;
466 ti,otap-del-sel-sdr25 = <0x0>;
467 ti,otap-del-sel-sdr50 = <0x8>;
468 ti,otap-del-sel-sdr104 = <0x7>;
469 ti,otap-del-sel-ddr50 = <0x4>;
470 ti,otap-del-sel-ddr52 = <0x4>;
471 ti,otap-del-sel-hs200 = <0x7>;
472 ti,clkbuf-sel = <0x7>;
473 ti,trm-icp = <0x8>;
480 reg = <0 0x00100000 0 0x1c000>;
483 ranges = <0x0 0x0 0x00100000 0x1c000>;
487 reg = <0x00004080 0x4>;
492 reg = <0x00004090 0x4>;
498 mux-reg-masks = <0x4080 0x3>, /* SERDES0 lane select */
499 <0x4090 0x3>; /* SERDES1 lane select */
504 reg = <0x41e0 0x14>;
509 reg = <0x4140 0x18>;
516 reg = <0x0 0x4000000 0x0 0x4000>;
519 ranges = <0x0 0x0 0x4000000 0x20000>;
530 reg = <0x10000 0x10000>;
547 reg = <0x0 0x4100000 0x0 0x54>;
548 syscon-phy-power = <&scm_conf 0x4000>;
549 clocks = <&k3_clks 151 0>, <&k3_clks 151 1>;
551 #phy-cells = <0>;
556 reg = <0x0 0x4020000 0x0 0x4000>;
559 ranges = <0x0 0x0 0x4020000 0x20000>;
569 reg = <0x10000 0x10000>;
585 reg = <0x0 0x4110000 0x0 0x54>;
586 syscon-phy-power = <&scm_conf 0x4020>;
587 clocks = <&k3_clks 152 0>, <&k3_clks 152 1>;
589 #phy-cells = <0>;
594 reg = <0x0 0x00a00000 0x0 0x400>;
601 ti,interrupt-ranges = <0 392 32>;
608 ranges = <0x0 0x30800000 0x0 0x30800000 0x0 0xbc00000>;
616 reg = <0x0 0x310e0000 0x0 0x2000>;
623 ti,interrupt-ranges = <0 64 64>,
629 reg = <0x0 0x33d00000 0x0 0x100000>;
633 #interrupt-cells = <0>;
636 ti,interrupt-ranges = <0 0 256>;
643 reg = <0x00 0x32c00000 0x00 0x100000>,
644 <0x00 0x32400000 0x00 0x100000>,
645 <0x00 0x32800000 0x00 0x100000>;
652 reg = <0x00 0x30e00000 0x00 0x1000>;
658 reg = <0x00 0x31f80000 0x00 0x200>;
668 reg = <0x00 0x31f81000 0x00 0x200>;
678 reg = <0x00 0x31f82000 0x00 0x200>;
688 reg = <0x00 0x31f83000 0x00 0x200>;
698 reg = <0x00 0x31f84000 0x00 0x200>;
708 reg = <0x00 0x31f85000 0x00 0x200>;
718 reg = <0x00 0x31f86000 0x00 0x200>;
728 reg = <0x00 0x31f87000 0x00 0x200>;
738 reg = <0x00 0x31f88000 0x00 0x200>;
748 reg = <0x00 0x31f89000 0x00 0x200>;
758 reg = <0x00 0x31f8a000 0x00 0x200>;
768 reg = <0x00 0x31f8b000 0x00 0x200>;
778 reg = <0x0 0x3c000000 0x0 0x400000>,
779 <0x0 0x38000000 0x0 0x400000>,
780 <0x0 0x31120000 0x0 0x100>,
781 <0x0 0x33000000 0x0 0x40000>,
782 <0x0 0x31080000 0x0 0x40000>;
785 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
793 reg = <0x0 0x31150000 0x0 0x100>,
794 <0x0 0x34000000 0x0 0x100000>,
795 <0x0 0x35000000 0x0 0x100000>,
796 <0x0 0x30b00000 0x0 0x10000>,
797 <0x0 0x30c00000 0x0 0x10000>,
798 <0x0 0x30d00000 0x0 0x8000>;
808 ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */
809 <0xd>; /* TX_CHAN */
810 ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */
811 <0xa>; /* RX_CHAN */
812 ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */
817 reg = <0x0 0x310d0000 0x0 0x400>;
827 #clock-cells = <0>;
840 reg = <0x0 0x600000 0x0 0x100>;
848 ti,davinci-gpio-unbanked = <0>;
849 clocks = <&k3_clks 57 0>;
855 reg = <0x0 0x601000 0x0 0x100>;
863 ti,davinci-gpio-unbanked = <0>;
864 clocks = <&k3_clks 58 0>;
870 reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>;
875 ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000>,
876 <0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>;
877 ti,syscon-pcie-id = <&scm_conf 0x210>;
878 ti,syscon-pcie-mode = <&scm_conf 0x4060>;
879 bus-range = <0x0 0xff>;
884 msi-map = <0x0 &gic_its 0x0 0x10000>;
891 reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>;
894 ti,syscon-pcie-mode = <&scm_conf 0x4060>;
905 reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>;
910 ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000>,
911 <0x82000000 0 0x18030000 0x0 0x18030000 0 0x07FD0000>;
912 ti,syscon-pcie-id = <&scm_conf 0x210>;
913 ti,syscon-pcie-mode = <&scm_conf 0x4070>;
914 bus-range = <0x0 0xff>;
919 msi-map = <0x0 &gic_its 0x10000 0x10000>;
926 reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>;
929 ti,syscon-pcie-mode = <&scm_conf 0x4070>;
940 reg = <0x0 0x02b00000 0x0 0x2000>,
941 <0x0 0x02b08000 0x0 0x1000>;
947 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
950 clocks = <&k3_clks 104 0>;
958 reg = <0x0 0x02b10000 0x0 0x2000>,
959 <0x0 0x02b18000 0x0 0x1000>;
965 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
968 clocks = <&k3_clks 105 0>;
976 reg = <0x0 0x02b20000 0x0 0x2000>,
977 <0x0 0x02b28000 0x0 0x1000>;
983 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
986 clocks = <&k3_clks 106 0>;
994 reg = <0x0 0x06f03000 0x0 0x400>,
995 <0x0 0x06f03800 0x0 0x40>;
999 ti,camerrx-control = <&scm_conf 0x40c0>;
1001 clocks = <&k3_clks 2 0>;
1006 #size-cells = <0>;
1008 csi2_0: port@0 {
1009 reg = <0>;
1016 reg = <0x0 0x04a00000 0x0 0x1000>, /* common */
1017 <0x0 0x04a02000 0x0 0x1000>, /* vidl1 */
1018 <0x0 0x04a06000 0x0 0x1000>, /* vid */
1019 <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */
1020 <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */
1021 <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */
1022 <0x0 0x04a0b000 0x0 0x1000>; /* vp2 */
1049 #size-cells = <0>;
1056 reg = <0x0 0x3000000 0x0 0x100>;
1058 clocks = <&ehrpwm_tbclk 0>, <&k3_clks 40 0>;
1066 reg = <0x0 0x3010000 0x0 0x100>;
1068 clocks = <&ehrpwm_tbclk 1>, <&k3_clks 41 0>;
1076 reg = <0x0 0x3020000 0x0 0x100>;
1078 clocks = <&ehrpwm_tbclk 2>, <&k3_clks 42 0>;
1086 reg = <0x0 0x3030000 0x0 0x100>;
1088 clocks = <&ehrpwm_tbclk 3>, <&k3_clks 43 0>;
1096 reg = <0x0 0x3040000 0x0 0x100>;
1098 clocks = <&ehrpwm_tbclk 4>, <&k3_clks 44 0>;
1106 reg = <0x0 0x3050000 0x0 0x100>;
1108 clocks = <&ehrpwm_tbclk 5>, <&k3_clks 45 0>;
1115 reg = <0x00 0xb000000 0x00 0x80000>;
1119 ranges = <0x0 0x00 0xb000000 0x80000>;
1121 icssg0_mem: memories@0 {
1122 reg = <0x0 0x2000>,
1123 <0x2000 0x2000>,
1124 <0x10000 0x10000>;
1131 reg = <0x26000 0x200>;
1134 ranges = <0x0 0x26000 0x2000>;
1138 #size-cells = <0>;
1141 reg = <0x3c>;
1142 #clock-cells = <0>;
1150 reg = <0x30>;
1151 #clock-cells = <0>;
1162 reg = <0x2e000 0x1000>;
1168 reg = <0x2f000 0x1000>;
1174 reg = <0x32000 0x100>;
1179 reg = <0x33000 0x1000>;
1184 reg = <0x20000 0x2000>;
1203 reg = <0x34000 0x4000>,
1204 <0x22000 0x100>,
1205 <0x22400 0x100>;
1212 reg = <0x4000 0x2000>,
1213 <0x23000 0x100>,
1214 <0x23400 0x100>;
1221 reg = <0xa000 0x1800>,
1222 <0x25000 0x100>,
1223 <0x25400 0x100>;
1230 reg = <0x38000 0x4000>,
1231 <0x24000 0x100>,
1232 <0x24400 0x100>;
1239 reg = <0x6000 0x2000>,
1240 <0x23800 0x100>,
1241 <0x23c00 0x100>;
1248 reg = <0xc000 0x1800>,
1249 <0x25800 0x100>,
1250 <0x25c00 0x100>;
1257 reg = <0x32400 0x100>;
1261 #size-cells = <0>;
1269 reg = <0x00 0xb100000 0x00 0x80000>;
1273 ranges = <0x0 0x00 0xb100000 0x80000>;
1275 icssg1_mem: memories@0 {
1276 reg = <0x0 0x2000>,
1277 <0x2000 0x2000>,
1278 <0x10000 0x10000>;
1285 reg = <0x26000 0x200>;
1288 ranges = <0x0 0x26000 0x2000>;
1292 #size-cells = <0>;
1295 reg = <0x3c>;
1296 #clock-cells = <0>;
1304 reg = <0x30>;
1305 #clock-cells = <0>;
1316 reg = <0x2e000 0x1000>;
1322 reg = <0x2f000 0x1000>;
1328 reg = <0x32000 0x100>;
1333 reg = <0x33000 0x1000>;
1338 reg = <0x20000 0x2000>;
1357 reg = <0x34000 0x4000>,
1358 <0x22000 0x100>,
1359 <0x22400 0x100>;
1366 reg = <0x4000 0x2000>,
1367 <0x23000 0x100>,
1368 <0x23400 0x100>;
1375 reg = <0xa000 0x1800>,
1376 <0x25000 0x100>,
1377 <0x25400 0x100>;
1384 reg = <0x38000 0x4000>,
1385 <0x24000 0x100>,
1386 <0x24400 0x100>;
1393 reg = <0x6000 0x2000>,
1394 <0x23800 0x100>,
1395 <0x23c00 0x100>;
1402 reg = <0xc000 0x1800>,
1403 <0x25800 0x100>,
1404 <0x25c00 0x100>;
1411 reg = <0x32400 0x100>;
1415 #size-cells = <0>;
1423 reg = <0x00 0xb200000 0x00 0x80000>;
1427 ranges = <0x0 0x00 0xb200000 0x80000>;
1429 icssg2_mem: memories@0 {
1430 reg = <0x0 0x2000>,
1431 <0x2000 0x2000>,
1432 <0x10000 0x10000>;
1439 reg = <0x26000 0x200>;
1442 ranges = <0x0 0x26000 0x2000>;
1446 #size-cells = <0>;
1449 reg = <0x3c>;
1450 #clock-cells = <0>;
1458 reg = <0x30>;
1459 #clock-cells = <0>;
1470 reg = <0x2e000 0x1000>;
1476 reg = <0x2f000 0x1000>;
1482 reg = <0x32000 0x100>;
1487 reg = <0x33000 0x1000>;
1492 reg = <0x20000 0x2000>;
1511 reg = <0x34000 0x4000>,
1512 <0x22000 0x100>,
1513 <0x22400 0x100>;
1520 reg = <0x4000 0x2000>,
1521 <0x23000 0x100>,
1522 <0x23400 0x100>;
1529 reg = <0xa000 0x1800>,
1530 <0x25000 0x100>,
1531 <0x25400 0x100>;
1538 reg = <0x38000 0x4000>,
1539 <0x24000 0x100>,
1540 <0x24400 0x100>;
1547 reg = <0x6000 0x2000>,
1548 <0x23800 0x100>,
1549 <0x23c00 0x100>;
1556 reg = <0xc000 0x1800>,
1557 <0x25800 0x100>,
1558 <0x25c00 0x100>;
1565 reg = <0x32400 0x100>;
1569 #size-cells = <0>;