Lines Matching +full:0 +full:x23100000
13 #clock-cells = <0>;
15 clock-frequency = <0>;
22 reg = <0x00 0x70000000 0x00 0x200000>;
25 ranges = <0x0 0x00 0x70000000 0x200000>;
28 reg = <0x1c0000 0x20000>;
32 reg = <0x1e0000 0x1c000>;
36 reg = <0x1fc000 0x4000>;
43 reg = <0x0 0x43000000 0x0 0x20000>;
46 ranges = <0x0 0x0 0x43000000 0x20000>;
51 reg = <0x00000014 0x4>;
57 mux-reg-masks = <0x4080 0x3>; /* SERDES0 lane0 select */
62 reg = <0x4044 0x8>;
68 reg = <0x4130 0x4>;
80 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
81 <0x00 0x01840000 0x00 0xC0000>, /* GICR */
82 <0x01 0x00000000 0x00 0x2000>, /* GICC */
83 <0x01 0x00010000 0x00 0x1000>, /* GICH */
84 <0x01 0x00020000 0x00 0x2000>; /* GICV */
93 reg = <0x00 0x01820000 0x00 0x10000>;
94 socionext,synquacer-pre-its = <0x1000000 0x400000>;
106 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>;
115 reg = <0x00 0x4d000000 0x00 0x80000>,
116 <0x00 0x4a600000 0x00 0x80000>,
117 <0x00 0x4a400000 0x00 0x80000>;
124 reg = <0x00 0x48000000 0x00 0x100000>;
125 #interrupt-cells = <0>;
137 reg = <0x00 0x485c0100 0x00 0x100>,
138 <0x00 0x4c000000 0x00 0x20000>,
139 <0x00 0x4a820000 0x00 0x20000>,
140 <0x00 0x4aa40000 0x00 0x20000>,
141 <0x00 0x4bc00000 0x00 0x100000>,
142 <0x00 0x48600000 0x00 0x8000>,
143 <0x00 0x484a4000 0x00 0x2000>,
144 <0x00 0x484c2000 0x00 0x2000>,
145 <0x00 0x48420000 0x00 0x2000>;
153 ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
154 ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
155 ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
160 reg = <0x00 0x485c0000 0x00 0x100>,
161 <0x00 0x4a800000 0x00 0x20000>,
162 <0x00 0x4aa00000 0x00 0x40000>,
163 <0x00 0x4b800000 0x00 0x400000>,
164 <0x00 0x485e0000 0x00 0x20000>,
165 <0x00 0x484a0000 0x00 0x4000>,
166 <0x00 0x484c0000 0x00 0x2000>,
167 <0x00 0x48430000 0x00 0x4000>;
175 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
176 <0x24>, /* CPSW_TX_CHAN */
177 <0x25>, /* SAUL_TX_0_CHAN */
178 <0x26>, /* SAUL_TX_1_CHAN */
179 <0x27>, /* ICSSG_0_TX_CHAN */
180 <0x28>; /* ICSSG_1_TX_CHAN */
181 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
182 <0x11>, /* RING_CPSW_TX_CHAN */
183 <0x12>, /* RING_SAUL_TX_0_CHAN */
184 <0x13>, /* RING_SAUL_TX_1_CHAN */
185 <0x14>, /* RING_ICSSG_0_TX_CHAN */
186 <0x15>; /* RING_ICSSG_1_TX_CHAN */
187 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
188 <0x2b>, /* CPSW_RX_CHAN */
189 <0x2d>, /* SAUL_RX_0_CHAN */
190 <0x2f>, /* SAUL_RX_1_CHAN */
191 <0x31>, /* SAUL_RX_2_CHAN */
192 <0x33>, /* SAUL_RX_3_CHAN */
193 <0x35>, /* ICSSG_0_RX_CHAN */
194 <0x37>; /* ICSSG_1_RX_CHAN */
195 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
196 <0x2c>, /* FLOW_CPSW_RX_CHAN */
197 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
198 <0x32>, /* FLOW_SAUL_RX_2/3_CHAN */
199 <0x36>, /* FLOW_ICSSG_0_RX_CHAN */
200 <0x38>; /* FLOW_ICSSG_1_RX_CHAN */
212 reg = <0x00 0x44043000 0x00 0xfe0>;
236 reg = <0x00 0xf4000 0x00 0x2d0>;
239 pinctrl-single,function-mask = <0xffffffff>;
245 reg = <0x00 0x2400000 0x00 0x400>;
257 reg = <0x00 0x2410000 0x00 0x400>;
269 reg = <0x00 0x2420000 0x00 0x400>;
281 reg = <0x00 0x2430000 0x00 0x400>;
293 reg = <0x00 0x2440000 0x00 0x400>;
305 reg = <0x00 0x2450000 0x00 0x400>;
317 reg = <0x00 0x2460000 0x00 0x400>;
329 reg = <0x00 0x2470000 0x00 0x400>;
341 reg = <0x00 0x2480000 0x00 0x400>;
353 reg = <0x00 0x2490000 0x00 0x400>;
365 reg = <0x00 0x24a0000 0x00 0x400>;
377 reg = <0x00 0x24b0000 0x00 0x400>;
390 reg = <0x00 0x420000 0x00 0x1000>;
396 reg = <0x00 0x02800000 0x00 0x100>;
400 clocks = <&k3_clks 146 0>;
407 reg = <0x00 0x02810000 0x00 0x100>;
411 clocks = <&k3_clks 152 0>;
418 reg = <0x00 0x02820000 0x00 0x100>;
422 clocks = <&k3_clks 153 0>;
429 reg = <0x00 0x02830000 0x00 0x100>;
433 clocks = <&k3_clks 154 0>;
440 reg = <0x00 0x02840000 0x00 0x100>;
444 clocks = <&k3_clks 155 0>;
451 reg = <0x00 0x02850000 0x00 0x100>;
455 clocks = <&k3_clks 156 0>;
462 reg = <0x00 0x02860000 0x00 0x100>;
466 clocks = <&k3_clks 158 0>;
473 reg = <0x00 0x20000000 0x00 0x100>;
476 #size-cells = <0>;
485 reg = <0x00 0x20010000 0x00 0x100>;
488 #size-cells = <0>;
497 reg = <0x00 0x20020000 0x00 0x100>;
500 #size-cells = <0>;
509 reg = <0x00 0x20030000 0x00 0x100>;
512 #size-cells = <0>;
521 reg = <0x00 0x20100000 0x00 0x400>;
524 #size-cells = <0>;
526 clocks = <&k3_clks 141 0>;
527 dmas = <&main_pktdma 0xc300 0>, <&main_pktdma 0x4300 0>;
534 reg = <0x00 0x20110000 0x00 0x400>;
537 #size-cells = <0>;
539 clocks = <&k3_clks 142 0>;
545 reg = <0x00 0x20120000 0x00 0x400>;
548 #size-cells = <0>;
550 clocks = <&k3_clks 143 0>;
556 reg = <0x00 0x20130000 0x00 0x400>;
559 #size-cells = <0>;
561 clocks = <&k3_clks 144 0>;
567 reg = <0x00 0x20140000 0x00 0x400>;
570 #size-cells = <0>;
572 clocks = <&k3_clks 145 0>;
578 reg = <0x00 0x00a00000 0x00 0x800>;
585 ti,interrupt-ranges = <0 32 16>;
590 reg = <0x0 0x00600000 0x0 0x100>;
599 ti,davinci-gpio-unbanked = <0>;
601 clocks = <&k3_clks 77 0>;
607 reg = <0x0 0x00601000 0x0 0x100>;
616 ti,davinci-gpio-unbanked = <0>;
618 clocks = <&k3_clks 78 0>;
624 reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>;
627 clocks = <&k3_clks 57 0>, <&k3_clks 57 1>;
631 ti,trm-icp = <0x2>;
632 ti,otap-del-sel-legacy = <0x0>;
633 ti,otap-del-sel-mmc-hs = <0x0>;
634 ti,otap-del-sel-ddr52 = <0x6>;
635 ti,otap-del-sel-hs200 = <0x7>;
641 reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>;
646 ti,trm-icp = <0x2>;
647 ti,otap-del-sel-legacy = <0x0>;
648 ti,otap-del-sel-sd-hs = <0xf>;
649 ti,otap-del-sel-sdr12 = <0xf>;
650 ti,otap-del-sel-sdr25 = <0xf>;
651 ti,otap-del-sel-sdr50 = <0xc>;
652 ti,otap-del-sel-sdr104 = <0x6>;
653 ti,otap-del-sel-ddr50 = <0x9>;
654 ti,clkbuf-sel = <0x7>;
662 reg = <0x0 0x8000000 0x0 0x200000>;
664 ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>;
665 clocks = <&k3_clks 13 0>;
671 dmas = <&main_pktdma 0xC500 15>,
672 <&main_pktdma 0xC501 15>,
673 <&main_pktdma 0xC502 15>,
674 <&main_pktdma 0xC503 15>,
675 <&main_pktdma 0xC504 15>,
676 <&main_pktdma 0xC505 15>,
677 <&main_pktdma 0xC506 15>,
678 <&main_pktdma 0xC507 15>,
679 <&main_pktdma 0x4500 15>;
685 #size-cells = <0>;
693 ti,syscon-efuse = <&main_conf 0x200>;
707 reg = <0x0 0xf00 0x0 0x100>;
709 #size-cells = <0>;
710 clocks = <&k3_clks 13 0>;
718 reg = <0x0 0x3d000 0x0 0x400>;
730 reg = <0x0 0x39000000 0x0 0x400>;
733 clocks = <&k3_clks 84 0>;
735 assigned-clocks = <&k3_clks 84 0>;
745 reg = <0x0 0xa40000 0x0 0x800>;
748 pinctrl-single,function-mask = <0x000107ff>;
753 reg = <0x00 0xf900000 0x00 0x100>;
764 reg = <0x00 0xf400000 0x00 0x10000>,
765 <0x00 0xf410000 0x00 0x10000>,
766 <0x00 0xf420000 0x00 0x10000>;
770 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
783 reg = <0x00 0x28001000 0x00 0x1000>;
785 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
786 clocks = <&k3_clks 0 0>;
787 assigned-clocks = <&k3_clks 0 0>;
788 assigned-clock-parents = <&k3_clks 0 3>;
801 reg = <0x00 0x0fc00000 0x00 0x70000>;
808 reg = <0x00 0x0fc40000 0x00 0x100>,
809 <0x05 0x00000000 0x01 0x00000000>;
813 cdns,trigger-address = <0x0>;
814 #address-cells = <0x1>;
815 #size-cells = <0x0>;
827 reg = <0x00 0x2a000000 0x00 0x1000>;
833 reg = <0x00 0x29020000 0x00 0x200>;
844 reg = <0x00 0x29030000 0x00 0x200>;
855 reg = <0x00 0x29040000 0x00 0x200>;
866 reg = <0x00 0x29050000 0x00 0x200>;
877 reg = <0x00 0x29060000 0x00 0x200>;
887 reg = <0x00 0x29070000 0x00 0x200>;
897 ti,cluster-mode = <0>;
900 ranges = <0x78000000 0x00 0x78000000 0x10000>,
901 <0x78100000 0x00 0x78100000 0x10000>,
902 <0x78200000 0x00 0x78200000 0x08000>,
903 <0x78300000 0x00 0x78300000 0x08000>;
908 reg = <0x78000000 0x00010000>,
909 <0x78100000 0x00010000>;
913 ti,sci-proc-ids = <0x01 0xff>;
923 reg = <0x78200000 0x00008000>,
924 <0x78300000 0x00008000>;
928 ti,sci-proc-ids = <0x02 0xff>;
939 ti,cluster-mode = <0>;
942 ranges = <0x78400000 0x00 0x78400000 0x10000>,
943 <0x78500000 0x00 0x78500000 0x10000>,
944 <0x78600000 0x00 0x78600000 0x08000>,
945 <0x78700000 0x00 0x78700000 0x08000>;
950 reg = <0x78400000 0x00010000>,
951 <0x78500000 0x00010000>;
955 ti,sci-proc-ids = <0x06 0xff>;
965 reg = <0x78600000 0x00008000>,
966 <0x78700000 0x00008000>;
970 ti,sci-proc-ids = <0x07 0xff>;
984 clocks = <&k3_clks 162 0>, <&k3_clks 162 1>, <&serdes_refclk>;
989 ranges = <0x0f000000 0x0 0x0f000000 0x00010000>;
996 reg = <0x0f000000 0x00010000>;
998 resets = <&serdes_wiz0 0>;
1010 #size-cells = <0>;
1017 reg = <0x00 0x0f102000 0x00 0x1000>,
1018 <0x00 0x0f100000 0x00 0x400>,
1019 <0x00 0x0d000000 0x00 0x00800000>,
1020 <0x00 0x68000000 0x00 0x00001000>;
1025 ti,syscon-pcie-ctrl = <&main_conf 0x4070>;
1029 clocks = <&k3_clks 114 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>;
1033 bus-range = <0x0 0xff>;
1035 vendor-id = <0x104c>;
1036 device-id = <0xb010>;
1037 msi-map = <0x0 &gic_its 0x0 0x10000>;
1038 ranges = <0x01000000 0x00 0x68001000 0x00 0x68001000 0x00 0x0010000>,
1039 <0x02000000 0x00 0x68011000 0x00 0x68011000 0x00 0x7fef000>;
1040 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x00000010 0x0>;
1046 reg = <0x00 0x0f102000 0x00 0x1000>,
1047 <0x00 0x0f100000 0x00 0x400>,
1048 <0x00 0x0d000000 0x00 0x00800000>,
1049 <0x00 0x68000000 0x00 0x08000000>;
1053 ti,syscon-pcie-ctrl = <&main_conf 0x4070>;
1057 clocks = <&k3_clks 114 0>;
1066 reg = <0x0 0x23000000 0x0 0x100>;
1068 clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>;
1076 reg = <0x0 0x23010000 0x0 0x100>;
1078 clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>;
1086 reg = <0x0 0x23020000 0x0 0x100>;
1088 clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>;
1096 reg = <0x0 0x23030000 0x0 0x100>;
1098 clocks = <&epwm_tbclk 3>, <&k3_clks 89 0>;
1106 reg = <0x0 0x23040000 0x0 0x100>;
1108 clocks = <&epwm_tbclk 4>, <&k3_clks 90 0>;
1116 reg = <0x0 0x23050000 0x0 0x100>;
1118 clocks = <&epwm_tbclk 5>, <&k3_clks 91 0>;
1126 reg = <0x0 0x23060000 0x0 0x100>;
1128 clocks = <&epwm_tbclk 6>, <&k3_clks 92 0>;
1136 reg = <0x0 0x23070000 0x0 0x100>;
1138 clocks = <&epwm_tbclk 7>, <&k3_clks 93 0>;
1146 reg = <0x0 0x23080000 0x0 0x100>;
1148 clocks = <&epwm_tbclk 8>, <&k3_clks 94 0>;
1156 reg = <0x0 0x23100000 0x0 0x60>;
1158 clocks = <&k3_clks 51 0>;
1166 reg = <0x0 0x23110000 0x0 0x60>;
1168 clocks = <&k3_clks 52 0>;
1176 reg = <0x0 0x23120000 0x0 0x60>;
1178 clocks = <&k3_clks 53 0>;
1185 reg = <0x00 0xe000000 0x00 0x100>;
1186 clocks = <&k3_clks 125 0>;
1188 assigned-clocks = <&k3_clks 125 0>;
1194 reg = <0x00 0xe010000 0x00 0x100>;
1195 clocks = <&k3_clks 126 0>;
1197 assigned-clocks = <&k3_clks 126 0>;
1203 reg = <0x00 0x30000000 0x00 0x80000>;
1207 ranges = <0x0 0x00 0x30000000 0x80000>;
1209 icssg0_mem: memories@0 {
1210 reg = <0x0 0x2000>,
1211 <0x2000 0x2000>,
1212 <0x10000 0x10000>;
1218 reg = <0x26000 0x200>;
1221 ranges = <0x0 0x26000 0x2000>;
1225 #size-cells = <0>;
1228 reg = <0x3c>;
1229 #clock-cells = <0>;
1230 clocks = <&k3_clks 81 0>, /* icssg0_core_clk */
1237 reg = <0x30>;
1238 #clock-cells = <0>;
1249 reg = <0x32000 0x100>;
1254 reg = <0x33000 0x1000>;
1259 reg = <0x20000 0x2000>;
1278 reg = <0x34000 0x3000>,
1279 <0x22000 0x100>,
1280 <0x22400 0x100>;
1287 reg = <0x4000 0x2000>,
1288 <0x23000 0x100>,
1289 <0x23400 0x100>;
1296 reg = <0xa000 0x1800>,
1297 <0x25000 0x100>,
1298 <0x25400 0x100>;
1305 reg = <0x38000 0x3000>,
1306 <0x24000 0x100>,
1307 <0x24400 0x100>;
1314 reg = <0x6000 0x2000>,
1315 <0x23800 0x100>,
1316 <0x23c00 0x100>;
1323 reg = <0xc000 0x1800>,
1324 <0x25800 0x100>,
1325 <0x25c00 0x100>;
1332 reg = <0x32400 0x100>;
1336 #size-cells = <0>;
1344 reg = <0x00 0x30080000 0x00 0x80000>;
1348 ranges = <0x0 0x00 0x30080000 0x80000>;
1350 icssg1_mem: memories@0 {
1351 reg = <0x0 0x2000>,
1352 <0x2000 0x2000>,
1353 <0x10000 0x10000>;
1359 reg = <0x26000 0x200>;
1362 ranges = <0x0 0x26000 0x2000>;
1366 #size-cells = <0>;
1369 reg = <0x3c>;
1370 #clock-cells = <0>;
1371 clocks = <&k3_clks 82 0>, /* icssg1_core_clk */
1378 reg = <0x30>;
1379 #clock-cells = <0>;
1390 reg = <0x32000 0x100>;
1395 reg = <0x33000 0x1000>;
1400 reg = <0x20000 0x2000>;
1419 reg = <0x34000 0x4000>,
1420 <0x22000 0x100>,
1421 <0x22400 0x100>;
1428 reg = <0x4000 0x2000>,
1429 <0x23000 0x100>,
1430 <0x23400 0x100>;
1437 reg = <0xa000 0x1800>,
1438 <0x25000 0x100>,
1439 <0x25400 0x100>;
1446 reg = <0x38000 0x4000>,
1447 <0x24000 0x100>,
1448 <0x24400 0x100>;
1455 reg = <0x6000 0x2000>,
1456 <0x23800 0x100>,
1457 <0x23c00 0x100>;
1464 reg = <0xc000 0x1800>,
1465 <0x25800 0x100>,
1466 <0x25c00 0x100>;
1473 reg = <0x32400 0x100>;
1475 #size-cells = <0>;
1476 clocks = <&k3_clks 82 0>;
1485 reg = <0x00 0x20701000 0x00 0x200>,
1486 <0x00 0x20708000 0x00 0x8000>;
1489 clocks = <&k3_clks 98 5>, <&k3_clks 98 0>;
1494 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1500 reg = <0x00 0x20711000 0x00 0x200>,
1501 <0x00 0x20718000 0x00 0x8000>;
1504 clocks = <&k3_clks 99 5>, <&k3_clks 99 0>;
1509 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1515 reg = <0x00 0x40900000 0x00 0x1200>;
1519 ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>;
1520 dmas = <&main_pktdma 0xc001 0>, <&main_pktdma 0x4002 0>,
1521 <&main_pktdma 0x4003 0>;
1526 reg = <0x00 0x40910000 0x00 0x7d>;
1535 clocks = <&k3_clks 80 0>;
1537 reg = <0x00 0x3b000000 0x00 0x400>,
1538 <0x00 0x50000000 0x00 0x8000000>;
1554 reg = <0x00 0x25010000 0x00 0x2000>;
1557 clocks = <&k3_clks 54 0>;
1564 reg = <0x00 0xb00000 0x00 0x400>,
1565 <0x00 0xb01000 0x00 0x400>;