Lines Matching +full:omap4 +full:- +full:mcspi
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "pinctrl-single";
12 #pinctrl-cells = <1>;
13 pinctrl-single,register-width = <32>;
14 pinctrl-single,function-mask = <0xffffffff>;
24 compatible = "ti,am654-timer";
27 clock-names = "fck";
28 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
29 ti,timer-pwm;
34 compatible = "ti,am654-timer";
37 clock-names = "fck";
38 power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
39 ti,timer-pwm;
44 compatible = "ti,am654-timer";
47 clock-names = "fck";
48 power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
49 ti,timer-pwm;
54 compatible = "ti,am654-timer";
57 clock-names = "fck";
58 power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>;
59 ti,timer-pwm;
64 compatible = "ti,am64-uart", "ti,am654-uart";
67 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
69 clock-names = "fclk";
74 compatible = "ti,am64-i2c", "ti,omap4-i2c";
77 #address-cells = <1>;
78 #size-cells = <0>;
79 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
81 clock-names = "fck";
86 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
89 #address-cells = <1>;
90 #size-cells = <0>;
91 power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
97 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
100 #address-cells = <1>;
101 #size-cells = <0>;
102 power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
107 mcu_gpio_intr: interrupt-controller@4210000 {
108 compatible = "ti,sci-intr";
110 ti,intr-trigger-type = <1>;
111 interrupt-controller;
112 interrupt-parent = <&gic500>;
113 #interrupt-cells = <1>;
115 ti,sci-dev-id = <5>;
116 ti,interrupt-ranges = <0 104 4>;
120 compatible = "ti,am64-gpio", "ti,keystone-gpio";
122 gpio-controller;
123 #gpio-cells = <2>;
124 interrupt-parent = <&mcu_gpio_intr>;
126 interrupt-controller;
127 #interrupt-cells = <2>;
129 ti,davinci-gpio-unbanked = <0>;
130 power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
132 clock-names = "gpio";
137 compatible = "ti,j7-rti-wdt";
140 power-domains = <&k3_pds 131 TI_SCI_PD_EXCLUSIVE>;
141 assigned-clocks = <&k3_clks 131 0>;
142 assigned-clock-parents = <&k3_clks 131 2>;
151 reg-names = "m_can", "message_ram";
152 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
154 clock-names = "hclk", "cclk";
155 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
163 reg-names = "m_can", "message_ram";
164 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
166 clock-names = "hclk", "cclk";
167 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;