Lines Matching +full:0 +full:x4a800000
11 reg = <0x00 0x70000000 0x00 0x10000>;
14 ranges = <0x0 0x00 0x70000000 0x10000>;
19 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
20 <0x00 0x01880000 0x00 0xc0000>, /* GICR */
21 <0x00 0x01880000 0x00 0xc0000>, /* GICR */
22 <0x01 0x00000000 0x00 0x2000>, /* GICC */
23 <0x01 0x00010000 0x00 0x1000>, /* GICH */
24 <0x01 0x00020000 0x00 0x2000>; /* GICV */
38 reg = <0x00 0x01820000 0x00 0x10000>;
39 socionext,synquacer-pre-its = <0x1000000 0x400000>;
47 reg = <0x00 0x00100000 0x00 0x20000>;
50 ranges = <0x00 0x00 0x00100000 0x20000>;
54 reg = <0x4044 0x8>;
60 reg = <0x4130 0x4>;
70 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06000000>;
76 reg = <0x00 0x4d000000 0x00 0x80000>,
77 <0x00 0x4a600000 0x00 0x80000>,
78 <0x00 0x4a400000 0x00 0x80000>;
87 reg = <0x00 0x48000000 0x00 0x100000>;
88 #interrupt-cells = <0>;
100 reg = <0x00 0x485c0100 0x00 0x100>,
101 <0x00 0x4c000000 0x00 0x20000>,
102 <0x00 0x4a820000 0x00 0x20000>,
103 <0x00 0x4aa40000 0x00 0x20000>,
104 <0x00 0x4bc00000 0x00 0x100000>,
105 <0x00 0x48600000 0x00 0x8000>,
106 <0x00 0x484a4000 0x00 0x2000>,
107 <0x00 0x484c2000 0x00 0x2000>,
108 <0x00 0x48420000 0x00 0x2000>;
115 ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
116 ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
117 ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
122 reg = <0x00 0x485c0000 0x00 0x100>,
123 <0x00 0x4a800000 0x00 0x20000>,
124 <0x00 0x4aa00000 0x00 0x40000>,
125 <0x00 0x4b800000 0x00 0x400000>,
126 <0x00 0x485e0000 0x00 0x10000>,
127 <0x00 0x484a0000 0x00 0x2000>,
128 <0x00 0x484c0000 0x00 0x2000>,
129 <0x00 0x48430000 0x00 0x1000>;
136 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
137 <0x24>, /* CPSW_TX_CHAN */
138 <0x25>, /* SAUL_TX_0_CHAN */
139 <0x26>; /* SAUL_TX_1_CHAN */
140 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
141 <0x11>, /* RING_CPSW_TX_CHAN */
142 <0x12>, /* RING_SAUL_TX_0_CHAN */
143 <0x13>; /* RING_SAUL_TX_1_CHAN */
144 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
145 <0x2b>, /* CPSW_RX_CHAN */
146 <0x2d>, /* SAUL_RX_0_CHAN */
147 <0x2f>, /* SAUL_RX_1_CHAN */
148 <0x31>, /* SAUL_RX_2_CHAN */
149 <0x33>; /* SAUL_RX_3_CHAN */
150 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
151 <0x2c>, /* FLOW_CPSW_RX_CHAN */
152 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
153 <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */
162 ranges = <0x00 0x4e000000 0x00 0x4e000000 0x00 0x300000>;
168 reg = <0x00 0x4e0a0000 0x00 0x8000>;
169 #interrupt-cells = <0>;
175 ti,interrupt-ranges = <0 237 8>;
182 reg = <0x00 0x4e230000 0x00 0x100>,
183 <0x00 0x4e180000 0x00 0x8000>,
184 <0x00 0x4e100000 0x00 0x10000>;
190 ti,sci-rm-range-rchan = <0x21>;
197 reg = <0x00 0x44043000 0x00 0xfe0>;
224 reg = <0x00 0x43600000 0x00 0x10000>,
225 <0x00 0x44880000 0x00 0x20000>,
226 <0x00 0x44860000 0x00 0x20000>;
237 reg = <0x00 0xf4000 0x00 0x2ac>;
240 pinctrl-single,function-mask = <0xffffffff>;
245 reg = <0x00 0x2400000 0x00 0x400>;
257 reg = <0x00 0x2410000 0x00 0x400>;
269 reg = <0x00 0x2420000 0x00 0x400>;
281 reg = <0x00 0x2430000 0x00 0x400>;
293 reg = <0x00 0x2440000 0x00 0x400>;
305 reg = <0x00 0x2450000 0x00 0x400>;
317 reg = <0x00 0x2460000 0x00 0x400>;
329 reg = <0x00 0x2470000 0x00 0x400>;
341 reg = <0x00 0x02800000 0x00 0x100>;
344 clocks = <&k3_clks 146 0>;
351 reg = <0x00 0x02810000 0x00 0x100>;
354 clocks = <&k3_clks 152 0>;
361 reg = <0x00 0x02820000 0x00 0x100>;
364 clocks = <&k3_clks 153 0>;
371 reg = <0x00 0x02830000 0x00 0x100>;
374 clocks = <&k3_clks 154 0>;
381 reg = <0x00 0x02840000 0x00 0x100>;
384 clocks = <&k3_clks 155 0>;
391 reg = <0x00 0x02850000 0x00 0x100>;
394 clocks = <&k3_clks 156 0>;
401 reg = <0x00 0x02860000 0x00 0x100>;
404 clocks = <&k3_clks 158 0>;
411 reg = <0x00 0x20000000 0x00 0x100>;
414 #size-cells = <0>;
423 reg = <0x00 0x20010000 0x00 0x100>;
426 #size-cells = <0>;
435 reg = <0x00 0x20020000 0x00 0x100>;
438 #size-cells = <0>;
447 reg = <0x00 0x20030000 0x00 0x100>;
450 #size-cells = <0>;
459 reg = <0x00 0x20100000 0x00 0x400>;
462 #size-cells = <0>;
464 clocks = <&k3_clks 141 0>;
470 reg = <0x00 0x20110000 0x00 0x400>;
473 #size-cells = <0>;
475 clocks = <&k3_clks 142 0>;
481 reg = <0x00 0x20120000 0x00 0x400>;
484 #size-cells = <0>;
486 clocks = <&k3_clks 143 0>;
492 reg = <0x00 0x00a00000 0x00 0x800>;
499 ti,interrupt-ranges = <0 32 16>;
505 reg = <0x00 0x00600000 0x0 0x100>;
514 ti,davinci-gpio-unbanked = <0>;
516 clocks = <&k3_clks 77 0>;
523 reg = <0x00 0x00601000 0x0 0x100>;
532 ti,davinci-gpio-unbanked = <0>;
534 clocks = <&k3_clks 78 0>;
541 reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>;
546 ti,trm-icp = <0x2>;
547 ti,otap-del-sel-legacy = <0x0>;
548 ti,otap-del-sel-sd-hs = <0x0>;
549 ti,otap-del-sel-sdr12 = <0xf>;
550 ti,otap-del-sel-sdr25 = <0xf>;
551 ti,otap-del-sel-sdr50 = <0xc>;
552 ti,otap-del-sel-sdr104 = <0x6>;
553 ti,otap-del-sel-ddr50 = <0x9>;
554 ti,itap-del-sel-legacy = <0x0>;
555 ti,itap-del-sel-sd-hs = <0x0>;
556 ti,itap-del-sel-sdr12 = <0x0>;
557 ti,itap-del-sel-sdr25 = <0x0>;
558 ti,clkbuf-sel = <0x7>;
566 reg = <0x00 0x0f900000 0x00 0x800>;
569 ti,syscon-phy-pll-refclk = <&wkup_conf 0x4008>;
578 reg = <0x00 0x31000000 0x00 0x50000>;
579 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
580 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
589 reg = <0x00 0x0f910000 0x00 0x800>;
592 ti,syscon-phy-pll-refclk = <&wkup_conf 0x4018>;
601 reg = <0x00 0x31100000 0x00 0x50000>;
602 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
603 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
612 reg = <0x00 0x0fc00000 0x00 0x70000>;
620 reg = <0x00 0x0fc40000 0x00 0x100>,
621 <0x05 0x00000000 0x01 0x00000000>;
625 cdns,trigger-address = <0x0>;
632 #size-cells = <0>;
640 reg = <0x0 0x8000000 0x0 0x200000>;
642 ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>;
643 clocks = <&k3_clks 13 0>;
650 dmas = <&main_pktdma 0xc600 15>,
651 <&main_pktdma 0xc601 15>,
652 <&main_pktdma 0xc602 15>,
653 <&main_pktdma 0xc603 15>,
654 <&main_pktdma 0xc604 15>,
655 <&main_pktdma 0xc605 15>,
656 <&main_pktdma 0xc606 15>,
657 <&main_pktdma 0xc607 15>,
658 <&main_pktdma 0x4600 15>;
664 #size-cells = <0>;
672 ti,syscon-efuse = <&wkup_conf 0x200>;
686 reg = <0x0 0xf00 0x0 0x100>;
688 #size-cells = <0>;
689 clocks = <&k3_clks 13 0>;
696 reg = <0x0 0x3d000 0x0 0x400>;
708 reg = <0x00 0x2a000000 0x00 0x1000>;
714 reg = <0x00 0x29000000 0x00 0x200>;
723 reg = <0x00 0x29010000 0x00 0x200>;
732 reg = <0x00 0x29020000 0x00 0x200>;
741 reg = <0x00 0x29030000 0x00 0x200>;
750 reg = <0x00 0x20701000 0x00 0x200>,
751 <0x00 0x20708000 0x00 0x8000>;
759 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
765 reg = <0x00 0x0e000000 0x00 0x100>;
766 clocks = <&k3_clks 125 0>;
768 assigned-clocks = <&k3_clks 125 0>;
774 reg = <0x00 0x0e010000 0x00 0x100>;
775 clocks = <&k3_clks 126 0>;
777 assigned-clocks = <&k3_clks 126 0>;
783 reg = <0x00 0x0e020000 0x00 0x100>;
784 clocks = <&k3_clks 127 0>;
786 assigned-clocks = <&k3_clks 127 0>;
792 reg = <0x00 0x0e030000 0x00 0x100>;
793 clocks = <&k3_clks 128 0>;
795 assigned-clocks = <&k3_clks 128 0>;
801 reg = <0x00 0x0e040000 0x00 0x100>;
802 clocks = <&k3_clks 205 0>;
804 assigned-clocks = <&k3_clks 205 0>;
811 reg = <0x00 0x23000000 0x00 0x100>;
813 clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>;
821 reg = <0x00 0x23010000 0x00 0x100>;
823 clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>;
831 reg = <0x00 0x23020000 0x00 0x100>;
833 clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>;
841 reg = <0x00 0x23100000 0x00 0x100>;
843 clocks = <&k3_clks 51 0>;
851 reg = <0x00 0x23110000 0x00 0x100>;
853 clocks = <&k3_clks 52 0>;
861 reg = <0x00 0x23120000 0x00 0x100>;
863 clocks = <&k3_clks 53 0>;
870 reg = <0x00 0x02b00000 0x00 0x2000>,
871 <0x00 0x02b08000 0x00 0x400>;
877 dmas = <&main_bcdma 0 0xc500 0>, <&main_bcdma 0 0x4500 0>;
880 clocks = <&k3_clks 190 0>;
882 assigned-clocks = <&k3_clks 190 0>;
890 reg = <0x00 0x02b10000 0x00 0x2000>,
891 <0x00 0x02b18000 0x00 0x400>;
897 dmas = <&main_bcdma 0 0xc501 0>, <&main_bcdma 0 0x4501 0>;
900 clocks = <&k3_clks 191 0>;
902 assigned-clocks = <&k3_clks 191 0>;
910 reg = <0x00 0x02b20000 0x00 0x2000>,
911 <0x00 0x02b28000 0x00 0x400>;
917 dmas = <&main_bcdma 0 0xc502 0>, <&main_bcdma 0 0x4502 0>;
920 clocks = <&k3_clks 192 0>;
922 assigned-clocks = <&k3_clks 192 0>;
930 dmas = <&main_bcdma_csi 0 0x5000 0>;
932 reg = <0x00 0x30102000 0x00 0x1000>;
941 reg = <0x00 0x30101000 0x00 0x1000>;
942 clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>,
943 <&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>;
951 #size-cells = <0>;
953 csi0_port0: port@0 {
954 reg = <0>;
983 reg = <0x00 0x30110000 0x00 0x1100>;
984 #phy-cells = <0>;