Lines Matching +full:tshsl +full:- +full:ns
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
8 /dts-v1/;
10 #include "k3-am62x-sk-common.dtsi"
13 compatible = "ti,am625-sk", "ti,am625";
16 opp-table {
17 /* Add 1.4GHz OPP for am625-sk board. Requires VDD_CORE to be at 0.85V */
18 opp-1400000000 {
19 opp-hz = /bits/ 64 <1400000000>;
20 opp-supported-hw = <0x01 0x0004>;
21 clock-latency-ns = <6000000>;
32 vmain_pd: regulator-0 {
34 bootph-all;
35 compatible = "regulator-fixed";
36 regulator-name = "vmain_pd";
37 regulator-min-microvolt = <5000000>;
38 regulator-max-microvolt = <5000000>;
39 regulator-always-on;
40 regulator-boot-on;
43 vcc_5v0: regulator-1 {
45 bootph-all;
46 compatible = "regulator-fixed";
47 regulator-name = "vcc_5v0";
48 regulator-min-microvolt = <5000000>;
49 regulator-max-microvolt = <5000000>;
50 vin-supply = <&vmain_pd>;
51 regulator-always-on;
52 regulator-boot-on;
55 vcc_3v3_sys: regulator-2 {
56 /* output of LM61460-Q1 */
57 bootph-all;
58 compatible = "regulator-fixed";
59 regulator-name = "vcc_3v3_sys";
60 regulator-min-microvolt = <3300000>;
61 regulator-max-microvolt = <3300000>;
62 vin-supply = <&vmain_pd>;
63 regulator-always-on;
64 regulator-boot-on;
67 vdd_mmc1: regulator-3 {
69 bootph-all;
70 compatible = "regulator-fixed";
71 regulator-name = "vdd_mmc1";
72 regulator-min-microvolt = <3300000>;
73 regulator-max-microvolt = <3300000>;
74 regulator-boot-on;
75 enable-active-high;
76 vin-supply = <&vcc_3v3_sys>;
80 vdd_sd_dv: regulator-4 {
82 bootph-all;
83 compatible = "regulator-gpio";
84 regulator-name = "tlv71033";
85 pinctrl-names = "default";
86 pinctrl-0 = <&vdd_sd_dv_pins_default>;
87 regulator-min-microvolt = <1800000>;
88 regulator-max-microvolt = <3300000>;
89 regulator-boot-on;
90 vin-supply = <&vcc_5v0>;
96 vcc_1v8: regulator-5 {
98 compatible = "regulator-fixed";
99 regulator-name = "vcc_1v8";
100 regulator-min-microvolt = <1800000>;
101 regulator-max-microvolt = <1800000>;
102 vin-supply = <&vcc_3v3_sys>;
103 regulator-always-on;
104 regulator-boot-on;
109 main_rgmii2_pins_default: main-rgmii2-default-pins {
110 bootph-all;
111 pinctrl-single,pins = <
127 ospi0_pins_default: ospi0-default-pins {
128 bootph-all;
129 pinctrl-single,pins = <
144 vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
145 bootph-all;
146 pinctrl-single,pins = <
151 main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-default-pins {
152 bootph-all;
153 pinctrl-single,pins = <
160 bootph-all;
164 bootph-all;
168 bootph-all;
170 bootph-all;
173 gpio-controller;
174 #gpio-cells = <2>;
175 gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST",
188 interrupt-parent = <&main_gpio1>;
190 interrupt-controller;
191 #interrupt-cells = <2>;
193 pinctrl-names = "default";
194 pinctrl-0 = <&main_gpio1_ioexp_intr_pins_default>;
199 vmmc-supply = <&vdd_mmc1>;
200 vqmmc-supply = <&vdd_sd_dv>;
204 pinctrl-names = "default";
205 pinctrl-0 = <&main_rgmii1_pins_default>, <&main_rgmii2_pins_default>;
209 phy-mode = "rgmii-rxid";
210 phy-handle = <&cpsw3g_phy1>;
214 cpsw3g_phy1: ethernet-phy@1 {
216 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
217 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
218 ti,min-output-impedance;
223 mbox_m4_0: mbox-m4-0 {
224 ti,mbox-rx = <0 0 0>;
225 ti,mbox-tx = <1 0 0>;
230 bootph-all;
234 bootph-all;
236 pinctrl-names = "default";
237 pinctrl-0 = <&ospi0_pins_default>;
240 bootph-all;
241 compatible = "jedec,spi-nor";
243 spi-tx-bus-width = <8>;
244 spi-rx-bus-width = <8>;
245 spi-max-frequency = <25000000>;
246 cdns,tshsl-ns = <60>;
247 cdns,tsd2d-ns = <60>;
248 cdns,tchsh-ns = <60>;
249 cdns,tslch-ns = <60>;
250 cdns,read-delay = <4>;
253 bootph-all;
254 compatible = "fixed-partitions";
255 #address-cells = <1>;
256 #size-cells = <1>;
269 label = "ospi.u-boot";
289 bootph-pre-ram;
298 DVDD-supply = <&vcc_1v8>;