Lines Matching +full:0 +full:x485c0000
11 reg = <0x00 0x70000000 0x00 0x10000>;
14 ranges = <0x0 0x00 0x70000000 0x10000>;
24 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
25 <0x00 0x01880000 0x00 0xc0000>, /* GICR */
26 <0x00 0x01880000 0x00 0xc0000>, /* GICR */
27 <0x01 0x00000000 0x00 0x2000>, /* GICC */
28 <0x01 0x00010000 0x00 0x1000>, /* GICH */
29 <0x01 0x00020000 0x00 0x2000>; /* GICV */
38 reg = <0x00 0x01820000 0x00 0x10000>;
39 socionext,synquacer-pre-its = <0x1000000 0x400000>;
47 reg = <0x00 0x00100000 0x00 0x20000>;
50 ranges = <0x0 0x00 0x00100000 0x20000>;
54 reg = <0x4044 0x8>;
60 reg = <0x4130 0x4>;
66 reg = <0x82e0 0x4>;
67 clocks = <&k3_clks 157 0>;
68 assigned-clocks = <&k3_clks 157 0>;
70 #clock-cells = <0>;
75 reg = <0x82e4 0x4>;
79 #clock-cells = <0>;
89 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>;
98 reg = <0x00 0x4d000000 0x00 0x80000>,
99 <0x00 0x4a600000 0x00 0x80000>,
100 <0x00 0x4a400000 0x00 0x80000>;
107 reg = <0x00 0x48000000 0x00 0x100000>;
108 #interrupt-cells = <0>;
120 reg = <0x00 0x485c0100 0x00 0x100>,
121 <0x00 0x4c000000 0x00 0x20000>,
122 <0x00 0x4a820000 0x00 0x20000>,
123 <0x00 0x4aa40000 0x00 0x20000>,
124 <0x00 0x4bc00000 0x00 0x100000>,
125 <0x00 0x48600000 0x00 0x8000>,
126 <0x00 0x484a4000 0x00 0x2000>,
127 <0x00 0x484c2000 0x00 0x2000>,
128 <0x00 0x48420000 0x00 0x2000>;
136 ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
137 ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
138 ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
143 reg = <0x00 0x485c0000 0x00 0x100>,
144 <0x00 0x4a800000 0x00 0x20000>,
145 <0x00 0x4aa00000 0x00 0x40000>,
146 <0x00 0x4b800000 0x00 0x400000>,
147 <0x00 0x485e0000 0x00 0x10000>,
148 <0x00 0x484a0000 0x00 0x2000>,
149 <0x00 0x484c0000 0x00 0x2000>,
150 <0x00 0x48430000 0x00 0x1000>;
158 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
159 <0x24>, /* CPSW_TX_CHAN */
160 <0x25>, /* SAUL_TX_0_CHAN */
161 <0x26>; /* SAUL_TX_1_CHAN */
162 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
163 <0x11>, /* RING_CPSW_TX_CHAN */
164 <0x12>, /* RING_SAUL_TX_0_CHAN */
165 <0x13>; /* RING_SAUL_TX_1_CHAN */
166 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
167 <0x2b>, /* CPSW_RX_CHAN */
168 <0x2d>, /* SAUL_RX_0_CHAN */
169 <0x2f>, /* SAUL_RX_1_CHAN */
170 <0x31>, /* SAUL_RX_2_CHAN */
171 <0x33>; /* SAUL_RX_3_CHAN */
172 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
173 <0x2c>, /* FLOW_CPSW_RX_CHAN */
174 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
175 <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */
187 reg = <0x00 0x44043000 0x00 0xfe0>;
210 reg = <0x00 0x40900000 0x00 0x1200>;
213 ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>;
215 dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>,
216 <&main_pktdma 0x7507 0>;
225 reg = <0x00 0x43600000 0x00 0x10000>,
226 <0x00 0x44880000 0x00 0x20000>,
227 <0x00 0x44860000 0x00 0x20000>;
239 reg = <0x00 0xf4000 0x00 0x2ac>;
242 pinctrl-single,function-mask = <0xffffffff>;
248 reg = <0x00 0x420000 0x00 0x1000>;
255 reg = <0x00 0x2400000 0x00 0x400>;
267 reg = <0x00 0x2410000 0x00 0x400>;
279 reg = <0x00 0x2420000 0x00 0x400>;
291 reg = <0x00 0x2430000 0x00 0x400>;
303 reg = <0x00 0x2440000 0x00 0x400>;
315 reg = <0x00 0x2450000 0x00 0x400>;
327 reg = <0x00 0x2460000 0x00 0x400>;
339 reg = <0x00 0x2470000 0x00 0x400>;
351 reg = <0x00 0x02800000 0x00 0x100>;
354 clocks = <&k3_clks 146 0>;
361 reg = <0x00 0x02810000 0x00 0x100>;
364 clocks = <&k3_clks 152 0>;
371 reg = <0x00 0x02820000 0x00 0x100>;
374 clocks = <&k3_clks 153 0>;
381 reg = <0x00 0x02830000 0x00 0x100>;
384 clocks = <&k3_clks 154 0>;
391 reg = <0x00 0x02840000 0x00 0x100>;
394 clocks = <&k3_clks 155 0>;
401 reg = <0x00 0x02850000 0x00 0x100>;
404 clocks = <&k3_clks 156 0>;
411 reg = <0x00 0x02860000 0x00 0x100>;
414 clocks = <&k3_clks 158 0>;
421 reg = <0x00 0x20000000 0x00 0x100>;
424 #size-cells = <0>;
433 reg = <0x00 0x20010000 0x00 0x100>;
436 #size-cells = <0>;
445 reg = <0x00 0x20020000 0x00 0x100>;
448 #size-cells = <0>;
457 reg = <0x00 0x20030000 0x00 0x100>;
460 #size-cells = <0>;
469 reg = <0x00 0x20100000 0x00 0x400>;
472 #size-cells = <0>;
474 clocks = <&k3_clks 141 0>;
480 reg = <0x00 0x20110000 0x00 0x400>;
483 #size-cells = <0>;
485 clocks = <&k3_clks 142 0>;
491 reg = <0x00 0x20120000 0x00 0x400>;
494 #size-cells = <0>;
496 clocks = <&k3_clks 143 0>;
502 reg = <0x00 0x00a00000 0x00 0x800>;
509 ti,interrupt-ranges = <0 32 16>;
514 reg = <0x0 0x00600000 0x0 0x100>;
515 gpio-ranges = <&main_pmx0 0 0 32>,
526 ti,davinci-gpio-unbanked = <0>;
528 clocks = <&k3_clks 77 0>;
534 reg = <0x0 0x00601000 0x0 0x100>;
536 gpio-ranges = <&main_pmx0 0 94 41>,
547 ti,davinci-gpio-unbanked = <0>;
549 clocks = <&k3_clks 78 0>;
555 reg = <0x00 0x0fa10000 0x00 0x1000>, <0x00 0x0fa18000 0x00 0x400>;
564 ti,trm-icp = <0x2>;
566 ti,clkbuf-sel = <0x7>;
567 ti,otap-del-sel-legacy = <0x0>;
568 ti,otap-del-sel-mmc-hs = <0x0>;
569 ti,otap-del-sel-ddr52 = <0x5>;
570 ti,otap-del-sel-hs200 = <0x5>;
571 ti,itap-del-sel-legacy = <0xa>;
572 ti,itap-del-sel-mmc-hs = <0x1>;
578 reg = <0x00 0x0fa00000 0x00 0x1000>, <0x00 0x0fa08000 0x00 0x400>;
583 ti,trm-icp = <0x2>;
584 ti,otap-del-sel-legacy = <0x8>;
585 ti,otap-del-sel-sd-hs = <0x0>;
586 ti,otap-del-sel-sdr12 = <0x0>;
587 ti,otap-del-sel-sdr25 = <0x0>;
588 ti,otap-del-sel-sdr50 = <0x8>;
589 ti,otap-del-sel-sdr104 = <0x7>;
590 ti,otap-del-sel-ddr50 = <0x4>;
591 ti,itap-del-sel-legacy = <0xa>;
592 ti,itap-del-sel-sd-hs = <0x1>;
593 ti,itap-del-sel-sdr12 = <0xa>;
594 ti,itap-del-sel-sdr25 = <0x1>;
595 ti,clkbuf-sel = <0x7>;
602 reg = <0x00 0x0fa20000 0x00 0x1000>, <0x00 0x0fa28000 0x00 0x400>;
607 ti,trm-icp = <0x2>;
608 ti,otap-del-sel-legacy = <0x8>;
609 ti,otap-del-sel-sd-hs = <0x0>;
610 ti,otap-del-sel-sdr12 = <0x0>;
611 ti,otap-del-sel-sdr25 = <0x0>;
612 ti,otap-del-sel-sdr50 = <0x8>;
613 ti,otap-del-sel-sdr104 = <0x7>;
614 ti,otap-del-sel-ddr50 = <0x8>;
615 ti,itap-del-sel-legacy = <0xa>;
616 ti,itap-del-sel-sd-hs = <0xa>;
617 ti,itap-del-sel-sdr12 = <0xa>;
618 ti,itap-del-sel-sdr25 = <0x1>;
619 ti,clkbuf-sel = <0x7>;
625 reg = <0x00 0x0f900000 0x00 0x800>;
628 ti,syscon-phy-pll-refclk = <&wkup_conf 0x4008>;
637 reg = <0x00 0x31000000 0x00 0x50000>;
638 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
639 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
648 reg = <0x00 0x0f910000 0x00 0x800>;
651 ti,syscon-phy-pll-refclk = <&wkup_conf 0x4018>;
660 reg = <0x00 0x31100000 0x00 0x50000>;
661 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
662 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
671 reg = <0x00 0x0fc00000 0x00 0x70000>;
678 reg = <0x00 0x0fc40000 0x00 0x100>,
679 <0x05 0x00000000 0x01 0x00000000>;
683 cdns,trigger-address = <0x0>;
690 #size-cells = <0>;
697 reg = <0x00 0x0fd00000 0x00 0x20000>;
698 clocks = <&k3_clks 187 0>;
708 reg = <0x00 0x08000000 0x00 0x200000>;
710 ranges = <0x00 0x00 0x00 0x08000000 0x00 0x200000>;
711 clocks = <&k3_clks 13 0>;
717 dmas = <&main_pktdma 0xc600 15>,
718 <&main_pktdma 0xc601 15>,
719 <&main_pktdma 0xc602 15>,
720 <&main_pktdma 0xc603 15>,
721 <&main_pktdma 0xc604 15>,
722 <&main_pktdma 0xc605 15>,
723 <&main_pktdma 0xc606 15>,
724 <&main_pktdma 0xc607 15>,
725 <&main_pktdma 0x4600 15>;
731 #size-cells = <0>;
739 ti,syscon-efuse = <&wkup_conf 0x200>;
753 reg = <0x00 0xf00 0x00 0x100>;
755 #size-cells = <0>;
756 clocks = <&k3_clks 13 0>;
764 reg = <0x00 0x3d000 0x00 0x400>;
776 reg = <0x00 0x30200000 0x00 0x1000>, /* common */
777 <0x00 0x30202000 0x00 0x1000>, /* vidl1 */
778 <0x00 0x30206000 0x00 0x1000>, /* vid */
779 <0x00 0x30207000 0x00 0x1000>, /* ovr1 */
780 <0x00 0x30208000 0x00 0x1000>, /* ovr2 */
781 <0x00 0x3020a000 0x00 0x1000>, /* vp1: Used for OLDI */
782 <0x00 0x3020b000 0x00 0x1000>; /* vp2: Used as DPI Out */
795 #size-cells = <0>;
801 reg = <0x00 0x2a000000 0x00 0x1000>;
807 reg = <0x00 0x29000000 0x00 0x200>;
818 reg = <0x00 0x23100000 0x00 0x100>;
820 clocks = <&k3_clks 51 0>;
828 reg = <0x00 0x23110000 0x00 0x100>;
830 clocks = <&k3_clks 52 0>;
838 reg = <0x00 0x23120000 0x00 0x100>;
840 clocks = <&k3_clks 53 0>;
847 reg = <0x00 0x20701000 0x00 0x200>,
848 <0x00 0x20708000 0x00 0x8000>;
856 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
862 reg = <0x00 0x0e000000 0x00 0x100>;
863 clocks = <&k3_clks 125 0>;
865 assigned-clocks = <&k3_clks 125 0>;
871 reg = <0x00 0x0e010000 0x00 0x100>;
872 clocks = <&k3_clks 126 0>;
874 assigned-clocks = <&k3_clks 126 0>;
880 reg = <0x00 0x0e020000 0x00 0x100>;
881 clocks = <&k3_clks 127 0>;
883 assigned-clocks = <&k3_clks 127 0>;
889 reg = <0x00 0x0e030000 0x00 0x100>;
890 clocks = <&k3_clks 128 0>;
892 assigned-clocks = <&k3_clks 128 0>;
898 reg = <0x00 0x0e0f0000 0x00 0x100>;
899 clocks = <&k3_clks 130 0>;
901 assigned-clocks = <&k3_clks 130 0>;
908 reg = <0x00 0x23000000 0x00 0x100>;
910 clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>;
918 reg = <0x00 0x23010000 0x00 0x100>;
920 clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>;
928 reg = <0x00 0x23020000 0x00 0x100>;
930 clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>;
937 reg = <0x00 0x02b00000 0x00 0x2000>,
938 <0x00 0x02b08000 0x00 0x400>;
944 dmas = <&main_bcdma 0 0xc500 0>, <&main_bcdma 0 0x4500 0>;
947 clocks = <&k3_clks 190 0>;
949 assigned-clocks = <&k3_clks 190 0>;
957 reg = <0x00 0x02b10000 0x00 0x2000>,
958 <0x00 0x02b18000 0x00 0x400>;
964 dmas = <&main_bcdma 0 0xc501 0>, <&main_bcdma 0 0x4501 0>;
967 clocks = <&k3_clks 191 0>;
969 assigned-clocks = <&k3_clks 191 0>;
977 reg = <0x00 0x02b20000 0x00 0x2000>,
978 <0x00 0x02b28000 0x00 0x400>;
984 dmas = <&main_bcdma 0 0xc502 0>, <&main_bcdma 0 0x4502 0>;
987 clocks = <&k3_clks 192 0>;
989 assigned-clocks = <&k3_clks 192 0>;
997 dmas = <&main_bcdma 0 0x4700 0>;
999 reg = <0x00 0x30102000 0x00 0x1000>;
1008 reg = <0x00 0x30101000 0x00 0x1000>;
1009 clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>,
1010 <&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>;
1018 #size-cells = <0>;
1020 csi0_port0: port@0 {
1021 reg = <0>;
1050 reg = <0x00 0x30110000 0x00 0x1100>;
1051 #phy-cells = <0>;