Lines Matching +full:psci +full:- +full:0
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
16 psci {
17 compatible = "arm,psci-1.0";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu0: cpu@0 {
26 compatible = "arm,cortex-a53";
28 reg = <0x0>;
29 enable-method = "psci";
30 next-level-cache = <&l2>;
31 cpu-idle-states = <&CPU_SLEEP_0>;
35 compatible = "arm,cortex-a53";
37 reg = <0x1>;
38 enable-method = "psci";
39 next-level-cache = <&l2>;
40 cpu-idle-states = <&CPU_SLEEP_0>;
44 compatible = "arm,cortex-a53";
46 reg = <0x2>;
47 enable-method = "psci";
48 next-level-cache = <&l2>;
49 cpu-idle-states = <&CPU_SLEEP_0>;
53 compatible = "arm,cortex-a53";
55 reg = <0x3>;
56 enable-method = "psci";
57 next-level-cache = <&l2>;
58 cpu-idle-states = <&CPU_SLEEP_0>;
65 idle-states {
66 entry-method = "psci";
67 CPU_SLEEP_0: cpu-sleep-0 {
68 compatible = "arm,idle-state";
69 local-timer-stop;
70 arm,psci-suspend-param = <0x0010000>;
71 entry-latency-us = <75>;
72 exit-latency-us = <155>;
73 min-residency-us = <1000>;
79 compatible = "fixed-clock";
80 #clock-cells = <0>;
81 clock-frequency = <25000000>;
85 compatible = "arm,cortex-a53-pmu";
90 interrupt-affinity = <&cpu0>,
97 compatible = "arm,armv8-timer";
105 compatible = "simple-bus";
106 #address-cells = <1>;
107 #size-cells = <1>;
108 ranges = <0 0 0xf7000000 0x1000000>;
110 gic: interrupt-controller@901000 {
111 compatible = "arm,gic-400";
112 #interrupt-cells = <3>;
113 interrupt-controller;
114 reg = <0x901000 0x1000>,
115 <0x902000 0x2000>,
116 <0x904000 0x2000>,
117 <0x906000 0x2000>;
122 compatible = "simple-bus";
123 #address-cells = <1>;
124 #size-cells = <1>;
125 ranges = <0 0xe80000 0x10000>;
128 compatible = "snps,dw-apb-uart";
129 reg = <0xc00 0x100>;
132 reg-shift = <2>;
137 compatible = "snps,dw-apb-gpio";
138 reg = <0x1800 0x400>;
139 #address-cells = <1>;
140 #size-cells = <0>;
142 porta: gpio-port@0 {
143 compatible = "snps,dw-apb-gpio-port";
144 gpio-controller;
145 #gpio-cells = <2>;
147 reg = <0>;
148 interrupt-controller;
149 #interrupt-cells = <2>;
155 compatible = "snps,dw-apb-gpio";
156 reg = <0x2000 0x400>;
157 #address-cells = <1>;
158 #size-cells = <0>;
160 portb: gpio-port@1 {
161 compatible = "snps,dw-apb-gpio-port";
162 gpio-controller;
163 #gpio-cells = <2>;
165 reg = <0>;
166 interrupt-controller;
167 #interrupt-cells = <2>;