Lines Matching +full:syscfg +full:- +full:dlyb
1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
6 #include <dt-bindings/clock/st,stm32mp25-rcc.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/reset/st,stm32mp25-rcc.h>
9 #include <dt-bindings/regulator/st,stm32mp25-regulator.h>
10 #include <dt-bindings/phy/phy.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
17 #address-cells = <1>;
18 #size-cells = <0>;
21 compatible = "arm,cortex-a35";
24 enable-method = "psci";
25 power-domains = <&CPU_PD0>;
26 power-domain-names = "psci";
30 arm-pmu {
31 compatible = "arm,cortex-a35-pmu";
33 interrupt-affinity = <&cpu0>;
34 interrupt-parent = <&intc>;
38 compatible = "arm,smc-wdt";
39 arm,smc-id = <0xb200005a>;
45 #clock-cells = <0>;
46 compatible = "fixed-clock";
47 clock-frequency = <0>;
50 clk_rcbsec: clk-rcbsec {
51 #clock-cells = <0>;
52 compatible = "fixed-clock";
53 clock-frequency = <64000000>;
59 compatible = "linaro,optee-tz";
61 interrupt-parent = <&intc>;
66 compatible = "linaro,scmi-optee";
67 #address-cells = <1>;
68 #size-cells = <0>;
69 linaro,optee-channel-id = <0>;
73 #clock-cells = <1>;
78 #reset-cells = <1>;
85 #address-cells = <1>;
86 #size-cells = <0>;
90 regulator-name = "vddio1";
94 regulator-name = "vddio2";
98 regulator-name = "vddio3";
102 regulator-name = "vddio4";
106 regulator-name = "vdd33ucpd";
110 regulator-name = "vdda18adc";
117 intc: interrupt-controller@4ac00000 {
118 compatible = "arm,gic-400";
119 #interrupt-cells = <3>;
120 interrupt-controller;
128 compatible = "arm,psci-1.0";
131 CPU_PD0: power-domain-cpu0 {
132 #power-domain-cells = <0>;
133 power-domains = <&CLUSTER_PD>;
136 CLUSTER_PD: power-domain-cluster {
137 #power-domain-cells = <0>;
138 power-domains = <&RET_PD>;
141 RET_PD: power-domain-retention {
142 #power-domain-cells = <0>;
147 compatible = "arm,armv8-timer";
148 interrupt-parent = <&intc>;
153 arm,no-tick-in-suspend;
157 compatible = "simple-bus";
158 #address-cells = <1>;
159 #size-cells = <1>;
160 interrupt-parent = <&intc>;
163 hpdma: dma-controller@40400000 {
164 compatible = "st,stm32mp25-dma3";
183 #dma-cells = <3>;
186 hpdma2: dma-controller@40410000 {
187 compatible = "st,stm32mp25-dma3";
206 #dma-cells = <3>;
209 hpdma3: dma-controller@40420000 {
210 compatible = "st,stm32mp25-dma3";
229 #dma-cells = <3>;
233 compatible = "st,stm32mp25-omm";
235 reg-names = "regs", "memory_map";
241 clock-names = "omm", "ospi1", "ospi2";
245 reset-names = "omm", "ospi1", "ospi2";
246 access-controllers = <&rifsc 111>;
247 power-domains = <&CLUSTER_PD>;
248 #address-cells = <2>;
249 #size-cells = <1>;
250 st,syscfg-amcr = <&syscfg 0x2c00 0x7>;
254 compatible = "st,stm32mp25-ospi";
259 dma-names = "tx", "rx";
263 access-controllers = <&rifsc 74>;
264 power-domains = <&CLUSTER_PD>;
265 st,syscfg-dlyb = <&syscfg 0x1000>;
270 compatible = "st,stm32mp25-ospi";
275 dma-names = "tx", "rx";
279 access-controllers = <&rifsc 75>;
280 power-domains = <&CLUSTER_PD>;
281 st,syscfg-dlyb = <&syscfg 0x1400>;
287 compatible = "st,stm32mp25-rifsc", "simple-bus";
289 #address-cells = <1>;
290 #size-cells = <1>;
291 #access-controller-cells = <1>;
295 compatible = "st,stm32mp25-timers";
298 interrupt-names = "global";
300 clock-names = "int";
301 #address-cells = <1>;
302 #size-cells = <0>;
303 access-controllers = <&rifsc 1>;
304 power-domains = <&CLUSTER_PD>;
308 compatible = "st,stm32mp25-timer-counter";
313 compatible = "st,stm32mp25-pwm";
314 #pwm-cells = <3>;
319 compatible = "st,stm32mp25-timer-trigger";
326 compatible = "st,stm32mp25-timers";
329 interrupt-names = "global";
331 clock-names = "int";
332 #address-cells = <1>;
333 #size-cells = <0>;
334 access-controllers = <&rifsc 2>;
335 power-domains = <&CLUSTER_PD>;
339 compatible = "st,stm32mp25-timer-counter";
344 compatible = "st,stm32mp25-pwm";
345 #pwm-cells = <3>;
350 compatible = "st,stm32mp25-timer-trigger";
357 compatible = "st,stm32mp25-timers";
360 interrupt-names = "global";
362 clock-names = "int";
363 #address-cells = <1>;
364 #size-cells = <0>;
365 access-controllers = <&rifsc 3>;
366 power-domains = <&CLUSTER_PD>;
370 compatible = "st,stm32mp25-timer-counter";
375 compatible = "st,stm32mp25-pwm";
376 #pwm-cells = <3>;
381 compatible = "st,stm32mp25-timer-trigger";
388 compatible = "st,stm32mp25-timers";
391 interrupt-names = "global";
393 clock-names = "int";
394 #address-cells = <1>;
395 #size-cells = <0>;
396 access-controllers = <&rifsc 4>;
397 power-domains = <&CLUSTER_PD>;
401 compatible = "st,stm32mp25-timer-counter";
406 compatible = "st,stm32mp25-pwm";
407 #pwm-cells = <3>;
412 compatible = "st,stm32mp25-timer-trigger";
419 compatible = "st,stm32mp25-timers";
422 interrupt-names = "global";
424 clock-names = "int";
425 #address-cells = <1>;
426 #size-cells = <0>;
427 access-controllers = <&rifsc 5>;
428 power-domains = <&CLUSTER_PD>;
432 compatible = "st,stm32mp25-timer-counter";
437 compatible = "st,stm32mp25-timer-trigger";
444 compatible = "st,stm32mp25-timers";
447 interrupt-names = "global";
449 clock-names = "int";
450 #address-cells = <1>;
451 #size-cells = <0>;
452 access-controllers = <&rifsc 6>;
453 power-domains = <&CLUSTER_PD>;
457 compatible = "st,stm32mp25-timer-counter";
462 compatible = "st,stm32mp25-timer-trigger";
469 compatible = "st,stm32mp25-timers";
472 interrupt-names = "global";
474 clock-names = "int";
475 #address-cells = <1>;
476 #size-cells = <0>;
477 access-controllers = <&rifsc 10>;
478 power-domains = <&CLUSTER_PD>;
482 compatible = "st,stm32mp25-timer-counter";
487 compatible = "st,stm32mp25-pwm";
488 #pwm-cells = <3>;
493 compatible = "st,stm32mp25-timer-trigger";
500 compatible = "st,stm32mp25-timers";
503 interrupt-names = "global";
505 clock-names = "int";
506 #address-cells = <1>;
507 #size-cells = <0>;
508 access-controllers = <&rifsc 11>;
509 power-domains = <&CLUSTER_PD>;
513 compatible = "st,stm32mp25-timer-counter";
518 compatible = "st,stm32mp25-pwm";
519 #pwm-cells = <3>;
524 compatible = "st,stm32mp25-timer-trigger";
531 compatible = "st,stm32mp25-timers";
534 interrupt-names = "global";
536 clock-names = "int";
537 #address-cells = <1>;
538 #size-cells = <0>;
539 access-controllers = <&rifsc 12>;
540 power-domains = <&CLUSTER_PD>;
544 compatible = "st,stm32mp25-timer-counter";
549 compatible = "st,stm32mp25-pwm";
550 #pwm-cells = <3>;
555 compatible = "st,stm32mp25-timer-trigger";
562 compatible = "st,stm32mp25-lptimer", "st,stm32-lptimer";
564 interrupts-extended = <&exti1 47 IRQ_TYPE_LEVEL_HIGH>;
566 clock-names = "mux";
567 #address-cells = <1>;
568 #size-cells = <0>;
569 access-controllers = <&rifsc 17>;
570 power-domains = <&RET_PD>;
571 wakeup-source;
575 compatible = "st,stm32mp25-lptimer-counter", "st,stm32-lptimer-counter";
580 compatible = "st,stm32mp25-pwm-lp", "st,stm32-pwm-lp";
581 #pwm-cells = <3>;
586 compatible = "st,stm32mp25-lptimer-timer", "st,stm32-lptimer-timer";
591 compatible = "st,stm32mp25-lptimer-trigger", "st,stm32-lptimer-trigger";
598 compatible = "st,stm32mp25-lptimer", "st,stm32-lptimer";
600 interrupts-extended = <&exti1 48 IRQ_TYPE_LEVEL_HIGH>;
602 clock-names = "mux";
603 #address-cells = <1>;
604 #size-cells = <0>;
605 access-controllers = <&rifsc 18>;
606 power-domains = <&RET_PD>;
607 wakeup-source;
611 compatible = "st,stm32mp25-lptimer-counter", "st,stm32-lptimer-counter";
616 compatible = "st,stm32mp25-pwm-lp", "st,stm32-pwm-lp";
617 #pwm-cells = <3>;
622 compatible = "st,stm32mp25-lptimer-timer", "st,stm32-lptimer-timer";
627 compatible = "st,stm32mp25-lptimer-trigger", "st,stm32-lptimer-trigger";
633 i2s2: audio-controller@400b0000 {
634 compatible = "st,stm32mp25-i2s";
636 #sound-dai-cells = <0>;
639 clock-names = "pclk", "i2sclk";
643 dma-names = "rx", "tx";
644 access-controllers = <&rifsc 23>;
649 #address-cells = <1>;
650 #size-cells = <0>;
651 compatible = "st,stm32mp25-spi";
658 dma-names = "rx", "tx";
659 access-controllers = <&rifsc 23>;
663 i2s3: audio-controller@400c0000 {
664 compatible = "st,stm32mp25-i2s";
666 #sound-dai-cells = <0>;
669 clock-names = "pclk", "i2sclk";
673 dma-names = "rx", "tx";
674 access-controllers = <&rifsc 24>;
679 #address-cells = <1>;
680 #size-cells = <0>;
681 compatible = "st,stm32mp25-spi";
688 dma-names = "rx", "tx";
689 access-controllers = <&rifsc 24>;
693 spdifrx: audio-controller@400d0000 {
694 compatible = "st,stm32h7-spdifrx";
695 #sound-dai-cells = <0>;
698 clock-names = "kclk";
702 dma-names = "rx", "rx-ctrl";
703 access-controllers = <&rifsc 30>;
708 compatible = "st,stm32h7-uart";
714 dma-names = "rx", "tx";
715 access-controllers = <&rifsc 32>;
720 compatible = "st,stm32h7-uart";
726 dma-names = "rx", "tx";
727 access-controllers = <&rifsc 33>;
732 compatible = "st,stm32h7-uart";
738 dma-names = "rx", "tx";
739 access-controllers = <&rifsc 34>;
744 compatible = "st,stm32h7-uart";
750 dma-names = "rx", "tx";
751 access-controllers = <&rifsc 35>;
756 compatible = "st,stm32mp25-i2c";
758 interrupt-names = "event";
762 #address-cells = <1>;
763 #size-cells = <0>;
766 dma-names = "rx", "tx";
767 access-controllers = <&rifsc 41>;
772 compatible = "st,stm32mp25-i2c";
774 interrupt-names = "event";
778 #address-cells = <1>;
779 #size-cells = <0>;
782 dma-names = "rx", "tx";
783 access-controllers = <&rifsc 42>;
788 compatible = "st,stm32mp25-i2c";
790 interrupt-names = "event";
794 #address-cells = <1>;
795 #size-cells = <0>;
798 dma-names = "rx", "tx";
799 access-controllers = <&rifsc 43>;
804 compatible = "st,stm32mp25-i2c";
806 interrupt-names = "event";
810 #address-cells = <1>;
811 #size-cells = <0>;
814 dma-names = "rx", "tx";
815 access-controllers = <&rifsc 44>;
820 compatible = "st,stm32mp25-i2c";
822 interrupt-names = "event";
826 #address-cells = <1>;
827 #size-cells = <0>;
830 dma-names = "rx", "tx";
831 access-controllers = <&rifsc 45>;
836 compatible = "st,stm32mp25-i2c";
838 interrupt-names = "event";
842 #address-cells = <1>;
843 #size-cells = <0>;
846 dma-names = "rx", "tx";
847 access-controllers = <&rifsc 46>;
852 compatible = "st,stm32mp25-i2c";
854 interrupt-names = "event";
858 #address-cells = <1>;
859 #size-cells = <0>;
862 dma-names = "rx", "tx";
863 access-controllers = <&rifsc 47>;
868 compatible = "st,stm32mp25-timers";
871 interrupt-names = "global";
873 clock-names = "int";
874 #address-cells = <1>;
875 #size-cells = <0>;
876 access-controllers = <&rifsc 8>;
877 power-domains = <&CLUSTER_PD>;
881 compatible = "st,stm32mp25-timer-counter";
886 compatible = "st,stm32mp25-pwm";
887 #pwm-cells = <3>;
892 compatible = "st,stm32mp25-timer-trigger";
899 compatible = "st,stm32mp25-timers";
902 interrupt-names = "global";
904 clock-names = "int";
905 #address-cells = <1>;
906 #size-cells = <0>;
907 access-controllers = <&rifsc 9>;
908 power-domains = <&CLUSTER_PD>;
912 compatible = "st,stm32mp25-timer-counter";
917 compatible = "st,stm32mp25-pwm";
918 #pwm-cells = <3>;
923 compatible = "st,stm32mp25-timer-trigger";
930 compatible = "st,stm32mp25-timers";
936 interrupt-names = "brk", "up", "trg-com", "cc";
938 clock-names = "int";
939 #address-cells = <1>;
940 #size-cells = <0>;
941 access-controllers = <&rifsc 0>;
942 power-domains = <&CLUSTER_PD>;
946 compatible = "st,stm32mp25-timer-counter";
951 compatible = "st,stm32mp25-pwm";
952 #pwm-cells = <3>;
957 compatible = "st,stm32mp25-timer-trigger";
964 compatible = "st,stm32mp25-timers";
970 interrupt-names = "brk", "up", "trg-com", "cc";
972 clock-names = "int";
973 #address-cells = <1>;
974 #size-cells = <0>;
975 access-controllers = <&rifsc 7>;
976 power-domains = <&CLUSTER_PD>;
980 compatible = "st,stm32mp25-timer-counter";
985 compatible = "st,stm32mp25-pwm";
986 #pwm-cells = <3>;
991 compatible = "st,stm32mp25-timer-trigger";
998 compatible = "st,stm32h7-uart";
1004 dma-names = "rx", "tx";
1005 access-controllers = <&rifsc 36>;
1009 i2s1: audio-controller@40230000 {
1010 compatible = "st,stm32mp25-i2s";
1012 #sound-dai-cells = <0>;
1015 clock-names = "pclk", "i2sclk";
1019 dma-names = "rx", "tx";
1020 access-controllers = <&rifsc 22>;
1025 #address-cells = <1>;
1026 #size-cells = <0>;
1027 compatible = "st,stm32mp25-spi";
1034 dma-names = "rx", "tx";
1035 access-controllers = <&rifsc 22>;
1040 #address-cells = <1>;
1041 #size-cells = <0>;
1042 compatible = "st,stm32mp25-spi";
1049 dma-names = "rx", "tx";
1050 access-controllers = <&rifsc 25>;
1055 compatible = "st,stm32mp25-timers";
1058 interrupt-names = "global";
1060 clock-names = "int";
1061 #address-cells = <1>;
1062 #size-cells = <0>;
1063 access-controllers = <&rifsc 13>;
1064 power-domains = <&CLUSTER_PD>;
1068 compatible = "st,stm32mp25-timer-counter";
1073 compatible = "st,stm32mp25-pwm";
1074 #pwm-cells = <3>;
1079 compatible = "st,stm32mp25-timer-trigger";
1086 compatible = "st,stm32mp25-timers";
1089 interrupt-names = "global";
1091 clock-names = "int";
1092 #address-cells = <1>;
1093 #size-cells = <0>;
1094 access-controllers = <&rifsc 14>;
1095 power-domains = <&CLUSTER_PD>;
1099 compatible = "st,stm32mp25-timer-counter";
1104 compatible = "st,stm32mp25-pwm";
1105 #pwm-cells = <3>;
1110 compatible = "st,stm32mp25-timer-trigger";
1117 compatible = "st,stm32mp25-timers";
1120 interrupt-names = "global";
1122 clock-names = "int";
1123 #address-cells = <1>;
1124 #size-cells = <0>;
1125 access-controllers = <&rifsc 15>;
1126 power-domains = <&CLUSTER_PD>;
1130 compatible = "st,stm32mp25-timer-counter";
1135 compatible = "st,stm32mp25-pwm";
1136 #pwm-cells = <3>;
1141 compatible = "st,stm32mp25-timer-trigger";
1148 #address-cells = <1>;
1149 #size-cells = <0>;
1150 compatible = "st,stm32mp25-spi";
1157 dma-names = "rx", "tx";
1158 access-controllers = <&rifsc 26>;
1163 compatible = "st,stm32mp25-sai";
1166 #address-cells = <1>;
1167 #size-cells = <1>;
1169 clock-names = "pclk";
1172 access-controllers = <&rifsc 49>;
1175 sai1a: audio-controller@40290004 {
1176 compatible = "st,stm32-sai-sub-a";
1178 #sound-dai-cells = <0>;
1180 clock-names = "sai_ck";
1185 sai1b: audio-controller@40290024 {
1186 compatible = "st,stm32-sai-sub-b";
1188 #sound-dai-cells = <0>;
1190 clock-names = "sai_ck";
1197 compatible = "st,stm32mp25-sai";
1200 #address-cells = <1>;
1201 #size-cells = <1>;
1203 clock-names = "pclk";
1206 access-controllers = <&rifsc 50>;
1209 sai2a: audio-controller@402a0004 {
1210 compatible = "st,stm32-sai-sub-a";
1212 #sound-dai-cells = <0>;
1214 clock-names = "sai_ck";
1219 sai2b: audio-controller@402a0024 {
1220 compatible = "st,stm32-sai-sub-b";
1222 #sound-dai-cells = <0>;
1224 clock-names = "sai_ck";
1231 compatible = "st,stm32mp25-sai";
1234 #address-cells = <1>;
1235 #size-cells = <1>;
1237 clock-names = "pclk";
1240 access-controllers = <&rifsc 51>;
1243 sai3a: audio-controller@402b0004 {
1244 compatible = "st,stm32-sai-sub-a";
1246 #sound-dai-cells = <0>;
1248 clock-names = "sai_ck";
1253 sai3b: audio-controller@502b0024 {
1254 compatible = "st,stm32-sai-sub-b";
1256 #sound-dai-cells = <0>;
1258 clock-names = "sai_ck";
1265 compatible = "st,stm32h7-uart";
1271 dma-names = "rx", "tx";
1272 access-controllers = <&rifsc 39>;
1277 compatible = "st,stm32mp25-timers";
1283 interrupt-names = "brk", "up", "trg-com", "cc";
1285 clock-names = "int";
1286 #address-cells = <1>;
1287 #size-cells = <0>;
1288 access-controllers = <&rifsc 16>;
1289 power-domains = <&CLUSTER_PD>;
1293 compatible = "st,stm32mp25-timer-counter";
1298 compatible = "st,stm32mp25-pwm";
1299 #pwm-cells = <3>;
1304 compatible = "st,stm32mp25-timer-trigger";
1311 compatible = "st,stm32h7-uart";
1317 dma-names = "rx", "tx";
1318 access-controllers = <&rifsc 31>;
1323 compatible = "st,stm32mp25-sai";
1326 #address-cells = <1>;
1327 #size-cells = <1>;
1329 clock-names = "pclk";
1332 access-controllers = <&rifsc 52>;
1335 sai4a: audio-controller@40340004 {
1336 compatible = "st,stm32-sai-sub-a";
1338 #sound-dai-cells = <0>;
1340 clock-names = "sai_ck";
1345 sai4b: audio-controller@40340024 {
1346 compatible = "st,stm32-sai-sub-b";
1348 #sound-dai-cells = <0>;
1350 clock-names = "sai_ck";
1357 #address-cells = <1>;
1358 #size-cells = <0>;
1359 compatible = "st,stm32mp25-spi";
1366 dma-names = "rx", "tx";
1367 access-controllers = <&rifsc 27>;
1372 #address-cells = <1>;
1373 #size-cells = <0>;
1374 compatible = "st,stm32mp25-spi";
1381 dma-names = "rx", "tx";
1382 access-controllers = <&rifsc 28>;
1387 compatible = "st,stm32h7-uart";
1393 dma-names = "rx", "tx";
1394 access-controllers = <&rifsc 37>;
1399 compatible = "st,stm32h7-uart";
1405 dma-names = "rx", "tx";
1406 access-controllers = <&rifsc 38>;
1411 compatible = "st,stm32mp25-rng";
1414 clock-names = "core", "bus";
1416 access-controllers = <&rifsc 92>;
1421 #address-cells = <1>;
1422 #size-cells = <0>;
1423 compatible = "st,stm32mp25-spi";
1430 dma-names = "rx", "tx";
1431 access-controllers = <&rifsc 29>;
1436 compatible = "st,stm32mp25-i2c";
1438 interrupt-names = "event";
1442 #address-cells = <1>;
1443 #size-cells = <0>;
1446 dma-names = "rx", "tx";
1447 access-controllers = <&rifsc 48>;
1452 compatible = "st,stm32mp25-lptimer", "st,stm32-lptimer";
1454 interrupts-extended = <&exti2 29 IRQ_TYPE_LEVEL_HIGH>;
1456 clock-names = "mux";
1457 #address-cells = <1>;
1458 #size-cells = <0>;
1459 access-controllers = <&rifsc 19>;
1460 wakeup-source;
1464 compatible = "st,stm32mp25-lptimer-counter", "st,stm32-lptimer-counter";
1469 compatible = "st,stm32mp25-pwm-lp", "st,stm32-pwm-lp";
1470 #pwm-cells = <3>;
1475 compatible = "st,stm32mp25-lptimer-timer", "st,stm32-lptimer-timer";
1480 compatible = "st,stm32mp25-lptimer-trigger", "st,stm32-lptimer-trigger";
1487 compatible = "st,stm32mp25-lptimer", "st,stm32-lptimer";
1489 interrupts-extended = <&exti2 30 IRQ_TYPE_LEVEL_HIGH>;
1491 clock-names = "mux";
1492 #address-cells = <1>;
1493 #size-cells = <0>;
1494 access-controllers = <&rifsc 20>;
1495 wakeup-source;
1499 compatible = "st,stm32mp25-lptimer-counter", "st,stm32-lptimer-counter";
1504 compatible = "st,stm32mp25-pwm-lp", "st,stm32-pwm-lp";
1505 #pwm-cells = <3>;
1510 compatible = "st,stm32mp25-lptimer-timer", "st,stm32-lptimer-timer";
1515 compatible = "st,stm32mp25-lptimer-trigger", "st,stm32-lptimer-trigger";
1522 compatible = "st,stm32mp25-lptimer", "st,stm32-lptimer";
1524 interrupts-extended = <&exti2 31 IRQ_TYPE_LEVEL_HIGH>;
1526 clock-names = "mux";
1527 #address-cells = <1>;
1528 #size-cells = <0>;
1529 access-controllers = <&rifsc 21>;
1530 wakeup-source;
1534 compatible = "st,stm32mp25-lptimer-counter", "st,stm32-lptimer-counter";
1539 compatible = "st,stm32mp25-pwm-lp", "st,stm32-pwm-lp";
1540 #pwm-cells = <3>;
1545 compatible = "st,stm32mp25-lptimer-timer", "st,stm32-lptimer-timer";
1550 compatible = "st,stm32mp25-lptimer-trigger", "st,stm32-lptimer-trigger";
1557 compatible = "st,stm32mp25-csi";
1563 clock-names = "pclk", "txesc", "csi2phy";
1564 access-controllers = <&rifsc 86>;
1569 compatible = "st,stm32mp25-dcmipp";
1574 clock-names = "kclk", "mclk";
1575 access-controllers = <&rifsc 87>;
1580 compatible = "st,stm32mp25-combophy";
1582 #phy-cells = <1>;
1584 clock-names = "apb", "ker";
1586 reset-names = "phy";
1587 access-controllers = <&rifsc 67>;
1588 power-domains = <&CLUSTER_PD>;
1589 wakeup-source;
1590 interrupts-extended = <&exti1 45 IRQ_TYPE_EDGE_FALLING>;
1595 compatible = "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell";
1596 arm,primecell-periphid = <0x00353180>;
1600 clock-names = "apb_pclk";
1602 cap-sd-highspeed;
1603 cap-mmc-highspeed;
1604 max-frequency = <120000000>;
1605 access-controllers = <&rifsc 76>;
1610 compatible = "st,stm32mp25-dwmac", "snps,dwmac-5.20";
1612 reg-names = "stmmaceth";
1613 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
1614 interrupt-names = "macirq";
1615 clock-names = "stmmaceth",
1616 "mac-clk-tx",
1617 "mac-clk-rx",
1620 "eth-ck";
1627 snps,axi-config = <&stmmac_axi_config_1>;
1628 snps,mixed-burst;
1629 snps,mtl-rx-config = <&mtl_rx_setup_1>;
1630 snps,mtl-tx-config = <&mtl_tx_setup_1>;
1633 st,syscon = <&syscfg 0x3000>;
1634 access-controllers = <&rifsc 60>;
1637 mtl_rx_setup_1: rx-queues-config {
1638 snps,rx-queues-to-use = <2>;
1643 mtl_tx_setup_1: tx-queues-config {
1644 snps,tx-queues-to-use = <4>;
1651 stmmac_axi_config_1: stmmac-axi-config {
1660 compatible = "st,stm32mp25-bsec";
1662 #address-cells = <1>;
1663 #size-cells = <1>;
1675 rcc: clock-controller@44200000 {
1676 compatible = "st,stm32mp25-rcc";
1678 #clock-cells = <1>;
1679 #reset-cells = <1>;
1760 access-controllers = <&rifsc 156>;
1763 exti1: interrupt-controller@44220000 {
1764 compatible = "st,stm32mp1-exti", "syscon";
1765 interrupt-controller;
1766 #interrupt-cells = <2>;
1768 interrupts-extended =
1856 syscfg: syscon@44230000 { label
1857 compatible = "st,stm32mp25-syscfg", "syscon";
1862 #address-cells = <1>;
1863 #size-cells = <1>;
1864 compatible = "st,stm32mp257-pinctrl";
1866 interrupt-parent = <&exti1>;
1867 st,syscfg = <&exti1 0x60 0xff>;
1868 pins-are-numbered;
1871 gpio-controller;
1872 #gpio-cells = <2>;
1873 interrupt-controller;
1874 #interrupt-cells = <2>;
1877 st,bank-name = "GPIOA";
1882 gpio-controller;
1883 #gpio-cells = <2>;
1884 interrupt-controller;
1885 #interrupt-cells = <2>;
1888 st,bank-name = "GPIOB";
1893 gpio-controller;
1894 #gpio-cells = <2>;
1895 interrupt-controller;
1896 #interrupt-cells = <2>;
1899 st,bank-name = "GPIOC";
1904 gpio-controller;
1905 #gpio-cells = <2>;
1906 interrupt-controller;
1907 #interrupt-cells = <2>;
1910 st,bank-name = "GPIOD";
1915 gpio-controller;
1916 #gpio-cells = <2>;
1917 interrupt-controller;
1918 #interrupt-cells = <2>;
1921 st,bank-name = "GPIOE";
1926 gpio-controller;
1927 #gpio-cells = <2>;
1928 interrupt-controller;
1929 #interrupt-cells = <2>;
1932 st,bank-name = "GPIOF";
1937 gpio-controller;
1938 #gpio-cells = <2>;
1939 interrupt-controller;
1940 #interrupt-cells = <2>;
1943 st,bank-name = "GPIOG";
1948 gpio-controller;
1949 #gpio-cells = <2>;
1950 interrupt-controller;
1951 #interrupt-cells = <2>;
1954 st,bank-name = "GPIOH";
1959 gpio-controller;
1960 #gpio-cells = <2>;
1961 interrupt-controller;
1962 #interrupt-cells = <2>;
1965 st,bank-name = "GPIOI";
1970 gpio-controller;
1971 #gpio-cells = <2>;
1972 interrupt-controller;
1973 #interrupt-cells = <2>;
1976 st,bank-name = "GPIOJ";
1981 gpio-controller;
1982 #gpio-cells = <2>;
1983 interrupt-controller;
1984 #interrupt-cells = <2>;
1987 st,bank-name = "GPIOK";
1993 compatible = "st,stm32mp25-rtc";
1997 clock-names = "pclk", "rtc_ck";
1998 interrupts-extended = <&exti2 17 IRQ_TYPE_LEVEL_HIGH>;
2003 #address-cells = <1>;
2004 #size-cells = <1>;
2005 compatible = "st,stm32mp257-z-pinctrl";
2007 interrupt-parent = <&exti1>;
2008 st,syscfg = <&exti1 0x60 0xff>;
2009 pins-are-numbered;
2012 gpio-controller;
2013 #gpio-cells = <2>;
2014 interrupt-controller;
2015 #interrupt-cells = <2>;
2018 st,bank-name = "GPIOZ";
2019 st,bank-ioport = <11>;
2024 exti2: interrupt-controller@46230000 {
2025 compatible = "st,stm32mp1-exti", "syscon";
2026 interrupt-controller;
2027 #interrupt-cells = <2>;
2029 interrupts-extended =