Lines Matching +full:cpu +full:- +full:syscon
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/sprd,ums512-clk.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 #address-cells = <2>;
18 #size-cells = <0>;
20 cpu-map {
23 cpu = <&CPU0>;
26 cpu = <&CPU1>;
29 cpu = <&CPU2>;
32 cpu = <&CPU3>;
35 cpu = <&CPU4>;
38 cpu = <&CPU5>;
41 cpu = <&CPU6>;
44 cpu = <&CPU7>;
49 CPU0: cpu@0 {
50 device_type = "cpu";
51 compatible = "arm,cortex-a55";
53 enable-method = "psci";
54 cpu-idle-states = <&CORE_PD>;
57 CPU1: cpu@100 {
58 device_type = "cpu";
59 compatible = "arm,cortex-a55";
61 enable-method = "psci";
62 cpu-idle-states = <&CORE_PD>;
65 CPU2: cpu@200 {
66 device_type = "cpu";
67 compatible = "arm,cortex-a55";
69 enable-method = "psci";
70 cpu-idle-states = <&CORE_PD>;
73 CPU3: cpu@300 {
74 device_type = "cpu";
75 compatible = "arm,cortex-a55";
77 enable-method = "psci";
78 cpu-idle-states = <&CORE_PD>;
81 CPU4: cpu@400 {
82 device_type = "cpu";
83 compatible = "arm,cortex-a55";
85 enable-method = "psci";
86 cpu-idle-states = <&CORE_PD>;
89 CPU5: cpu@500 {
90 device_type = "cpu";
91 compatible = "arm,cortex-a55";
93 enable-method = "psci";
94 cpu-idle-states = <&CORE_PD>;
97 CPU6: cpu@600 {
98 device_type = "cpu";
99 compatible = "arm,cortex-a75";
101 enable-method = "psci";
102 cpu-idle-states = <&CORE_PD>;
105 CPU7: cpu@700 {
106 device_type = "cpu";
107 compatible = "arm,cortex-a75";
109 enable-method = "psci";
110 cpu-idle-states = <&CORE_PD>;
114 idle-states {
115 entry-method = "psci";
116 CORE_PD: cpu-pd {
117 compatible = "arm,idle-state";
118 entry-latency-us = <4000>;
119 exit-latency-us = <4000>;
120 min-residency-us = <10000>;
121 local-timer-stop;
122 arm,psci-suspend-param = <0x00010000>;
127 compatible = "arm,psci-0.2";
132 compatible = "arm,armv8-timer";
134 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, /* Physical Non-Secure PPI */
140 compatible = "arm,armv8-pmuv3";
152 compatible = "simple-bus";
153 #address-cells = <2>;
154 #size-cells = <2>;
157 gic: interrupt-controller@12000000 {
158 compatible = "arm,gic-v3";
161 #interrupt-cells = <3>;
162 #address-cells = <2>;
163 #size-cells = <2>;
165 redistributor-stride = <0x0 0x20000>; /* 128KB stride */
166 #redistributor-regions = <1>;
167 interrupt-controller;
171 ap_ahb_regs: syscon@20100000 {
172 compatible = "sprd,ums512-glbregs", "syscon",
173 "simple-mfd";
175 #address-cells = <1>;
176 #size-cells = <1>;
179 apahb_gate: clock-controller@0 {
180 compatible = "sprd,ums512-apahb-gate";
183 clock-names = "ext-26m";
184 #clock-cells = <1>;
188 pub_apb_regs: syscon@31050000 {
189 compatible = "sprd,ums512-glbregs", "syscon",
190 "simple-mfd";
194 top_dvfs_apb_regs: syscon@322a0000 {
195 compatible = "sprd,ums512-glbregs", "syscon",
196 "simple-mfd";
200 ap_intc0_regs: syscon@32310000 {
201 compatible = "sprd,ums512-glbregs", "syscon",
202 "simple-mfd";
206 ap_intc1_regs: syscon@32320000 {
207 compatible = "sprd,ums512-glbregs", "syscon",
208 "simple-mfd";
212 ap_intc2_regs: syscon@32330000 {
213 compatible = "sprd,ums512-glbregs", "syscon",
214 "simple-mfd";
218 ap_intc3_regs: syscon@32340000 {
219 compatible = "sprd,ums512-glbregs", "syscon",
220 "simple-mfd";
224 ap_intc4_regs: syscon@32350000 {
225 compatible = "sprd,ums512-glbregs", "syscon",
226 "simple-mfd";
230 ap_intc5_regs: syscon@32360000 {
231 compatible = "sprd,ums512-glbregs", "syscon",
232 "simple-mfd";
236 anlg_phy_g0_regs: syscon@32390000 {
237 compatible = "sprd,ums512-glbregs", "syscon",
238 "simple-mfd";
240 #address-cells = <1>;
241 #size-cells = <1>;
244 dpll0: clock-controller@0 {
245 compatible = "sprd,ums512-g0-pll";
247 #clock-cells = <1>;
251 anlg_phy_g2_regs: syscon@323b0000 {
252 compatible = "sprd,ums512-glbregs", "syscon",
253 "simple-mfd";
255 #address-cells = <1>;
256 #size-cells = <1>;
259 mpll1: clock-controller@0 {
260 compatible = "sprd,ums512-g2-pll";
262 #clock-cells = <1>;
266 anlg_phy_g3_regs: syscon@323c0000 {
267 compatible = "sprd,ums512-glbregs", "syscon",
268 "simple-mfd";
270 #address-cells = <1>;
271 #size-cells = <1>;
274 pll1: clock-controller@0 {
275 compatible = "sprd,ums512-g3-pll";
278 clock-names = "ext-26m";
279 #clock-cells = <1>;
283 anlg_phy_gc_regs: syscon@323e0000 {
284 compatible = "sprd,ums512-glbregs", "syscon",
285 "simple-mfd";
287 #address-cells = <1>;
288 #size-cells = <1>;
291 pll2: clock-controller@0 {
292 compatible = "sprd,ums512-gc-pll";
295 clock-names = "ext-26m";
296 #clock-cells = <1>;
300 anlg_phy_g10_regs: syscon@323f0000 {
301 compatible = "sprd,ums512-glbregs", "syscon",
302 "simple-mfd";
306 aon_apb_regs: syscon@327d0000 {
307 compatible = "sprd,ums512-glbregs", "syscon",
308 "simple-mfd";
310 #address-cells = <1>;
311 #size-cells = <1>;
314 aonapb_gate: clock-controller@0 {
315 compatible = "sprd,ums512-aon-gate";
318 clock-names = "ext-26m";
319 #clock-cells = <1>;
323 pmu_apb_regs: syscon@327e0000 {
324 compatible = "sprd,ums512-glbregs", "syscon",
325 "simple-mfd";
327 #address-cells = <1>;
328 #size-cells = <1>;
331 pmu_gate: clock-controller@0 {
332 compatible = "sprd,ums512-pmu-gate";
335 clock-names = "ext-26m";
336 #clock-cells = <1>;
340 audcp_apb_regs: syscon@3350d000 {
341 compatible = "sprd,ums512-glbregs", "syscon",
342 "simple-mfd";
344 #address-cells = <1>;
345 #size-cells = <1>;
348 audcpapb_gate: clock-controller@0 {
349 compatible = "sprd,ums512-audcpapb-gate";
351 #clock-cells = <1>;
355 audcp_ahb_regs: syscon@335e0000 {
356 compatible = "sprd,ums512-glbregs", "syscon",
357 "simple-mfd";
359 #address-cells = <1>;
360 #size-cells = <1>;
363 audcpahb_gate: clock-controller@0 {
364 compatible = "sprd,ums512-audcpahb-gate";
366 #clock-cells = <1>;
370 gpu_apb_regs: syscon@60100000 {
371 compatible = "sprd,ums512-glbregs", "syscon",
372 "simple-mfd";
374 #address-cells = <1>;
375 #size-cells = <1>;
378 gpu_clk: clock-controller@0 {
379 compatible = "sprd,ums512-gpu-clk";
381 clock-names = "ext-26m";
383 #clock-cells = <1>;
387 gpu_dvfs_apb_regs: syscon@60110000 {
388 compatible = "sprd,ums512-glbregs", "syscon",
389 "simple-mfd";
393 mm_ahb_regs: syscon@62200000 {
394 compatible = "sprd,ums512-glbregs", "syscon",
395 "simple-mfd";
397 #address-cells = <1>;
398 #size-cells = <1>;
401 mm_gate: clock-controller@0 {
402 compatible = "sprd,ums512-mm-gate-clk";
404 #clock-cells = <1>;
408 ap_apb_regs: syscon@71000000 {
409 compatible = "sprd,ums512-glbregs", "syscon",
410 "simple-mfd";
412 #address-cells = <1>;
413 #size-cells = <1>;
416 apapb_gate: clock-controller@0 {
417 compatible = "sprd,ums512-apapb-gate";
419 #clock-cells = <1>;
423 ap_clk: clock-controller@20200000 {
424 compatible = "sprd,ums512-ap-clk";
427 clock-names = "ext-26m";
428 #clock-cells = <1>;
431 aon_clk: clock-controller@32080000 {
432 compatible = "sprd,ums512-aonapb-clk";
436 clock-names = "ext-26m", "ext-32k",
437 "ext-4m", "rco-100m";
438 #clock-cells = <1>;
441 mm_clk: clock-controller@62100000 {
442 compatible = "sprd,ums512-mm-clk";
445 clock-names = "ext-26m";
446 #clock-cells = <1>;
451 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
454 clock-names = "apb_pclk";
456 out-ports {
459 remote-endpoint = <&etb_in>;
464 in-ports {
465 #address-cells = <1>;
466 #size-cells = <0>;
471 remote-endpoint =
480 compatible = "arm,coresight-tmc", "arm,primecell";
483 clock-names = "apb_pclk";
485 in-ports {
488 remote-endpoint =
495 /* AP-CPU Funnel for core3/4/5/7 */
497 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
500 clock-names = "apb_pclk";
502 out-ports {
505 remote-endpoint =
511 in-ports {
512 #address-cells = <1>;
513 #size-cells = <0>;
518 remote-endpoint = <&etm3_out>;
525 remote-endpoint = <&etm4_out>;
532 remote-endpoint = <&etm5_out>;
539 remote-endpoint = <&etm7_out>;
545 /* AP-CPU ETF for little cores */
547 compatible = "arm,coresight-tmc", "arm,primecell";
550 clock-names = "apb_pclk";
552 out-ports {
555 remote-endpoint =
561 in-ports {
564 remote-endpoint =
571 /* AP-CPU ETF for big cores */
573 compatible = "arm,coresight-tmc", "arm,primecell";
576 clock-names = "apb_pclk";
578 out-ports {
581 remote-endpoint =
587 in-ports {
590 remote-endpoint =
599 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
602 clock-names = "apb_pclk";
604 out-ports {
607 remote-endpoint =
613 in-ports {
614 #address-cells = <1>;
615 #size-cells = <0>;
620 remote-endpoint = <&corinth_etf_lit_out>;
627 remote-endpoint = <&corinth_etf_big_out>;
633 /* AP-CPU Funnel for core0/1/2/6 */
635 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
638 clock-names = "apb_pclk";
640 out-ports {
643 remote-endpoint = <&corinth_etf_big_in>;
648 in-ports {
649 #address-cells = <1>;
650 #size-cells = <0>;
655 remote-endpoint = <&etm0_out>;
662 remote-endpoint = <&etm1_out>;
669 remote-endpoint = <&etm2_out>;
676 remote-endpoint = <&etm6_out>;
683 compatible = "arm,coresight-etm4x", "arm,primecell";
685 cpu = <&CPU0>;
687 clock-names = "apb_pclk";
689 out-ports {
692 remote-endpoint =
700 compatible = "arm,coresight-etm4x", "arm,primecell";
702 cpu = <&CPU1>;
704 clock-names = "apb_pclk";
706 out-ports {
709 remote-endpoint =
717 compatible = "arm,coresight-etm4x", "arm,primecell";
719 cpu = <&CPU2>;
721 clock-names = "apb_pclk";
723 out-ports {
726 remote-endpoint =
734 compatible = "arm,coresight-etm4x", "arm,primecell";
736 cpu = <&CPU3>;
738 clock-names = "apb_pclk";
740 out-ports {
743 remote-endpoint =
751 compatible = "arm,coresight-etm4x", "arm,primecell";
753 cpu = <&CPU4>;
755 clock-names = "apb_pclk";
757 out-ports {
760 remote-endpoint =
768 compatible = "arm,coresight-etm4x", "arm,primecell";
770 cpu = <&CPU5>;
772 clock-names = "apb_pclk";
774 out-ports {
777 remote-endpoint =
785 compatible = "arm,coresight-etm4x", "arm,primecell";
787 cpu = <&CPU6>;
789 clock-names = "apb_pclk";
791 out-ports {
794 remote-endpoint =
802 compatible = "arm,coresight-etm4x", "arm,primecell";
804 cpu = <&CPU7>;
806 clock-names = "apb_pclk";
808 out-ports {
811 remote-endpoint =
819 compatible = "simple-bus";
820 #address-cells = <1>;
821 #size-cells = <1>;
825 compatible = "sprd,ums512-uart",
826 "sprd,sc9836-uart";
834 compatible = "sprd,ums512-uart",
835 "sprd,sc9836-uart";
843 compatible = "sprd,sdhci-r11";
846 clock-names = "sdio", "enable";
849 assigned-clocks = <&ap_clk CLK_SDIO0_2X>;
850 assigned-clock-parents = <&pll1 CLK_RPLL>;
855 compatible = "sprd,sdhci-r11";
858 clock-names = "sdio", "enable";
861 assigned-clocks = <&ap_clk CLK_EMMC_2X>;
862 assigned-clock-parents = <&pll1 CLK_RPLL>;
868 compatible = "simple-bus";
869 #address-cells = <1>;
870 #size-cells = <1>;
874 compatible = "sprd,ums512-adi";
876 #address-cells = <1>;
877 #size-cells = <0>;
878 sprd,hw-channels = <2 0x18cc>, <3 0x18cc>, <13 0x1854>, <15 0x1874>,
885 ext_26m: clk-26m {
886 compatible = "fixed-clock";
887 #clock-cells = <0>;
888 clock-frequency = <26000000>;
889 clock-output-names = "ext-26m";
892 ext_32k: clk-32k {
893 compatible = "fixed-clock";
894 #clock-cells = <0>;
895 clock-frequency = <32768>;
896 clock-output-names = "ext-32k";
899 ext_4m: clk-4m {
900 compatible = "fixed-clock";
901 #clock-cells = <0>;
902 clock-frequency = <4000000>;
903 clock-output-names = "ext-4m";
906 rco_100m: clk-100m {
907 compatible = "fixed-clock";
908 #clock-cells = <0>;
909 clock-frequency = <100000000>;
910 clock-output-names = "rco-100m";