Lines Matching +full:0 +full:x20200000
18 #size-cells = <0>;
49 CPU0: cpu@0 {
52 reg = <0x0 0x0>;
60 reg = <0x0 0x100>;
68 reg = <0x0 0x200>;
76 reg = <0x0 0x300>;
84 reg = <0x0 0x400>;
92 reg = <0x0 0x500>;
100 reg = <0x0 0x600>;
108 reg = <0x0 0x700>;
122 arm,psci-suspend-param = <0x00010000>;
159 reg = <0x0 0x12000000 0 0x20000>, /* GICD */
160 <0x0 0x12040000 0 0x100000>; /* GICR */
165 redistributor-stride = <0x0 0x20000>; /* 128KB stride */
174 reg = <0 0x20100000 0 0x4000>;
177 ranges = <0 0 0x20100000 0x4000>;
179 apahb_gate: clock-controller@0 {
181 reg = <0x0 0x3000>;
191 reg = <0 0x31050000 0 0x9000>;
197 reg = <0 0x322a0000 0 0x8000>;
203 reg = <0 0x32310000 0 0x1000>;
209 reg = <0 0x32320000 0 0x1000>;
215 reg = <0 0x32330000 0 0x1000>;
221 reg = <0 0x32340000 0 0x1000>;
227 reg = <0 0x32350000 0 0x1000>;
233 reg = <0 0x32360000 0 0x1000>;
239 reg = <0 0x32390000 0 0x3000>;
242 ranges = <0 0 0x32390000 0x3000>;
244 dpll0: clock-controller@0 {
246 reg = <0x0 0x100>;
254 reg = <0 0x323b0000 0 0x3000>;
257 ranges = <0 0 0x323b0000 0x3000>;
259 mpll1: clock-controller@0 {
261 reg = <0x0 0x100>;
269 reg = <0 0x323c0000 0 0x3000>;
272 ranges = <0 0 0x323c0000 0x3000>;
274 pll1: clock-controller@0 {
276 reg = <0x0 0x3000>;
286 reg = <0 0x323e0000 0 0x3000>;
289 ranges = <0 0 0x323e0000 0x3000>;
291 pll2: clock-controller@0 {
293 reg = <0x0 0x100>;
303 reg = <0 0x323f0000 0 0x3000>;
309 reg = <0 0x327d0000 0 0x3000>;
312 ranges = <0 0 0x327d0000 0x3000>;
314 aonapb_gate: clock-controller@0 {
316 reg = <0x0 0x3000>;
326 reg = <0 0x327e0000 0 0x3000>;
329 ranges = <0 0 0x327e0000 0x3000>;
331 pmu_gate: clock-controller@0 {
333 reg = <0x0 0x3000>;
343 reg = <0 0x3350d000 0 0x1000>;
346 ranges = <0 0 0x3350d000 0x1000>;
348 audcpapb_gate: clock-controller@0 {
350 reg = <0x0 0x300>;
358 reg = <0 0x335e0000 0 0x1000>;
361 ranges = <0 0 0x335e0000 0x1000>;
363 audcpahb_gate: clock-controller@0 {
365 reg = <0x0 0x300>;
373 reg = <0 0x60100000 0 0x3000>;
376 ranges = <0 0 0x60100000 0x3000>;
378 gpu_clk: clock-controller@0 {
382 reg = <0x0 0x100>;
390 reg = <0 0x60110000 0 0x3000>;
396 reg = <0 0x62200000 0 0x3000>;
399 ranges = <0 0 0x62200000 0x3000>;
401 mm_gate: clock-controller@0 {
403 reg = <0x0 0x3000>;
411 reg = <0 0x71000000 0 0x3000>;
414 ranges = <0 0 0x71000000 0x3000>;
416 apapb_gate: clock-controller@0 {
418 reg = <0x0 0x3000>;
425 reg = <0 0x20200000 0 0x1000>;
433 reg = <0 0x32080000 0 0x1000>;
443 reg = <0 0x62100000 0 0x1000>;
452 reg = <0 0x3c002000 0 0x1000>;
466 #size-cells = <0>;
481 reg = <0 0x3c003000 0 0x1000>;
498 reg = <0 0x3e001000 0 0x1000>;
513 #size-cells = <0>;
515 port@0 {
516 reg = <0>;
548 reg = <0 0x3e002000 0 0x1000>;
574 reg = <0 0x3e003000 0 0x1000>;
600 reg = <0 0x3e004000 0 0x1000>;
615 #size-cells = <0>;
617 port@0 {
618 reg = <0>;
636 reg = <0 0x3e005000 0 0x1000>;
650 #size-cells = <0>;
652 port@0 {
653 reg = <0>;
684 reg = <0 0x3f040000 0 0x1000>;
701 reg = <0 0x3f140000 0 0x1000>;
718 reg = <0 0x3f240000 0 0x1000>;
735 reg = <0 0x3f340000 0 0x1000>;
752 reg = <0 0x3f440000 0 0x1000>;
769 reg = <0 0x3f540000 0 0x1000>;
786 reg = <0 0x3f640000 0 0x1000>;
803 reg = <0 0x3f740000 0 0x1000>;
822 ranges = <0 0x0 0x70000000 0x10000000>;
824 uart0: serial@0 {
827 reg = <0x0 0x100>;
836 reg = <0x100000 0x100>;
844 reg = <0x1100000 0x1000>;
856 reg = <0x1400000 0x1000>;
871 ranges = <0 0x0 0x32000000 0x1000000>;
875 reg = <0x100000 0x100000>;
877 #size-cells = <0>;
878 sprd,hw-channels = <2 0x18cc>, <3 0x18cc>, <13 0x1854>, <15 0x1874>,
879 <17 0x1844>,<19 0x1844>, <21 0x1864>, <30 0x1820>,
880 <35 0x19b8>, <39 0x19ac>;
887 #clock-cells = <0>;
894 #clock-cells = <0>;
901 #clock-cells = <0>;
908 #clock-cells = <0>;