Lines Matching +full:0 +full:x12003000
15 #size-cells = <0>;
46 CPU0: cpu@0 {
49 reg = <0x0 0x0>;
57 reg = <0x0 0x100>;
65 reg = <0x0 0x200>;
73 reg = <0x0 0x300>;
81 reg = <0x0 0x400>;
89 reg = <0x0 0x500>;
97 reg = <0x0 0x600>;
105 reg = <0x0 0x700>;
119 arm,psci-suspend-param = <0x00010000>;
155 redistributor-stride = <0x0 0x20000>; /* 128KB stride */
158 reg = <0x0 0x14000000 0 0x20000>, /* GICD */
159 <0x0 0x14040000 0 0x100000>; /* GICR */
165 reg = <0 0x21500000 0 0x1000>;
173 reg = <0 0x402d0000 0 0x1000>;
183 reg = <0 0x60900000 0 0x1000>;
189 reg = <0 0x10001000 0 0x1000>;
213 reg = <0 0x10003000 0 0x1000>;
229 reg = <0 0x12001000 0 0x1000>;
244 #size-cells = <0>;
246 port@0 {
247 reg = <0>;
278 reg = <0 0x12002000 0 0x1000>;
303 reg = <0 0x12003000 0 0x1000>;
328 reg = <0 0x12004000 0 0x1000>;
343 #size-cells = <0>;
345 port@0 {
346 reg = <0>;
365 reg = <0 0x12005000 0 0x1000>;
380 #size-cells = <0>;
382 port@0 {
383 reg = <0>;
414 reg = <0 0x13040000 0 0x1000>;
431 reg = <0 0x13140000 0 0x1000>;
448 reg = <0 0x13240000 0 0x1000>;
465 reg = <0 0x13340000 0 0x1000>;
482 reg = <0 0x13440000 0 0x1000>;
499 reg = <0 0x13540000 0 0x1000>;
516 reg = <0 0x13640000 0 0x1000>;
533 reg = <0 0x13740000 0 0x1000>;
556 reg = <0 0x20300000 0 0x1000>;
572 reg = <0 0x20600000 0 0x1000>;