Lines Matching +full:0 +full:x11840000
17 #size-cells = <0>;
54 reg = <0x0 0x530000>;
62 reg = <0x0 0x530001>;
70 reg = <0x0 0x530002>;
78 reg = <0x0 0x530003>;
86 reg = <0x0 0x530100>;
94 reg = <0x0 0x530101>;
102 reg = <0x0 0x530102>;
110 reg = <0x0 0x530103>;
125 arm,psci-suspend-param = <0x00010002>;
134 arm,psci-suspend-param = <0x01010003>;
140 reg = <0 0x12001000 0 0x1000>,
141 <0 0x12002000 0 0x2000>,
142 <0 0x12004000 0 0x2000>,
143 <0 0x12006000 0 0x2000>;
190 sprd,syscon = <&pmu_regs>; /* 0x402b0000 */
197 sprd,syscon = <&ana_regs>; /* 0x40400000 */
198 clocks = <&pmu_gate 0>;
204 reg = <0 0x20000000 0 0x400>;
205 clocks = <&ext_26m>, <&pll 0>,
206 <&pmu_gate 0>;
212 reg = <0 0x402d0000 0 0x400>;
213 clocks = <&ext_26m>, <&pll 0>,
214 <&pmu_gate 0>;
220 sprd,syscon = <&ap_ahb_regs>; /* 0x20210000 */
221 clocks = <&aon_prediv 0>;
227 sprd,syscon = <&aon_regs>; /* 0x402e0000 */
228 clocks = <&aon_prediv 0>;
234 reg = <0 0x40880000 0 0x400>;
235 clocks = <&ext_26m>, <&pll 0>;
241 sprd,syscon = <&agcp_regs>; /* 0x415e0000 */
242 clocks = <&aon_prediv 0>;
248 reg = <0 0x60200000 0 0x400>;
249 clocks = <&pll 0>;
255 reg = <0 0x61000000 0 0x400>;
256 clocks = <&ext_26m>, <&pll 0>;
262 sprd,syscon = <&vsp_regs>; /* 0x61100000 */
263 clocks = <&vsp_clk 0>;
269 reg = <0 0x62000000 0 0x4000>;
270 clocks = <&ext_26m>, <&pll 0>;
276 sprd,syscon = <&cam_regs>; /* 0x62100000 */
277 clocks = <&cam_clk 0>;
283 reg = <0 0x63000000 0 0x400>;
284 clocks = <&ext_26m>, <&pll 0>;
290 sprd,syscon = <&disp_regs>; /* 0x63100000 */
291 clocks = <&disp_clk 0>;
297 sprd,syscon = <&ap_apb_regs>; /* 0x70b00000 */
298 clocks = <&ap_clk 0>;
304 reg = <0 0x10001000 0 0x1000>;
317 #size-cells = <0>;
319 port@0 {
320 reg = <0>;
339 reg = <0 0x10003000 0 0x1000>;
354 reg = <0 0x10006000 0 0x1000>,
355 <0 0x01000000 0 0x180000>;
371 reg = <0 0x11001000 0 0x1000>;
385 #size-cells = <0>;
387 port@0 {
388 reg = <0>;
419 reg = <0 0x11002000 0 0x1000>;
433 #size-cells = <0>;
435 port@0 {
436 reg = <0>;
467 reg = <0 0x11003000 0 0x1000>;
492 reg = <0 0x11004000 0 0x1000>;
517 reg = <0 0x11005000 0 0x1000>;
532 #size-cells = <0>;
534 port@0 {
535 reg = <0>;
554 reg = <0 0x11440000 0 0x1000>;
571 reg = <0 0x11540000 0 0x1000>;
588 reg = <0 0x11640000 0 0x1000>;
605 reg = <0 0x11740000 0 0x1000>;
622 reg = <0 0x11840000 0 0x1000>;
639 reg = <0 0x11940000 0 0x1000>;
656 reg = <0 0x11a40000 0 0x1000>;
673 reg = <0 0x11b40000 0 0x1000>;