Lines Matching +full:default +full:- +full:trim
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/thermal/thermal.h>
14 compatible = "socionext,uniphier-pxs3";
15 #address-cells = <2>;
16 #size-cells = <2>;
17 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <0>;
23 cpu-map {
42 compatible = "arm,cortex-a53";
45 enable-method = "psci";
46 next-level-cache = <&l2>;
47 operating-points-v2 = <&cluster0_opp>;
48 #cooling-cells = <2>;
53 compatible = "arm,cortex-a53";
56 enable-method = "psci";
57 next-level-cache = <&l2>;
58 operating-points-v2 = <&cluster0_opp>;
59 #cooling-cells = <2>;
64 compatible = "arm,cortex-a53";
67 enable-method = "psci";
68 next-level-cache = <&l2>;
69 operating-points-v2 = <&cluster0_opp>;
70 #cooling-cells = <2>;
75 compatible = "arm,cortex-a53";
78 enable-method = "psci";
79 next-level-cache = <&l2>;
80 operating-points-v2 = <&cluster0_opp>;
81 #cooling-cells = <2>;
84 l2: l2-cache {
86 cache-level = <2>;
87 cache-unified;
91 cluster0_opp: opp-table {
92 compatible = "operating-points-v2";
93 opp-shared;
95 opp-250000000 {
96 opp-hz = /bits/ 64 <250000000>;
97 clock-latency-ns = <300>;
99 opp-325000000 {
100 opp-hz = /bits/ 64 <325000000>;
101 clock-latency-ns = <300>;
103 opp-500000000 {
104 opp-hz = /bits/ 64 <500000000>;
105 clock-latency-ns = <300>;
107 opp-650000000 {
108 opp-hz = /bits/ 64 <650000000>;
109 clock-latency-ns = <300>;
111 opp-666667000 {
112 opp-hz = /bits/ 64 <666667000>;
113 clock-latency-ns = <300>;
115 opp-866667000 {
116 opp-hz = /bits/ 64 <866667000>;
117 clock-latency-ns = <300>;
119 opp-1000000000 {
120 opp-hz = /bits/ 64 <1000000000>;
121 clock-latency-ns = <300>;
123 opp-1300000000 {
124 opp-hz = /bits/ 64 <1300000000>;
125 clock-latency-ns = <300>;
130 compatible = "arm,psci-1.0";
136 compatible = "fixed-clock";
137 #clock-cells = <0>;
138 clock-frequency = <25000000>;
142 emmc_pwrseq: emmc-pwrseq {
143 compatible = "mmc-pwrseq-emmc";
144 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(5, 7) GPIO_ACTIVE_LOW>;
148 compatible = "arm,armv8-timer";
155 thermal-zones {
156 cpu-thermal {
157 polling-delay-passive = <250>; /* 250ms */
158 polling-delay = <1000>; /* 1000ms */
159 thermal-sensors = <&pvtctl>;
162 cpu_crit: cpu-crit {
167 cpu_alert: cpu-alert {
174 cooling-maps {
177 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
186 reserved-memory {
187 #address-cells = <2>;
188 #size-cells = <2>;
191 secure-memory@81000000 {
193 no-map;
198 compatible = "simple-bus";
199 #address-cells = <1>;
200 #size-cells = <1>;
204 compatible = "socionext,uniphier-scssi";
207 #address-cells = <1>;
208 #size-cells = <0>;
210 pinctrl-names = "default";
211 pinctrl-0 = <&pinctrl_spi0>;
217 compatible = "socionext,uniphier-scssi";
220 #address-cells = <1>;
221 #size-cells = <0>;
223 pinctrl-names = "default";
224 pinctrl-0 = <&pinctrl_spi1>;
230 compatible = "socionext,uniphier-uart";
234 pinctrl-names = "default";
235 pinctrl-0 = <&pinctrl_uart0>;
241 compatible = "socionext,uniphier-uart";
245 pinctrl-names = "default";
246 pinctrl-0 = <&pinctrl_uart1>;
252 compatible = "socionext,uniphier-uart";
256 pinctrl-names = "default";
257 pinctrl-0 = <&pinctrl_uart2>;
263 compatible = "socionext,uniphier-uart";
267 pinctrl-names = "default";
268 pinctrl-0 = <&pinctrl_uart3>;
274 compatible = "socionext,uniphier-gpio";
276 interrupt-parent = <&aidet>;
277 interrupt-controller;
278 #interrupt-cells = <2>;
279 gpio-controller;
280 #gpio-cells = <2>;
281 gpio-ranges = <&pinctrl 0 0 0>,
284 gpio-ranges-group-names = "gpio_range0",
288 socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
293 compatible = "socionext,uniphier-fi2c";
296 #address-cells = <1>;
297 #size-cells = <0>;
299 pinctrl-names = "default";
300 pinctrl-0 = <&pinctrl_i2c0>;
303 clock-frequency = <100000>;
307 compatible = "socionext,uniphier-fi2c";
310 #address-cells = <1>;
311 #size-cells = <0>;
313 pinctrl-names = "default";
314 pinctrl-0 = <&pinctrl_i2c1>;
317 clock-frequency = <100000>;
321 compatible = "socionext,uniphier-fi2c";
324 #address-cells = <1>;
325 #size-cells = <0>;
327 pinctrl-names = "default";
328 pinctrl-0 = <&pinctrl_i2c2>;
331 clock-frequency = <100000>;
335 compatible = "socionext,uniphier-fi2c";
338 #address-cells = <1>;
339 #size-cells = <0>;
341 pinctrl-names = "default";
342 pinctrl-0 = <&pinctrl_i2c3>;
345 clock-frequency = <100000>;
348 /* chip-internal connection for HDMI */
350 compatible = "socionext,uniphier-fi2c";
352 #address-cells = <1>;
353 #size-cells = <0>;
357 clock-frequency = <400000>;
360 system_bus: system-bus@58c00000 {
361 compatible = "socionext,uniphier-system-bus";
364 #address-cells = <2>;
365 #size-cells = <1>;
366 pinctrl-names = "default";
367 pinctrl-0 = <&pinctrl_system_bus>;
371 compatible = "socionext,uniphier-smpctrl";
376 compatible = "socionext,uniphier-pxs3-sdctrl",
377 "simple-mfd", "syscon";
380 sd_clk: clock-controller {
381 compatible = "socionext,uniphier-pxs3-sd-clock";
382 #clock-cells = <1>;
385 sd_rst: reset-controller {
386 compatible = "socionext,uniphier-pxs3-sd-reset";
387 #reset-cells = <1>;
392 compatible = "socionext,uniphier-pxs3-perictrl",
393 "simple-mfd", "syscon";
396 peri_clk: clock-controller {
397 compatible = "socionext,uniphier-pxs3-peri-clock";
398 #clock-cells = <1>;
401 peri_rst: reset-controller {
402 compatible = "socionext,uniphier-pxs3-peri-reset";
403 #reset-cells = <1>;
408 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
411 pinctrl-names = "default";
412 pinctrl-0 = <&pinctrl_emmc>;
415 bus-width = <8>;
416 mmc-ddr-1_8v;
417 mmc-hs200-1_8v;
418 mmc-pwrseq = <&emmc_pwrseq>;
419 cdns,phy-input-delay-legacy = <9>;
420 cdns,phy-input-delay-mmc-highspeed = <2>;
421 cdns,phy-input-delay-mmc-ddr = <3>;
422 cdns,phy-dll-delay-sdclk = <21>;
423 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
427 compatible = "socionext,uniphier-sd-v3.1.1";
431 pinctrl-names = "default", "uhs";
432 pinctrl-0 = <&pinctrl_sd>;
433 pinctrl-1 = <&pinctrl_sd_uhs>;
435 reset-names = "host";
437 bus-width = <4>;
438 cap-sd-highspeed;
439 sd-uhs-sdr12;
440 sd-uhs-sdr25;
441 sd-uhs-sdr50;
442 socionext,syscon-uhs-mode = <&sdctrl 0>;
446 compatible = "socionext,uniphier-pxs3-soc-glue",
447 "simple-mfd", "syscon";
451 compatible = "socionext,uniphier-pxs3-pinctrl";
456 compatible = "socionext,uniphier-pxs3-soc-glue-debug",
457 "simple-mfd", "syscon";
459 #address-cells = <1>;
460 #size-cells = <1>;
464 compatible = "socionext,uniphier-efuse";
469 compatible = "socionext,uniphier-efuse";
471 #address-cells = <1>;
472 #size-cells = <1>;
475 usb_rterm0: trim@54,4 {
479 usb_rterm1: trim@55,4 {
483 usb_rterm2: trim@58,4 {
487 usb_rterm3: trim@59,4 {
491 usb_sel_t0: trim@54,0 {
495 usb_sel_t1: trim@55,0 {
499 usb_sel_t2: trim@58,0 {
503 usb_sel_t3: trim@59,0 {
507 usb_hs_i0: trim@56,0 {
511 usb_hs_i2: trim@5a,0 {
518 xdmac: dma-controller@5fc10000 {
519 compatible = "socionext,uniphier-xdmac";
522 dma-channels = <16>;
523 #dma-cells = <2>;
526 aidet: interrupt-controller@5fc20000 {
527 compatible = "socionext,uniphier-pxs3-aidet";
529 interrupt-controller;
530 #interrupt-cells = <2>;
533 gic: interrupt-controller@5fe00000 {
534 compatible = "arm,gic-v3";
537 interrupt-controller;
538 #interrupt-cells = <3>;
543 compatible = "socionext,uniphier-pxs3-sysctrl",
544 "simple-mfd", "syscon";
547 sys_clk: clock-controller {
548 compatible = "socionext,uniphier-pxs3-clock";
549 #clock-cells = <1>;
552 sys_rst: reset-controller {
553 compatible = "socionext,uniphier-pxs3-reset";
554 #reset-cells = <1>;
558 compatible = "socionext,uniphier-wdt";
561 pvtctl: thermal-sensor {
562 compatible = "socionext,uniphier-pxs3-thermal";
564 #thermal-sensor-cells = <0>;
565 socionext,tmod-calibration = <0x0f22 0x68ee>;
570 compatible = "socionext,uniphier-pxs3-ave4";
574 pinctrl-names = "default";
575 pinctrl-0 = <&pinctrl_ether_rgmii>;
576 clock-names = "ether";
578 reset-names = "ether";
580 phy-mode = "rgmii-id";
581 local-mac-address = [00 00 00 00 00 00];
582 socionext,syscon-phy-mode = <&soc_glue 0>;
585 #address-cells = <1>;
586 #size-cells = <0>;
591 compatible = "socionext,uniphier-pxs3-ave4";
595 pinctrl-names = "default";
596 pinctrl-0 = <&pinctrl_ether1_rgmii>;
597 clock-names = "ether";
599 reset-names = "ether";
601 phy-mode = "rgmii-id";
602 local-mac-address = [00 00 00 00 00 00];
603 socionext,syscon-phy-mode = <&soc_glue 1>;
606 #address-cells = <1>;
607 #size-cells = <0>;
612 compatible = "socionext,uniphier-pxs3-ahci",
613 "generic-ahci";
619 ports-implemented = <1>;
623 sata-controller@65700000 {
624 compatible = "socionext,uniphier-pxs3-ahci-glue",
625 "simple-mfd";
627 #address-cells = <1>;
628 #size-cells = <1>;
631 ahci0_rst: reset-controller@0 {
632 compatible = "socionext,uniphier-pxs3-ahci-reset";
634 clock-names = "link";
636 reset-names = "link";
638 #reset-cells = <1>;
641 ahci0_phy: sata-phy@10 {
642 compatible = "socionext,uniphier-pxs3-ahci-phy";
644 clock-names = "link", "phy";
646 reset-names = "link", "phy";
648 #phy-cells = <0>;
653 compatible = "socionext,uniphier-pxs3-ahci",
654 "generic-ahci";
660 ports-implemented = <1>;
664 sata-controller@65900000 {
665 compatible = "socionext,uniphier-pxs3-ahci-glue",
666 "simple-mfd";
668 #address-cells = <1>;
669 #size-cells = <1>;
672 ahci1_rst: reset-controller@0 {
673 compatible = "socionext,uniphier-pxs3-ahci-reset";
675 clock-names = "link";
677 reset-names = "link";
679 #reset-cells = <1>;
682 ahci1_phy: sata-phy@10 {
683 compatible = "socionext,uniphier-pxs3-ahci-phy";
685 clock-names = "link", "phy";
687 reset-names = "link", "phy";
689 #phy-cells = <0>;
694 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
697 interrupt-names = "dwc_usb3";
699 pinctrl-names = "default";
700 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
701 clock-names = "ref", "bus_early", "suspend";
709 usb-controller@65b00000 {
710 compatible = "socionext,uniphier-pxs3-dwc3-glue",
711 "simple-mfd";
713 #address-cells = <1>;
714 #size-cells = <1>;
717 usb0_rst: reset-controller@0 {
718 compatible = "socionext,uniphier-pxs3-usb3-reset";
720 #reset-cells = <1>;
721 clock-names = "link";
723 reset-names = "link";
728 compatible = "socionext,uniphier-pxs3-usb3-regulator";
730 clock-names = "link";
732 reset-names = "link";
737 compatible = "socionext,uniphier-pxs3-usb3-regulator";
739 clock-names = "link";
741 reset-names = "link";
746 compatible = "socionext,uniphier-pxs3-usb3-hsphy";
748 #phy-cells = <0>;
749 clock-names = "link", "phy";
751 reset-names = "link", "phy";
753 vbus-supply = <&usb0_vbus0>;
754 nvmem-cell-names = "rterm", "sel_t", "hs_i";
755 nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>,
760 compatible = "socionext,uniphier-pxs3-usb3-hsphy";
762 #phy-cells = <0>;
763 clock-names = "link", "phy";
765 reset-names = "link", "phy";
767 vbus-supply = <&usb0_vbus1>;
768 nvmem-cell-names = "rterm", "sel_t", "hs_i";
769 nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>,
774 compatible = "socionext,uniphier-pxs3-usb3-ssphy";
776 #phy-cells = <0>;
777 clock-names = "link", "phy";
779 reset-names = "link", "phy";
781 vbus-supply = <&usb0_vbus0>;
785 compatible = "socionext,uniphier-pxs3-usb3-ssphy";
787 #phy-cells = <0>;
788 clock-names = "link", "phy";
790 reset-names = "link", "phy";
792 vbus-supply = <&usb0_vbus1>;
797 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
800 interrupt-names = "dwc_usb3";
802 pinctrl-names = "default";
803 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
804 clock-names = "ref", "bus_early", "suspend";
812 usb-controller@65d00000 {
813 compatible = "socionext,uniphier-pxs3-dwc3-glue",
814 "simple-mfd";
816 #address-cells = <1>;
817 #size-cells = <1>;
820 usb1_rst: reset-controller@0 {
821 compatible = "socionext,uniphier-pxs3-usb3-reset";
823 #reset-cells = <1>;
824 clock-names = "link";
826 reset-names = "link";
831 compatible = "socionext,uniphier-pxs3-usb3-regulator";
833 clock-names = "link";
835 reset-names = "link";
840 compatible = "socionext,uniphier-pxs3-usb3-regulator";
842 clock-names = "link";
844 reset-names = "link";
849 compatible = "socionext,uniphier-pxs3-usb3-hsphy";
851 #phy-cells = <0>;
852 clock-names = "link", "phy", "phy-ext";
855 reset-names = "link", "phy";
857 vbus-supply = <&usb1_vbus0>;
858 nvmem-cell-names = "rterm", "sel_t", "hs_i";
859 nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>,
864 compatible = "socionext,uniphier-pxs3-usb3-hsphy";
866 #phy-cells = <0>;
867 clock-names = "link", "phy", "phy-ext";
870 reset-names = "link", "phy";
872 vbus-supply = <&usb1_vbus1>;
873 nvmem-cell-names = "rterm", "sel_t", "hs_i";
874 nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>,
879 compatible = "socionext,uniphier-pxs3-usb3-ssphy";
881 #phy-cells = <0>;
882 clock-names = "link", "phy", "phy-ext";
885 reset-names = "link", "phy";
887 vbus-supply = <&usb1_vbus0>;
892 compatible = "socionext,uniphier-pcie";
894 reg-names = "dbi", "link", "config";
897 #address-cells = <3>;
898 #size-cells = <2>;
901 num-lanes = <1>;
902 num-viewport = <1>;
903 bus-range = <0x0 0xff>;
908 /* non-prefetchable memory */
910 #interrupt-cells = <1>;
911 interrupt-names = "dma", "msi";
914 interrupt-map-mask = <0 0 0 7>;
915 interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */
919 phy-names = "pcie-phy";
922 pcie_intc: legacy-interrupt-controller {
923 interrupt-controller;
924 #interrupt-cells = <1>;
925 interrupt-parent = <&gic>;
931 compatible = "socionext,uniphier-pxs3-pcie-phy";
933 #phy-cells = <0>;
934 clock-names = "link";
936 reset-names = "link";
941 nand: nand-controller@68000000 {
942 compatible = "socionext,uniphier-denali-nand-v5b";
944 reg-names = "nand_data", "denali_reg";
946 #address-cells = <1>;
947 #size-cells = <0>;
949 pinctrl-names = "default";
950 pinctrl-0 = <&pinctrl_nand>;
951 clock-names = "nand", "nand_x", "ecc";
953 reset-names = "nand", "reg";
959 #include "uniphier-pinctrl.dtsi"