Lines Matching +full:uniphier +full:- +full:evea
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier LD20 SoC
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/thermal/thermal.h>
14 compatible = "socionext,uniphier-ld20";
15 #address-cells = <2>;
16 #size-cells = <2>;
17 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <0>;
23 cpu-map {
45 compatible = "arm,cortex-a72";
48 enable-method = "psci";
49 next-level-cache = <&a72_l2>;
50 operating-points-v2 = <&cluster0_opp>;
51 #cooling-cells = <2>;
56 compatible = "arm,cortex-a72";
59 enable-method = "psci";
60 next-level-cache = <&a72_l2>;
61 operating-points-v2 = <&cluster0_opp>;
62 #cooling-cells = <2>;
67 compatible = "arm,cortex-a53";
70 enable-method = "psci";
71 next-level-cache = <&a53_l2>;
72 operating-points-v2 = <&cluster1_opp>;
73 #cooling-cells = <2>;
78 compatible = "arm,cortex-a53";
81 enable-method = "psci";
82 next-level-cache = <&a53_l2>;
83 operating-points-v2 = <&cluster1_opp>;
84 #cooling-cells = <2>;
87 a72_l2: l2-cache0 {
89 cache-level = <2>;
90 cache-unified;
93 a53_l2: l2-cache1 {
95 cache-level = <2>;
96 cache-unified;
100 cluster0_opp: opp-table-0 {
101 compatible = "operating-points-v2";
102 opp-shared;
104 opp-250000000 {
105 opp-hz = /bits/ 64 <250000000>;
106 clock-latency-ns = <300>;
108 opp-275000000 {
109 opp-hz = /bits/ 64 <275000000>;
110 clock-latency-ns = <300>;
112 opp-500000000 {
113 opp-hz = /bits/ 64 <500000000>;
114 clock-latency-ns = <300>;
116 opp-550000000 {
117 opp-hz = /bits/ 64 <550000000>;
118 clock-latency-ns = <300>;
120 opp-666667000 {
121 opp-hz = /bits/ 64 <666667000>;
122 clock-latency-ns = <300>;
124 opp-733334000 {
125 opp-hz = /bits/ 64 <733334000>;
126 clock-latency-ns = <300>;
128 opp-1000000000 {
129 opp-hz = /bits/ 64 <1000000000>;
130 clock-latency-ns = <300>;
132 opp-1100000000 {
133 opp-hz = /bits/ 64 <1100000000>;
134 clock-latency-ns = <300>;
138 cluster1_opp: opp-table-1 {
139 compatible = "operating-points-v2";
140 opp-shared;
142 opp-250000000 {
143 opp-hz = /bits/ 64 <250000000>;
144 clock-latency-ns = <300>;
146 opp-275000000 {
147 opp-hz = /bits/ 64 <275000000>;
148 clock-latency-ns = <300>;
150 opp-500000000 {
151 opp-hz = /bits/ 64 <500000000>;
152 clock-latency-ns = <300>;
154 opp-550000000 {
155 opp-hz = /bits/ 64 <550000000>;
156 clock-latency-ns = <300>;
158 opp-666667000 {
159 opp-hz = /bits/ 64 <666667000>;
160 clock-latency-ns = <300>;
162 opp-733334000 {
163 opp-hz = /bits/ 64 <733334000>;
164 clock-latency-ns = <300>;
166 opp-1000000000 {
167 opp-hz = /bits/ 64 <1000000000>;
168 clock-latency-ns = <300>;
170 opp-1100000000 {
171 opp-hz = /bits/ 64 <1100000000>;
172 clock-latency-ns = <300>;
177 compatible = "arm,psci-1.0";
183 compatible = "fixed-clock";
184 #clock-cells = <0>;
185 clock-frequency = <25000000>;
189 emmc_pwrseq: emmc-pwrseq {
190 compatible = "mmc-pwrseq-emmc";
191 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(3, 2) GPIO_ACTIVE_LOW>;
195 compatible = "arm,armv8-timer";
202 thermal-zones {
203 cpu-thermal {
204 polling-delay-passive = <250>; /* 250ms */
205 polling-delay = <1000>; /* 1000ms */
206 thermal-sensors = <&pvtctl>;
209 cpu_crit: cpu-crit {
214 cpu_alert: cpu-alert {
221 cooling-maps {
224 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
233 reserved-memory {
234 #address-cells = <2>;
235 #size-cells = <2>;
238 secure-memory@81000000 {
240 no-map;
245 compatible = "simple-bus";
246 #address-cells = <1>;
247 #size-cells = <1>;
251 compatible = "socionext,uniphier-scssi";
254 #address-cells = <1>;
255 #size-cells = <0>;
257 pinctrl-names = "default";
258 pinctrl-0 = <&pinctrl_spi0>;
264 compatible = "socionext,uniphier-scssi";
267 #address-cells = <1>;
268 #size-cells = <0>;
270 pinctrl-names = "default";
271 pinctrl-0 = <&pinctrl_spi1>;
277 compatible = "socionext,uniphier-scssi";
280 #address-cells = <1>;
281 #size-cells = <0>;
283 pinctrl-names = "default";
284 pinctrl-0 = <&pinctrl_spi2>;
290 compatible = "socionext,uniphier-scssi";
293 #address-cells = <1>;
294 #size-cells = <0>;
296 pinctrl-names = "default";
297 pinctrl-0 = <&pinctrl_spi3>;
303 compatible = "socionext,uniphier-uart";
307 pinctrl-names = "default";
308 pinctrl-0 = <&pinctrl_uart0>;
314 compatible = "socionext,uniphier-uart";
318 pinctrl-names = "default";
319 pinctrl-0 = <&pinctrl_uart1>;
325 compatible = "socionext,uniphier-uart";
329 pinctrl-names = "default";
330 pinctrl-0 = <&pinctrl_uart2>;
336 compatible = "socionext,uniphier-uart";
340 pinctrl-names = "default";
341 pinctrl-0 = <&pinctrl_uart3>;
347 compatible = "socionext,uniphier-gpio";
349 interrupt-parent = <&aidet>;
350 interrupt-controller;
351 #interrupt-cells = <2>;
352 gpio-controller;
353 #gpio-cells = <2>;
354 gpio-ranges = <&pinctrl 0 0 0>,
357 gpio-ranges-group-names = "gpio_range0",
361 socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
366 compatible = "socionext,uniphier-ld20-aio";
369 pinctrl-names = "default";
370 pinctrl-0 = <&pinctrl_aout1>,
372 clock-names = "aio";
374 reset-names = "aio";
376 #sound-dai-cells = <1>;
391 dai-format = "i2s";
392 remote-endpoint = <&evea_line>;
403 dai-format = "i2s";
404 remote-endpoint = <&evea_hp>;
430 compatible = "socionext,uniphier-evea";
432 clock-names = "evea", "exiv";
434 reset-names = "evea", "exiv", "adamv";
436 #sound-dai-cells = <1>;
440 remote-endpoint = <&i2s_line>;
446 remote-endpoint = <&i2s_hp>;
452 compatible = "socionext,uniphier-ld20-adamv",
453 "simple-mfd", "syscon";
456 adamv_rst: reset-controller {
457 compatible = "socionext,uniphier-ld20-adamv-reset";
458 #reset-cells = <1>;
463 compatible = "socionext,uniphier-fi2c";
466 #address-cells = <1>;
467 #size-cells = <0>;
469 pinctrl-names = "default";
470 pinctrl-0 = <&pinctrl_i2c0>;
473 clock-frequency = <100000>;
477 compatible = "socionext,uniphier-fi2c";
480 #address-cells = <1>;
481 #size-cells = <0>;
483 pinctrl-names = "default";
484 pinctrl-0 = <&pinctrl_i2c1>;
487 clock-frequency = <100000>;
491 compatible = "socionext,uniphier-fi2c";
493 #address-cells = <1>;
494 #size-cells = <0>;
498 clock-frequency = <400000>;
502 compatible = "socionext,uniphier-fi2c";
505 #address-cells = <1>;
506 #size-cells = <0>;
508 pinctrl-names = "default";
509 pinctrl-0 = <&pinctrl_i2c3>;
512 clock-frequency = <100000>;
516 compatible = "socionext,uniphier-fi2c";
519 #address-cells = <1>;
520 #size-cells = <0>;
522 pinctrl-names = "default";
523 pinctrl-0 = <&pinctrl_i2c4>;
526 clock-frequency = <100000>;
530 compatible = "socionext,uniphier-fi2c";
532 #address-cells = <1>;
533 #size-cells = <0>;
537 clock-frequency = <400000>;
540 system_bus: system-bus@58c00000 {
541 compatible = "socionext,uniphier-system-bus";
544 #address-cells = <2>;
545 #size-cells = <1>;
546 pinctrl-names = "default";
547 pinctrl-0 = <&pinctrl_system_bus>;
551 compatible = "socionext,uniphier-smpctrl";
556 compatible = "socionext,uniphier-ld20-sdctrl",
557 "simple-mfd", "syscon";
560 sd_clk: clock-controller {
561 compatible = "socionext,uniphier-ld20-sd-clock";
562 #clock-cells = <1>;
565 sd_rst: reset-controller {
566 compatible = "socionext,uniphier-ld20-sd-reset";
567 #reset-cells = <1>;
572 compatible = "socionext,uniphier-ld20-perictrl",
573 "simple-mfd", "syscon";
576 peri_clk: clock-controller {
577 compatible = "socionext,uniphier-ld20-peri-clock";
578 #clock-cells = <1>;
581 peri_rst: reset-controller {
582 compatible = "socionext,uniphier-ld20-peri-reset";
583 #reset-cells = <1>;
588 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
591 pinctrl-names = "default";
592 pinctrl-0 = <&pinctrl_emmc>;
595 bus-width = <8>;
596 mmc-ddr-1_8v;
597 mmc-hs200-1_8v;
598 mmc-pwrseq = <&emmc_pwrseq>;
599 cdns,phy-input-delay-legacy = <9>;
600 cdns,phy-input-delay-mmc-highspeed = <2>;
601 cdns,phy-input-delay-mmc-ddr = <3>;
602 cdns,phy-dll-delay-sdclk = <21>;
603 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
607 compatible = "socionext,uniphier-sd-v3.1.1";
611 pinctrl-names = "default";
612 pinctrl-0 = <&pinctrl_sd>;
614 reset-names = "host";
616 bus-width = <4>;
617 cap-sd-highspeed;
618 socionext,syscon-uhs-mode = <&sdctrl 0>;
622 compatible = "socionext,uniphier-ld20-soc-glue",
623 "simple-mfd", "syscon";
627 compatible = "socionext,uniphier-ld20-pinctrl";
632 compatible = "socionext,uniphier-ld20-soc-glue-debug",
633 "simple-mfd", "syscon";
635 #address-cells = <1>;
636 #size-cells = <1>;
640 compatible = "socionext,uniphier-efuse";
645 compatible = "socionext,uniphier-efuse";
647 #address-cells = <1>;
648 #size-cells = <1>;
694 xdmac: dma-controller@5fc10000 {
695 compatible = "socionext,uniphier-xdmac";
698 dma-channels = <16>;
699 #dma-cells = <2>;
702 aidet: interrupt-controller@5fc20000 {
703 compatible = "socionext,uniphier-ld20-aidet";
705 interrupt-controller;
706 #interrupt-cells = <2>;
709 gic: interrupt-controller@5fe00000 {
710 compatible = "arm,gic-v3";
713 interrupt-controller;
714 #interrupt-cells = <3>;
719 compatible = "socionext,uniphier-ld20-sysctrl",
720 "simple-mfd", "syscon";
723 sys_clk: clock-controller {
724 compatible = "socionext,uniphier-ld20-clock";
725 #clock-cells = <1>;
728 sys_rst: reset-controller {
729 compatible = "socionext,uniphier-ld20-reset";
730 #reset-cells = <1>;
734 compatible = "socionext,uniphier-wdt";
737 pvtctl: thermal-sensor {
738 compatible = "socionext,uniphier-ld20-thermal";
740 #thermal-sensor-cells = <0>;
741 socionext,tmod-calibration = <0x0f22 0x68ee>;
746 compatible = "socionext,uniphier-ld20-ave4";
750 pinctrl-names = "default";
751 pinctrl-0 = <&pinctrl_ether_rgmii>;
752 clock-names = "ether";
754 reset-names = "ether";
756 phy-mode = "rgmii-id";
757 local-mac-address = [00 00 00 00 00 00];
758 socionext,syscon-phy-mode = <&soc_glue 0>;
761 #address-cells = <1>;
762 #size-cells = <0>;
767 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
770 interrupt-names = "host";
772 pinctrl-names = "default";
773 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb1>,
775 clock-names = "ref", "bus_early", "suspend";
784 usb-controller@65b00000 {
785 compatible = "socionext,uniphier-ld20-dwc3-glue",
786 "simple-mfd";
788 #address-cells = <1>;
789 #size-cells = <1>;
792 usb_rst: reset-controller@0 {
793 compatible = "socionext,uniphier-ld20-usb3-reset";
795 #reset-cells = <1>;
796 clock-names = "link";
798 reset-names = "link";
803 compatible = "socionext,uniphier-ld20-usb3-regulator";
805 clock-names = "link";
807 reset-names = "link";
812 compatible = "socionext,uniphier-ld20-usb3-regulator";
814 clock-names = "link";
816 reset-names = "link";
821 compatible = "socionext,uniphier-ld20-usb3-regulator";
823 clock-names = "link";
825 reset-names = "link";
830 compatible = "socionext,uniphier-ld20-usb3-regulator";
832 clock-names = "link";
834 reset-names = "link";
839 compatible = "socionext,uniphier-ld20-usb3-hsphy";
841 #phy-cells = <0>;
842 clock-names = "link", "phy";
844 reset-names = "link", "phy";
846 vbus-supply = <&usb_vbus0>;
847 nvmem-cell-names = "rterm", "sel_t", "hs_i";
848 nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>,
853 compatible = "socionext,uniphier-ld20-usb3-hsphy";
855 #phy-cells = <0>;
856 clock-names = "link", "phy";
858 reset-names = "link", "phy";
860 vbus-supply = <&usb_vbus1>;
861 nvmem-cell-names = "rterm", "sel_t", "hs_i";
862 nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>,
867 compatible = "socionext,uniphier-ld20-usb3-hsphy";
869 #phy-cells = <0>;
870 clock-names = "link", "phy";
872 reset-names = "link", "phy";
874 vbus-supply = <&usb_vbus2>;
875 nvmem-cell-names = "rterm", "sel_t", "hs_i";
876 nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>,
881 compatible = "socionext,uniphier-ld20-usb3-hsphy";
883 #phy-cells = <0>;
884 clock-names = "link", "phy";
886 reset-names = "link", "phy";
888 vbus-supply = <&usb_vbus3>;
889 nvmem-cell-names = "rterm", "sel_t", "hs_i";
890 nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>,
895 compatible = "socionext,uniphier-ld20-usb3-ssphy";
897 #phy-cells = <0>;
898 clock-names = "link", "phy";
900 reset-names = "link", "phy";
902 vbus-supply = <&usb_vbus0>;
906 compatible = "socionext,uniphier-ld20-usb3-ssphy";
908 #phy-cells = <0>;
909 clock-names = "link", "phy";
911 reset-names = "link", "phy";
913 vbus-supply = <&usb_vbus1>;
918 compatible = "socionext,uniphier-pcie";
920 reg-names = "dbi", "link", "config";
923 #address-cells = <3>;
924 #size-cells = <2>;
927 num-lanes = <1>;
928 num-viewport = <1>;
929 bus-range = <0x0 0xff>;
934 /* non-prefetchable memory */
936 #interrupt-cells = <1>;
937 interrupt-names = "dma", "msi";
940 interrupt-map-mask = <0 0 0 7>;
941 interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */
945 phy-names = "pcie-phy";
948 pcie_intc: legacy-interrupt-controller {
949 interrupt-controller;
950 #interrupt-cells = <1>;
951 interrupt-parent = <&gic>;
957 compatible = "socionext,uniphier-ld20-pcie-phy";
959 #phy-cells = <0>;
960 clock-names = "link";
962 reset-names = "link";
967 nand: nand-controller@68000000 {
968 compatible = "socionext,uniphier-denali-nand-v5b";
970 reg-names = "nand_data", "denali_reg";
972 #address-cells = <1>;
973 #size-cells = <0>;
975 pinctrl-names = "default";
976 pinctrl-0 = <&pinctrl_nand>;
977 clock-names = "nand", "nand_x", "ecc";
979 reset-names = "nand", "reg";
985 #include "uniphier-pinctrl.dtsi"
988 drive-strength = <4>; /* default: 3.5mA */
992 drive-strength = <5>; /* 5mA */
997 drive-strength = <4>; /* default: 3.5mA */
1001 drive-strength = <11>; /* 11mA */