Lines Matching +full:rk3588 +full:- +full:cru
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rockchip,rk3588-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/power/rk3588-power.h>
10 #include <dt-bindings/reset/rockchip,rk3588-cru.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/ata/ahci.h>
15 compatible = "rockchip,rk3588";
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
54 #address-cells = <1>;
55 #size-cells = <0>;
57 cpu-map {
92 compatible = "arm,cortex-a55";
94 enable-method = "psci";
95 capacity-dmips-mhz = <530>;
97 assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>;
98 assigned-clock-rates = <816000000>;
99 cpu-idle-states = <&CPU_SLEEP>;
100 i-cache-size = <32768>;
101 i-cache-line-size = <64>;
102 i-cache-sets = <128>;
103 d-cache-size = <32768>;
104 d-cache-line-size = <64>;
105 d-cache-sets = <128>;
106 next-level-cache = <&l2_cache_l0>;
107 dynamic-power-coefficient = <228>;
108 #cooling-cells = <2>;
113 compatible = "arm,cortex-a55";
115 enable-method = "psci";
116 capacity-dmips-mhz = <530>;
118 cpu-idle-states = <&CPU_SLEEP>;
119 i-cache-size = <32768>;
120 i-cache-line-size = <64>;
121 i-cache-sets = <128>;
122 d-cache-size = <32768>;
123 d-cache-line-size = <64>;
124 d-cache-sets = <128>;
125 next-level-cache = <&l2_cache_l1>;
126 dynamic-power-coefficient = <228>;
127 #cooling-cells = <2>;
132 compatible = "arm,cortex-a55";
134 enable-method = "psci";
135 capacity-dmips-mhz = <530>;
137 cpu-idle-states = <&CPU_SLEEP>;
138 i-cache-size = <32768>;
139 i-cache-line-size = <64>;
140 i-cache-sets = <128>;
141 d-cache-size = <32768>;
142 d-cache-line-size = <64>;
143 d-cache-sets = <128>;
144 next-level-cache = <&l2_cache_l2>;
145 dynamic-power-coefficient = <228>;
146 #cooling-cells = <2>;
151 compatible = "arm,cortex-a55";
153 enable-method = "psci";
154 capacity-dmips-mhz = <530>;
156 cpu-idle-states = <&CPU_SLEEP>;
157 i-cache-size = <32768>;
158 i-cache-line-size = <64>;
159 i-cache-sets = <128>;
160 d-cache-size = <32768>;
161 d-cache-line-size = <64>;
162 d-cache-sets = <128>;
163 next-level-cache = <&l2_cache_l3>;
164 dynamic-power-coefficient = <228>;
165 #cooling-cells = <2>;
170 compatible = "arm,cortex-a76";
172 enable-method = "psci";
173 capacity-dmips-mhz = <1024>;
175 assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>;
176 assigned-clock-rates = <816000000>;
177 cpu-idle-states = <&CPU_SLEEP>;
178 i-cache-size = <65536>;
179 i-cache-line-size = <64>;
180 i-cache-sets = <256>;
181 d-cache-size = <65536>;
182 d-cache-line-size = <64>;
183 d-cache-sets = <256>;
184 next-level-cache = <&l2_cache_b0>;
185 dynamic-power-coefficient = <416>;
186 #cooling-cells = <2>;
191 compatible = "arm,cortex-a76";
193 enable-method = "psci";
194 capacity-dmips-mhz = <1024>;
196 cpu-idle-states = <&CPU_SLEEP>;
197 i-cache-size = <65536>;
198 i-cache-line-size = <64>;
199 i-cache-sets = <256>;
200 d-cache-size = <65536>;
201 d-cache-line-size = <64>;
202 d-cache-sets = <256>;
203 next-level-cache = <&l2_cache_b1>;
204 dynamic-power-coefficient = <416>;
205 #cooling-cells = <2>;
210 compatible = "arm,cortex-a76";
212 enable-method = "psci";
213 capacity-dmips-mhz = <1024>;
215 assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>;
216 assigned-clock-rates = <816000000>;
217 cpu-idle-states = <&CPU_SLEEP>;
218 i-cache-size = <65536>;
219 i-cache-line-size = <64>;
220 i-cache-sets = <256>;
221 d-cache-size = <65536>;
222 d-cache-line-size = <64>;
223 d-cache-sets = <256>;
224 next-level-cache = <&l2_cache_b2>;
225 dynamic-power-coefficient = <416>;
226 #cooling-cells = <2>;
231 compatible = "arm,cortex-a76";
233 enable-method = "psci";
234 capacity-dmips-mhz = <1024>;
236 cpu-idle-states = <&CPU_SLEEP>;
237 i-cache-size = <65536>;
238 i-cache-line-size = <64>;
239 i-cache-sets = <256>;
240 d-cache-size = <65536>;
241 d-cache-line-size = <64>;
242 d-cache-sets = <256>;
243 next-level-cache = <&l2_cache_b3>;
244 dynamic-power-coefficient = <416>;
245 #cooling-cells = <2>;
248 idle-states {
249 entry-method = "psci";
250 CPU_SLEEP: cpu-sleep {
251 compatible = "arm,idle-state";
252 local-timer-stop;
253 arm,psci-suspend-param = <0x0010000>;
254 entry-latency-us = <100>;
255 exit-latency-us = <120>;
256 min-residency-us = <1000>;
260 l2_cache_l0: l2-cache-l0 {
262 cache-size = <131072>;
263 cache-line-size = <64>;
264 cache-sets = <512>;
265 cache-level = <2>;
266 cache-unified;
267 next-level-cache = <&l3_cache>;
270 l2_cache_l1: l2-cache-l1 {
272 cache-size = <131072>;
273 cache-line-size = <64>;
274 cache-sets = <512>;
275 cache-level = <2>;
276 cache-unified;
277 next-level-cache = <&l3_cache>;
280 l2_cache_l2: l2-cache-l2 {
282 cache-size = <131072>;
283 cache-line-size = <64>;
284 cache-sets = <512>;
285 cache-level = <2>;
286 cache-unified;
287 next-level-cache = <&l3_cache>;
290 l2_cache_l3: l2-cache-l3 {
292 cache-size = <131072>;
293 cache-line-size = <64>;
294 cache-sets = <512>;
295 cache-level = <2>;
296 cache-unified;
297 next-level-cache = <&l3_cache>;
300 l2_cache_b0: l2-cache-b0 {
302 cache-size = <524288>;
303 cache-line-size = <64>;
304 cache-sets = <1024>;
305 cache-level = <2>;
306 cache-unified;
307 next-level-cache = <&l3_cache>;
310 l2_cache_b1: l2-cache-b1 {
312 cache-size = <524288>;
313 cache-line-size = <64>;
314 cache-sets = <1024>;
315 cache-level = <2>;
316 cache-unified;
317 next-level-cache = <&l3_cache>;
320 l2_cache_b2: l2-cache-b2 {
322 cache-size = <524288>;
323 cache-line-size = <64>;
324 cache-sets = <1024>;
325 cache-level = <2>;
326 cache-unified;
327 next-level-cache = <&l3_cache>;
330 l2_cache_b3: l2-cache-b3 {
332 cache-size = <524288>;
333 cache-line-size = <64>;
334 cache-sets = <1024>;
335 cache-level = <2>;
336 cache-unified;
337 next-level-cache = <&l3_cache>;
340 l3_cache: l3-cache {
342 cache-size = <3145728>;
343 cache-line-size = <64>;
344 cache-sets = <4096>;
345 cache-level = <3>;
346 cache-unified;
352 compatible = "linaro,optee-tz";
357 compatible = "arm,scmi-smc";
358 arm,smc-id = <0x82000010>;
360 #address-cells = <1>;
361 #size-cells = <0>;
365 #clock-cells = <1>;
370 #reset-cells = <1>;
375 pmu-a55 {
376 compatible = "arm,cortex-a55-pmu";
380 pmu-a76 {
381 compatible = "arm,cortex-a76-pmu";
386 compatible = "arm,psci-1.0";
390 spll: clock-0 {
391 compatible = "fixed-clock";
392 clock-frequency = <702000000>;
393 clock-output-names = "spll";
394 #clock-cells = <0>;
397 display_subsystem: display-subsystem {
398 compatible = "rockchip,display-subsystem";
403 compatible = "arm,armv8-timer";
409 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
412 xin24m: clock-1 {
413 compatible = "fixed-clock";
414 clock-frequency = <24000000>;
415 clock-output-names = "xin24m";
416 #clock-cells = <0>;
419 xin32k: clock-2 {
420 compatible = "fixed-clock";
421 clock-frequency = <32768>;
422 clock-output-names = "xin32k";
423 #clock-cells = <0>;
427 compatible = "mmio-sram";
430 #address-cells = <1>;
431 #size-cells = <1>;
434 compatible = "arm,scmi-shmem";
440 compatible = "rockchip,rk3588-ehci", "generic-ehci";
443 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>;
445 phy-names = "usb";
446 power-domains = <&power RK3588_PD_USB>;
451 compatible = "rockchip,rk3588-ohci", "generic-ohci";
454 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>;
456 phy-names = "usb";
457 power-domains = <&power RK3588_PD_USB>;
462 compatible = "rockchip,rk3588-ehci", "generic-ehci";
465 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>;
467 phy-names = "usb";
468 power-domains = <&power RK3588_PD_USB>;
473 compatible = "rockchip,rk3588-ohci", "generic-ohci";
476 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>;
478 phy-names = "usb";
479 power-domains = <&power RK3588_PD_USB>;
484 compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
487 clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>,
488 <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>,
489 <&cru CLK_PIPEPHY2_PIPE_U3_G>;
490 clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi", "pipe";
493 phy-names = "usb3-phy";
495 resets = <&cru SRST_A_USB3OTG2>;
497 snps,dis-u2-freeclk-exists-quirk;
498 snps,dis-del-phy-power-chg-quirk;
499 snps,dis-tx-ipgap-linecheck-quirk;
505 compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd";
510 compatible = "rockchip,rk3588-sys-grf", "syscon";
515 compatible = "rockchip,rk3588-vop-grf", "syscon";
520 compatible = "rockchip,rk3588-vo-grf", "syscon";
525 compatible = "rockchip,rk3588-php-grf", "syscon";
530 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
535 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
540 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
542 #address-cells = <1>;
543 #size-cells = <1>;
545 u2phy2: usb2-phy@8000 {
546 compatible = "rockchip,rk3588-usb2phy";
549 resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
550 reset-names = "phy", "apb";
551 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
552 clock-names = "phyclk";
553 clock-output-names = "usb480m_phy2";
554 #clock-cells = <0>;
557 u2phy2_host: host-port {
558 #phy-cells = <0>;
565 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
567 #address-cells = <1>;
568 #size-cells = <1>;
570 u2phy3: usb2-phy@c000 {
571 compatible = "rockchip,rk3588-usb2phy";
574 resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;
575 reset-names = "phy", "apb";
576 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
577 clock-names = "phyclk";
578 clock-output-names = "usb480m_phy3";
579 #clock-cells = <0>;
582 u2phy3_host: host-port {
583 #phy-cells = <0>;
590 compatible = "rockchip,rk3588-ioc", "syscon";
595 compatible = "mmio-sram";
598 #address-cells = <1>;
599 #size-cells = <1>;
602 cru: clock-controller@fd7c0000 {
603 compatible = "rockchip,rk3588-cru";
605 assigned-clocks =
606 <&cru PLL_PPLL>, <&cru PLL_AUPLL>,
607 <&cru PLL_NPLL>, <&cru PLL_GPLL>,
608 <&cru ACLK_CENTER_ROOT>,
609 <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>,
610 <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>,
611 <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>,
612 <&cru HCLK_PMU_CM0_ROOT>, <&cru ACLK_VOP>,
613 <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>,
614 <&cru CLK_GPU>;
615 assigned-clock-rates =
626 #clock-cells = <1>;
627 #reset-cells = <1>;
631 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
634 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>;
635 clock-names = "i2c", "pclk";
636 pinctrl-0 = <&i2c0m0_xfer>;
637 pinctrl-names = "default";
638 #address-cells = <1>;
639 #size-cells = <0>;
644 compatible = "rockchip,rk3588-vop";
646 reg-names = "vop", "gamma-lut";
648 clocks = <&cru ACLK_VOP>,
649 <&cru HCLK_VOP>,
650 <&cru DCLK_VOP0>,
651 <&cru DCLK_VOP1>,
652 <&cru DCLK_VOP2>,
653 <&cru DCLK_VOP3>,
654 <&cru PCLK_VOP_ROOT>;
655 clock-names = "aclk",
663 power-domains = <&power RK3588_PD_VOP>;
665 rockchip,vop-grf = <&vop_grf>;
666 rockchip,vo1-grf = <&vo1_grf>;
671 #address-cells = <1>;
672 #size-cells = <0>;
675 #address-cells = <1>;
676 #size-cells = <0>;
681 #address-cells = <1>;
682 #size-cells = <0>;
687 #address-cells = <1>;
688 #size-cells = <0>;
693 #address-cells = <1>;
694 #size-cells = <0>;
701 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
704 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
705 clock-names = "aclk", "iface";
706 #iommu-cells = <0>;
707 power-domains = <&power RK3588_PD_VOP>;
712 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
715 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
716 clock-names = "baudclk", "apb_pclk";
718 dma-names = "tx", "rx";
719 pinctrl-0 = <&uart0m1_xfer>;
720 pinctrl-names = "default";
721 reg-shift = <2>;
722 reg-io-width = <4>;
727 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
729 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
730 clock-names = "pwm", "pclk";
731 pinctrl-0 = <&pwm0m0_pins>;
732 pinctrl-names = "default";
733 #pwm-cells = <3>;
738 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
740 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
741 clock-names = "pwm", "pclk";
742 pinctrl-0 = <&pwm1m0_pins>;
743 pinctrl-names = "default";
744 #pwm-cells = <3>;
749 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
751 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
752 clock-names = "pwm", "pclk";
753 pinctrl-0 = <&pwm2m0_pins>;
754 pinctrl-names = "default";
755 #pwm-cells = <3>;
760 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
762 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
763 clock-names = "pwm", "pclk";
764 pinctrl-0 = <&pwm3m0_pins>;
765 pinctrl-names = "default";
766 #pwm-cells = <3>;
770 pmu: power-management@fd8d8000 {
771 compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd";
774 power: power-controller {
775 compatible = "rockchip,rk3588-power-controller";
776 #address-cells = <1>;
777 #power-domain-cells = <1>;
778 #size-cells = <0>;
782 power-domain@RK3588_PD_NPU {
784 #power-domain-cells = <0>;
785 #address-cells = <1>;
786 #size-cells = <0>;
788 power-domain@RK3588_PD_NPUTOP {
790 clocks = <&cru HCLK_NPU_ROOT>,
791 <&cru PCLK_NPU_ROOT>,
792 <&cru CLK_NPU_DSU0>,
793 <&cru HCLK_NPU_CM0_ROOT>;
797 #power-domain-cells = <0>;
798 #address-cells = <1>;
799 #size-cells = <0>;
801 power-domain@RK3588_PD_NPU1 {
803 clocks = <&cru HCLK_NPU_ROOT>,
804 <&cru PCLK_NPU_ROOT>,
805 <&cru CLK_NPU_DSU0>;
807 #power-domain-cells = <0>;
809 power-domain@RK3588_PD_NPU2 {
811 clocks = <&cru HCLK_NPU_ROOT>,
812 <&cru PCLK_NPU_ROOT>,
813 <&cru CLK_NPU_DSU0>;
815 #power-domain-cells = <0>;
820 power-domain@RK3588_PD_GPU {
822 clocks = <&cru CLK_GPU>,
823 <&cru CLK_GPU_COREGROUP>,
824 <&cru CLK_GPU_STACKS>;
829 #power-domain-cells = <0>;
832 power-domain@RK3588_PD_VCODEC {
834 #address-cells = <1>;
835 #size-cells = <0>;
836 #power-domain-cells = <0>;
838 power-domain@RK3588_PD_RKVDEC0 {
840 clocks = <&cru HCLK_RKVDEC0>,
841 <&cru HCLK_VDPU_ROOT>,
842 <&cru ACLK_VDPU_ROOT>,
843 <&cru ACLK_RKVDEC0>,
844 <&cru ACLK_RKVDEC_CCU>;
846 #power-domain-cells = <0>;
848 power-domain@RK3588_PD_RKVDEC1 {
850 clocks = <&cru HCLK_RKVDEC1>,
851 <&cru HCLK_VDPU_ROOT>,
852 <&cru ACLK_VDPU_ROOT>,
853 <&cru ACLK_RKVDEC1>;
855 #power-domain-cells = <0>;
857 power-domain@RK3588_PD_VENC0 {
859 clocks = <&cru HCLK_RKVENC0>,
860 <&cru ACLK_RKVENC0>;
864 #address-cells = <1>;
865 #size-cells = <0>;
866 #power-domain-cells = <0>;
868 power-domain@RK3588_PD_VENC1 {
870 clocks = <&cru HCLK_RKVENC1>,
871 <&cru HCLK_RKVENC0>,
872 <&cru ACLK_RKVENC0>,
873 <&cru ACLK_RKVENC1>;
877 #power-domain-cells = <0>;
882 power-domain@RK3588_PD_VDPU {
884 clocks = <&cru HCLK_VDPU_ROOT>,
885 <&cru ACLK_VDPU_LOW_ROOT>,
886 <&cru ACLK_VDPU_ROOT>,
887 <&cru ACLK_JPEG_DECODER_ROOT>,
888 <&cru ACLK_IEP2P0>,
889 <&cru HCLK_IEP2P0>,
890 <&cru ACLK_JPEG_ENCODER0>,
891 <&cru HCLK_JPEG_ENCODER0>,
892 <&cru ACLK_JPEG_ENCODER1>,
893 <&cru HCLK_JPEG_ENCODER1>,
894 <&cru ACLK_JPEG_ENCODER2>,
895 <&cru HCLK_JPEG_ENCODER2>,
896 <&cru ACLK_JPEG_ENCODER3>,
897 <&cru HCLK_JPEG_ENCODER3>,
898 <&cru ACLK_JPEG_DECODER>,
899 <&cru HCLK_JPEG_DECODER>,
900 <&cru ACLK_RGA2>,
901 <&cru HCLK_RGA2>;
910 #address-cells = <1>;
911 #size-cells = <0>;
912 #power-domain-cells = <0>;
915 power-domain@RK3588_PD_AV1 {
917 clocks = <&cru PCLK_AV1>,
918 <&cru ACLK_AV1>,
919 <&cru HCLK_VDPU_ROOT>;
921 #power-domain-cells = <0>;
923 power-domain@RK3588_PD_RKVDEC0 {
925 clocks = <&cru HCLK_RKVDEC0>,
926 <&cru HCLK_VDPU_ROOT>,
927 <&cru ACLK_VDPU_ROOT>,
928 <&cru ACLK_RKVDEC0>;
930 #power-domain-cells = <0>;
932 power-domain@RK3588_PD_RKVDEC1 {
934 clocks = <&cru HCLK_RKVDEC1>,
935 <&cru HCLK_VDPU_ROOT>,
936 <&cru ACLK_VDPU_ROOT>;
938 #power-domain-cells = <0>;
940 power-domain@RK3588_PD_RGA30 {
942 clocks = <&cru ACLK_RGA3_0>,
943 <&cru HCLK_RGA3_0>;
945 #power-domain-cells = <0>;
948 power-domain@RK3588_PD_VOP {
950 clocks = <&cru PCLK_VOP_ROOT>,
951 <&cru HCLK_VOP_ROOT>,
952 <&cru ACLK_VOP>;
955 #address-cells = <1>;
956 #size-cells = <0>;
957 #power-domain-cells = <0>;
959 power-domain@RK3588_PD_VO0 {
961 clocks = <&cru PCLK_VO0_ROOT>,
962 <&cru PCLK_VO0_S_ROOT>,
963 <&cru HCLK_VO0_S_ROOT>,
964 <&cru ACLK_VO0_ROOT>,
965 <&cru HCLK_HDCP0>,
966 <&cru ACLK_HDCP0>,
967 <&cru HCLK_VOP_ROOT>;
969 #power-domain-cells = <0>;
972 power-domain@RK3588_PD_VO1 {
974 clocks = <&cru PCLK_VO1_ROOT>,
975 <&cru PCLK_VO1_S_ROOT>,
976 <&cru HCLK_VO1_S_ROOT>,
977 <&cru HCLK_HDCP1>,
978 <&cru ACLK_HDCP1>,
979 <&cru ACLK_HDMIRX_ROOT>,
980 <&cru HCLK_VO1USB_TOP_ROOT>;
983 #power-domain-cells = <0>;
985 power-domain@RK3588_PD_VI {
987 clocks = <&cru HCLK_VI_ROOT>,
988 <&cru PCLK_VI_ROOT>,
989 <&cru HCLK_ISP0>,
990 <&cru ACLK_ISP0>,
991 <&cru HCLK_VICAP>,
992 <&cru ACLK_VICAP>;
997 #address-cells = <1>;
998 #size-cells = <0>;
999 #power-domain-cells = <0>;
1001 power-domain@RK3588_PD_ISP1 {
1003 clocks = <&cru HCLK_ISP1>,
1004 <&cru ACLK_ISP1>,
1005 <&cru HCLK_VI_ROOT>,
1006 <&cru PCLK_VI_ROOT>;
1009 #power-domain-cells = <0>;
1011 power-domain@RK3588_PD_FEC {
1013 clocks = <&cru HCLK_FISHEYE0>,
1014 <&cru ACLK_FISHEYE0>,
1015 <&cru HCLK_FISHEYE1>,
1016 <&cru ACLK_FISHEYE1>,
1017 <&cru PCLK_VI_ROOT>;
1020 #power-domain-cells = <0>;
1023 power-domain@RK3588_PD_RGA31 {
1025 clocks = <&cru HCLK_RGA3_1>,
1026 <&cru ACLK_RGA3_1>;
1028 #power-domain-cells = <0>;
1030 power-domain@RK3588_PD_USB {
1032 clocks = <&cru PCLK_PHP_ROOT>,
1033 <&cru ACLK_USB_ROOT>,
1034 <&cru ACLK_USB>,
1035 <&cru HCLK_USB_ROOT>,
1036 <&cru HCLK_HOST0>,
1037 <&cru HCLK_HOST_ARB0>,
1038 <&cru HCLK_HOST1>,
1039 <&cru HCLK_HOST_ARB1>;
1044 #power-domain-cells = <0>;
1046 power-domain@RK3588_PD_GMAC {
1048 clocks = <&cru PCLK_PHP_ROOT>,
1049 <&cru ACLK_PCIE_ROOT>,
1050 <&cru ACLK_PHP_ROOT>;
1051 #power-domain-cells = <0>;
1053 power-domain@RK3588_PD_PCIE {
1055 clocks = <&cru PCLK_PHP_ROOT>,
1056 <&cru ACLK_PCIE_ROOT>,
1057 <&cru ACLK_PHP_ROOT>;
1058 #power-domain-cells = <0>;
1060 power-domain@RK3588_PD_SDIO {
1062 clocks = <&cru HCLK_SDIO>,
1063 <&cru HCLK_NVM_ROOT>;
1065 #power-domain-cells = <0>;
1067 power-domain@RK3588_PD_AUDIO {
1069 clocks = <&cru HCLK_AUDIO_ROOT>,
1070 <&cru PCLK_AUDIO_ROOT>;
1071 #power-domain-cells = <0>;
1073 power-domain@RK3588_PD_SDMMC {
1076 #power-domain-cells = <0>;
1082 compatible = "rockchip,rk3588-i2s-tdm";
1085 clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>;
1086 clock-names = "mclk_tx", "mclk_rx", "hclk";
1087 assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>;
1088 assigned-clock-parents = <&cru PLL_AUPLL>;
1090 dma-names = "tx";
1091 power-domains = <&power RK3588_PD_VO0>;
1092 resets = <&cru SRST_M_I2S4_8CH_TX>;
1093 reset-names = "tx-m";
1094 #sound-dai-cells = <0>;
1099 compatible = "rockchip,rk3588-i2s-tdm";
1102 clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>;
1103 clock-names = "mclk_tx", "mclk_rx", "hclk";
1104 assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>;
1105 assigned-clock-parents = <&cru PLL_AUPLL>;
1107 dma-names = "tx";
1108 power-domains = <&power RK3588_PD_VO1>;
1109 resets = <&cru SRST_M_I2S5_8CH_TX>;
1110 reset-names = "tx-m";
1111 #sound-dai-cells = <0>;
1116 compatible = "rockchip,rk3588-i2s-tdm";
1119 clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>;
1120 clock-names = "mclk_tx", "mclk_rx", "hclk";
1121 assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>;
1122 assigned-clock-parents = <&cru PLL_AUPLL>;
1124 dma-names = "rx";
1125 power-domains = <&power RK3588_PD_VO1>;
1126 resets = <&cru SRST_M_I2S9_8CH_RX>;
1127 reset-names = "rx-m";
1128 #sound-dai-cells = <0>;
1133 compatible = "rockchip,rk3588-qos", "syscon";
1138 compatible = "rockchip,rk3588-qos", "syscon";
1143 compatible = "rockchip,rk3588-qos", "syscon";
1148 compatible = "rockchip,rk3588-qos", "syscon";
1153 compatible = "rockchip,rk3588-qos", "syscon";
1158 compatible = "rockchip,rk3588-qos", "syscon";
1163 compatible = "rockchip,rk3588-qos", "syscon";
1168 compatible = "rockchip,rk3588-qos", "syscon";
1173 compatible = "rockchip,rk3588-qos", "syscon";
1178 compatible = "rockchip,rk3588-qos", "syscon";
1183 compatible = "rockchip,rk3588-qos", "syscon";
1188 compatible = "rockchip,rk3588-qos", "syscon";
1193 compatible = "rockchip,rk3588-qos", "syscon";
1198 compatible = "rockchip,rk3588-qos", "syscon";
1203 compatible = "rockchip,rk3588-qos", "syscon";
1208 compatible = "rockchip,rk3588-qos", "syscon";
1213 compatible = "rockchip,rk3588-qos", "syscon";
1218 compatible = "rockchip,rk3588-qos", "syscon";
1223 compatible = "rockchip,rk3588-qos", "syscon";
1228 compatible = "rockchip,rk3588-qos", "syscon";
1233 compatible = "rockchip,rk3588-qos", "syscon";
1238 compatible = "rockchip,rk3588-qos", "syscon";
1243 compatible = "rockchip,rk3588-qos", "syscon";
1248 compatible = "rockchip,rk3588-qos", "syscon";
1253 compatible = "rockchip,rk3588-qos", "syscon";
1258 compatible = "rockchip,rk3588-qos", "syscon";
1263 compatible = "rockchip,rk3588-qos", "syscon";
1268 compatible = "rockchip,rk3588-qos", "syscon";
1273 compatible = "rockchip,rk3588-qos", "syscon";
1278 compatible = "rockchip,rk3588-qos", "syscon";
1283 compatible = "rockchip,rk3588-qos", "syscon";
1288 compatible = "rockchip,rk3588-qos", "syscon";
1293 compatible = "rockchip,rk3588-qos", "syscon";
1298 compatible = "rockchip,rk3588-qos", "syscon";
1303 compatible = "rockchip,rk3588-qos", "syscon";
1308 compatible = "rockchip,rk3588-qos", "syscon";
1313 compatible = "rockchip,rk3588-qos", "syscon";
1318 compatible = "rockchip,rk3588-qos", "syscon";
1323 compatible = "rockchip,rk3588-qos", "syscon";
1328 compatible = "rockchip,rk3588-qos", "syscon";
1333 compatible = "rockchip,rk3588-qos", "syscon";
1338 compatible = "rockchip,rk3588-qos", "syscon";
1343 compatible = "rockchip,rk3588-qos", "syscon";
1348 compatible = "rockchip,rk3588-qos", "syscon";
1353 compatible = "rockchip,rk3588-qos", "syscon";
1358 compatible = "rockchip,rk3588-qos", "syscon";
1363 compatible = "rockchip,rk3588-qos", "syscon";
1368 compatible = "rockchip,rk3588-qos", "syscon";
1373 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
1374 bus-range = <0x30 0x3f>;
1375 clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>,
1376 <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>,
1377 <&cru CLK_PCIE_AUX3>, <&cru CLK_PCIE1L1_PIPE>;
1378 clock-names = "aclk_mst", "aclk_slv",
1387 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
1388 #interrupt-cells = <1>;
1389 interrupt-map-mask = <0 0 0 7>;
1390 interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>,
1394 linux,pci-domain = <3>;
1395 max-link-speed = <2>;
1396 msi-map = <0x3000 &its0 0x3000 0x1000>;
1397 num-lanes = <1>;
1399 phy-names = "pcie-phy";
1400 power-domains = <&power RK3588_PD_PCIE>;
1407 reg-names = "dbi", "apb", "config";
1408 resets = <&cru SRST_PCIE3_POWER_UP>, <&cru SRST_P_PCIE3>;
1409 reset-names = "pwr", "pipe";
1410 #address-cells = <3>;
1411 #size-cells = <2>;
1414 pcie2x1l1_intc: legacy-interrupt-controller {
1415 interrupt-controller;
1416 #address-cells = <0>;
1417 #interrupt-cells = <1>;
1418 interrupt-parent = <&gic>;
1424 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
1425 bus-range = <0x40 0x4f>;
1426 clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>,
1427 <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>,
1428 <&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>;
1429 clock-names = "aclk_mst", "aclk_slv",
1438 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
1439 #interrupt-cells = <1>;
1440 interrupt-map-mask = <0 0 0 7>;
1441 interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>,
1445 linux,pci-domain = <4>;
1446 max-link-speed = <2>;
1447 msi-map = <0x4000 &its0 0x4000 0x1000>;
1448 num-lanes = <1>;
1450 phy-names = "pcie-phy";
1451 power-domains = <&power RK3588_PD_PCIE>;
1458 reg-names = "dbi", "apb", "config";
1459 resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>;
1460 reset-names = "pwr", "pipe";
1461 #address-cells = <3>;
1462 #size-cells = <2>;
1465 pcie2x1l2_intc: legacy-interrupt-controller {
1466 interrupt-controller;
1467 #address-cells = <0>;
1468 #interrupt-cells = <1>;
1469 interrupt-parent = <&gic>;
1476 compatible = "rockchip,rk3588-dfi";
1485 compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
1489 interrupt-names = "macirq", "eth_wake_irq";
1490 clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>,
1491 <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>,
1492 <&cru CLK_GMAC1_PTP_REF>;
1493 clock-names = "stmmaceth", "clk_mac_ref",
1496 power-domains = <&power RK3588_PD_GMAC>;
1497 resets = <&cru SRST_A_GMAC1>;
1498 reset-names = "stmmaceth";
1500 rockchip,php-grf = <&php_grf>;
1501 snps,axi-config = <&gmac1_stmmac_axi_setup>;
1502 snps,mixed-burst;
1503 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
1504 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
1509 compatible = "snps,dwmac-mdio";
1510 #address-cells = <0x1>;
1511 #size-cells = <0x0>;
1514 gmac1_stmmac_axi_setup: stmmac-axi-config {
1520 gmac1_mtl_rx_setup: rx-queues-config {
1521 snps,rx-queues-to-use = <2>;
1526 gmac1_mtl_tx_setup: tx-queues-config {
1527 snps,tx-queues-to-use = <2>;
1534 compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
1537 clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>,
1538 <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>,
1539 <&cru CLK_PIPEPHY0_PIPE_ASIC_G>;
1540 clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
1541 ports-implemented = <0x1>;
1542 #address-cells = <1>;
1543 #size-cells = <0>;
1546 sata-port@0 {
1548 hba-port-cap = <HBA_PORT_FBSCP>;
1550 phy-names = "sata-phy";
1551 snps,rx-ts-max = <32>;
1552 snps,tx-ts-max = <32>;
1557 compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
1560 clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>,
1561 <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>,
1562 <&cru CLK_PIPEPHY2_PIPE_ASIC_G>;
1563 clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
1564 ports-implemented = <0x1>;
1565 #address-cells = <1>;
1566 #size-cells = <0>;
1569 sata-port@0 {
1571 hba-port-cap = <HBA_PORT_FBSCP>;
1573 phy-names = "sata-phy";
1574 snps,rx-ts-max = <32>;
1575 snps,tx-ts-max = <32>;
1583 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
1584 clock-names = "clk_sfc", "hclk_sfc";
1585 #address-cells = <1>;
1586 #size-cells = <0>;
1591 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
1595 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
1596 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1597 fifo-depth = <0x100>;
1598 max-frequency = <200000000>;
1599 pinctrl-names = "default";
1600 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
1601 power-domains = <&power RK3588_PD_SDMMC>;
1606 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
1609 clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>,
1610 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
1611 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1612 fifo-depth = <0x100>;
1613 max-frequency = <200000000>;
1614 pinctrl-names = "default";
1615 pinctrl-0 = <&sdiom1_pins>;
1616 power-domains = <&power RK3588_PD_SDIO>;
1621 compatible = "rockchip,rk3588-dwcmshc";
1624 assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>, <&cru CCLK_EMMC>;
1625 assigned-clock-rates = <200000000>, <24000000>, <200000000>;
1626 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
1627 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
1628 <&cru TMCLK_EMMC>;
1629 clock-names = "core", "bus", "axi", "block", "timer";
1630 max-frequency = <200000000>;
1631 pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>,
1633 pinctrl-names = "default";
1634 resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>,
1635 <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>,
1636 <&cru SRST_T_EMMC>;
1637 reset-names = "core", "bus", "axi", "block", "timer";
1642 compatible = "rockchip,rk3588-i2s-tdm";
1645 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>;
1646 clock-names = "mclk_tx", "mclk_rx", "hclk";
1647 assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>;
1648 assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>;
1650 dma-names = "tx", "rx";
1651 power-domains = <&power RK3588_PD_AUDIO>;
1652 resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>;
1653 reset-names = "tx-m", "rx-m";
1654 rockchip,trcm-sync-tx-only;
1655 pinctrl-names = "default";
1656 pinctrl-0 = <&i2s0_lrck
1666 #sound-dai-cells = <0>;
1671 compatible = "rockchip,rk3588-i2s-tdm";
1674 clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>;
1675 clock-names = "mclk_tx", "mclk_rx", "hclk";
1677 dma-names = "tx", "rx";
1678 resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>;
1679 reset-names = "tx-m", "rx-m";
1680 rockchip,trcm-sync-tx-only;
1681 pinctrl-names = "default";
1682 pinctrl-0 = <&i2s1m0_lrck
1692 #sound-dai-cells = <0>;
1697 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
1700 clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>;
1701 clock-names = "i2s_clk", "i2s_hclk";
1702 assigned-clocks = <&cru CLK_I2S2_2CH_SRC>;
1703 assigned-clock-parents = <&cru PLL_AUPLL>;
1705 dma-names = "tx", "rx";
1706 power-domains = <&power RK3588_PD_AUDIO>;
1707 rockchip,trcm-sync-tx-only;
1708 pinctrl-names = "default";
1709 pinctrl-0 = <&i2s2m1_lrck
1713 #sound-dai-cells = <0>;
1718 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
1721 clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>;
1722 clock-names = "i2s_clk", "i2s_hclk";
1723 assigned-clocks = <&cru CLK_I2S3_2CH_SRC>;
1724 assigned-clock-parents = <&cru PLL_AUPLL>;
1726 dma-names = "tx", "rx";
1727 power-domains = <&power RK3588_PD_AUDIO>;
1728 rockchip,trcm-sync-tx-only;
1729 pinctrl-names = "default";
1730 pinctrl-0 = <&i2s3_lrck
1734 #sound-dai-cells = <0>;
1738 gic: interrupt-controller@fe600000 {
1739 compatible = "arm,gic-v3";
1743 interrupt-controller;
1744 mbi-alias = <0x0 0xfe610000>;
1745 mbi-ranges = <424 56>;
1746 msi-controller;
1748 #address-cells = <2>;
1749 #interrupt-cells = <4>;
1750 #size-cells = <2>;
1752 its0: msi-controller@fe640000 {
1753 compatible = "arm,gic-v3-its";
1755 msi-controller;
1756 #msi-cells = <1>;
1759 its1: msi-controller@fe660000 {
1760 compatible = "arm,gic-v3-its";
1762 msi-controller;
1763 #msi-cells = <1>;
1766 ppi-partitions {
1767 ppi_partition0: interrupt-partition-0 {
1771 ppi_partition1: interrupt-partition-1 {
1777 dmac0: dma-controller@fea10000 {
1782 arm,pl330-periph-burst;
1783 clocks = <&cru ACLK_DMAC0>;
1784 clock-names = "apb_pclk";
1785 #dma-cells = <1>;
1788 dmac1: dma-controller@fea30000 {
1793 arm,pl330-periph-burst;
1794 clocks = <&cru ACLK_DMAC1>;
1795 clock-names = "apb_pclk";
1796 #dma-cells = <1>;
1800 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
1802 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
1803 clock-names = "i2c", "pclk";
1805 pinctrl-0 = <&i2c1m0_xfer>;
1806 pinctrl-names = "default";
1807 #address-cells = <1>;
1808 #size-cells = <0>;
1813 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
1815 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
1816 clock-names = "i2c", "pclk";
1818 pinctrl-0 = <&i2c2m0_xfer>;
1819 pinctrl-names = "default";
1820 #address-cells = <1>;
1821 #size-cells = <0>;
1826 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
1828 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
1829 clock-names = "i2c", "pclk";
1831 pinctrl-0 = <&i2c3m0_xfer>;
1832 pinctrl-names = "default";
1833 #address-cells = <1>;
1834 #size-cells = <0>;
1839 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
1841 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
1842 clock-names = "i2c", "pclk";
1844 pinctrl-0 = <&i2c4m0_xfer>;
1845 pinctrl-names = "default";
1846 #address-cells = <1>;
1847 #size-cells = <0>;
1852 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
1854 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
1855 clock-names = "i2c", "pclk";
1857 pinctrl-0 = <&i2c5m0_xfer>;
1858 pinctrl-names = "default";
1859 #address-cells = <1>;
1860 #size-cells = <0>;
1865 compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer";
1868 clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>;
1869 clock-names = "pclk", "timer";
1873 compatible = "rockchip,rk3588-wdt", "snps,dw-wdt";
1875 clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>;
1876 clock-names = "tclk", "pclk";
1881 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
1884 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
1885 clock-names = "spiclk", "apb_pclk";
1887 dma-names = "tx", "rx";
1888 num-cs = <2>;
1889 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
1890 pinctrl-names = "default";
1891 #address-cells = <1>;
1892 #size-cells = <0>;
1897 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
1900 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
1901 clock-names = "spiclk", "apb_pclk";
1903 dma-names = "tx", "rx";
1904 num-cs = <2>;
1905 pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>;
1906 pinctrl-names = "default";
1907 #address-cells = <1>;
1908 #size-cells = <0>;
1913 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
1916 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>;
1917 clock-names = "spiclk", "apb_pclk";
1919 dma-names = "tx", "rx";
1920 num-cs = <2>;
1921 pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>;
1922 pinctrl-names = "default";
1923 #address-cells = <1>;
1924 #size-cells = <0>;
1929 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
1932 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>;
1933 clock-names = "spiclk", "apb_pclk";
1935 dma-names = "tx", "rx";
1936 num-cs = <2>;
1937 pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>;
1938 pinctrl-names = "default";
1939 #address-cells = <1>;
1940 #size-cells = <0>;
1945 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1948 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
1949 clock-names = "baudclk", "apb_pclk";
1951 dma-names = "tx", "rx";
1952 pinctrl-0 = <&uart1m1_xfer>;
1953 pinctrl-names = "default";
1954 reg-io-width = <4>;
1955 reg-shift = <2>;
1960 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1963 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
1964 clock-names = "baudclk", "apb_pclk";
1966 dma-names = "tx", "rx";
1967 pinctrl-0 = <&uart2m1_xfer>;
1968 pinctrl-names = "default";
1969 reg-io-width = <4>;
1970 reg-shift = <2>;
1975 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1978 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
1979 clock-names = "baudclk", "apb_pclk";
1981 dma-names = "tx", "rx";
1982 pinctrl-0 = <&uart3m1_xfer>;
1983 pinctrl-names = "default";
1984 reg-io-width = <4>;
1985 reg-shift = <2>;
1990 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1993 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
1994 clock-names = "baudclk", "apb_pclk";
1996 dma-names = "tx", "rx";
1997 pinctrl-0 = <&uart4m1_xfer>;
1998 pinctrl-names = "default";
1999 reg-io-width = <4>;
2000 reg-shift = <2>;
2005 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
2008 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
2009 clock-names = "baudclk", "apb_pclk";
2011 dma-names = "tx", "rx";
2012 pinctrl-0 = <&uart5m1_xfer>;
2013 pinctrl-names = "default";
2014 reg-io-width = <4>;
2015 reg-shift = <2>;
2020 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
2023 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
2024 clock-names = "baudclk", "apb_pclk";
2026 dma-names = "tx", "rx";
2027 pinctrl-0 = <&uart6m1_xfer>;
2028 pinctrl-names = "default";
2029 reg-io-width = <4>;
2030 reg-shift = <2>;
2035 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
2038 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
2039 clock-names = "baudclk", "apb_pclk";
2041 dma-names = "tx", "rx";
2042 pinctrl-0 = <&uart7m1_xfer>;
2043 pinctrl-names = "default";
2044 reg-io-width = <4>;
2045 reg-shift = <2>;
2050 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
2053 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
2054 clock-names = "baudclk", "apb_pclk";
2056 dma-names = "tx", "rx";
2057 pinctrl-0 = <&uart8m1_xfer>;
2058 pinctrl-names = "default";
2059 reg-io-width = <4>;
2060 reg-shift = <2>;
2065 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
2068 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
2069 clock-names = "baudclk", "apb_pclk";
2071 dma-names = "tx", "rx";
2072 pinctrl-0 = <&uart9m1_xfer>;
2073 pinctrl-names = "default";
2074 reg-io-width = <4>;
2075 reg-shift = <2>;
2080 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2082 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
2083 clock-names = "pwm", "pclk";
2084 pinctrl-0 = <&pwm4m0_pins>;
2085 pinctrl-names = "default";
2086 #pwm-cells = <3>;
2091 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2093 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
2094 clock-names = "pwm", "pclk";
2095 pinctrl-0 = <&pwm5m0_pins>;
2096 pinctrl-names = "default";
2097 #pwm-cells = <3>;
2102 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2104 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
2105 clock-names = "pwm", "pclk";
2106 pinctrl-0 = <&pwm6m0_pins>;
2107 pinctrl-names = "default";
2108 #pwm-cells = <3>;
2113 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2115 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
2116 clock-names = "pwm", "pclk";
2117 pinctrl-0 = <&pwm7m0_pins>;
2118 pinctrl-names = "default";
2119 #pwm-cells = <3>;
2124 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2126 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
2127 clock-names = "pwm", "pclk";
2128 pinctrl-0 = <&pwm8m0_pins>;
2129 pinctrl-names = "default";
2130 #pwm-cells = <3>;
2135 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2137 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
2138 clock-names = "pwm", "pclk";
2139 pinctrl-0 = <&pwm9m0_pins>;
2140 pinctrl-names = "default";
2141 #pwm-cells = <3>;
2146 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2148 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
2149 clock-names = "pwm", "pclk";
2150 pinctrl-0 = <&pwm10m0_pins>;
2151 pinctrl-names = "default";
2152 #pwm-cells = <3>;
2157 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2159 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
2160 clock-names = "pwm", "pclk";
2161 pinctrl-0 = <&pwm11m0_pins>;
2162 pinctrl-names = "default";
2163 #pwm-cells = <3>;
2168 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2170 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
2171 clock-names = "pwm", "pclk";
2172 pinctrl-0 = <&pwm12m0_pins>;
2173 pinctrl-names = "default";
2174 #pwm-cells = <3>;
2179 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2181 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
2182 clock-names = "pwm", "pclk";
2183 pinctrl-0 = <&pwm13m0_pins>;
2184 pinctrl-names = "default";
2185 #pwm-cells = <3>;
2190 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2192 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
2193 clock-names = "pwm", "pclk";
2194 pinctrl-0 = <&pwm14m0_pins>;
2195 pinctrl-names = "default";
2196 #pwm-cells = <3>;
2201 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2203 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
2204 clock-names = "pwm", "pclk";
2205 pinctrl-0 = <&pwm15m0_pins>;
2206 pinctrl-names = "default";
2207 #pwm-cells = <3>;
2212 compatible = "rockchip,rk3588-tsadc";
2215 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
2216 clock-names = "tsadc", "apb_pclk";
2217 assigned-clocks = <&cru CLK_TSADC>;
2218 assigned-clock-rates = <2000000>;
2219 resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>;
2220 reset-names = "tsadc-apb", "tsadc";
2221 rockchip,hw-tshut-temp = <120000>;
2222 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
2223 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
2224 pinctrl-0 = <&tsadc_gpio_func>;
2225 pinctrl-1 = <&tsadc_shut>;
2226 pinctrl-names = "gpio", "otpout";
2227 #thermal-sensor-cells = <1>;
2232 compatible = "rockchip,rk3588-saradc";
2235 #io-channel-cells = <1>;
2236 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
2237 clock-names = "saradc", "apb_pclk";
2238 resets = <&cru SRST_P_SARADC>;
2239 reset-names = "saradc-apb";
2244 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2246 clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>;
2247 clock-names = "i2c", "pclk";
2249 pinctrl-0 = <&i2c6m0_xfer>;
2250 pinctrl-names = "default";
2251 #address-cells = <1>;
2252 #size-cells = <0>;
2257 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2259 clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>;
2260 clock-names = "i2c", "pclk";
2262 pinctrl-0 = <&i2c7m0_xfer>;
2263 pinctrl-names = "default";
2264 #address-cells = <1>;
2265 #size-cells = <0>;
2270 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2272 clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>;
2273 clock-names = "i2c", "pclk";
2275 pinctrl-0 = <&i2c8m0_xfer>;
2276 pinctrl-names = "default";
2277 #address-cells = <1>;
2278 #size-cells = <0>;
2283 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
2286 clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>;
2287 clock-names = "spiclk", "apb_pclk";
2289 dma-names = "tx", "rx";
2290 num-cs = <2>;
2291 pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>;
2292 pinctrl-names = "default";
2293 #address-cells = <1>;
2294 #size-cells = <0>;
2299 compatible = "rockchip,rk3588-otp";
2301 clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>,
2302 <&cru CLK_OTP_PHY_G>, <&cru CLK_OTPC_ARB>;
2303 clock-names = "otp", "apb_pclk", "phy", "arb";
2304 resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>,
2305 <&cru SRST_OTPC_ARB>;
2306 reset-names = "otp", "apb", "arb";
2307 #address-cells = <1>;
2308 #size-cells = <1>;
2310 cpu_code: cpu-code@2 {
2318 cpub0_leakage: cpu-leakage@17 {
2322 cpub1_leakage: cpu-leakage@18 {
2326 cpul_leakage: cpu-leakage@19 {
2330 log_leakage: log-leakage@1a {
2334 gpu_leakage: gpu-leakage@1b {
2338 otp_cpu_version: cpu-version@1c {
2343 npu_leakage: npu-leakage@28 {
2347 codec_leakage: codec-leakage@29 {
2352 dmac2: dma-controller@fed10000 {
2357 arm,pl330-periph-burst;
2358 clocks = <&cru ACLK_DMAC2>;
2359 clock-names = "apb_pclk";
2360 #dma-cells = <1>;
2364 compatible = "rockchip,rk3588-naneng-combphy";
2366 clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>,
2367 <&cru PCLK_PHP_ROOT>;
2368 clock-names = "ref", "apb", "pipe";
2369 assigned-clocks = <&cru CLK_REF_PIPE_PHY0>;
2370 assigned-clock-rates = <100000000>;
2371 #phy-cells = <1>;
2372 resets = <&cru SRST_REF_PIPE_PHY0>, <&cru SRST_P_PCIE2_PHY0>;
2373 reset-names = "phy", "apb";
2374 rockchip,pipe-grf = <&php_grf>;
2375 rockchip,pipe-phy-grf = <&pipe_phy0_grf>;
2380 compatible = "rockchip,rk3588-naneng-combphy";
2382 clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>,
2383 <&cru PCLK_PHP_ROOT>;
2384 clock-names = "ref", "apb", "pipe";
2385 assigned-clocks = <&cru CLK_REF_PIPE_PHY2>;
2386 assigned-clock-rates = <100000000>;
2387 #phy-cells = <1>;
2388 resets = <&cru SRST_REF_PIPE_PHY2>, <&cru SRST_P_PCIE2_PHY2>;
2389 reset-names = "phy", "apb";
2390 rockchip,pipe-grf = <&php_grf>;
2391 rockchip,pipe-phy-grf = <&pipe_phy2_grf>;
2396 compatible = "mmio-sram";
2399 #address-cells = <1>;
2400 #size-cells = <1>;
2404 compatible = "rockchip,rk3588-pinctrl";
2407 #address-cells = <2>;
2408 #size-cells = <2>;
2411 compatible = "rockchip,gpio-bank";
2414 clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
2415 gpio-controller;
2416 gpio-ranges = <&pinctrl 0 0 32>;
2417 interrupt-controller;
2418 #gpio-cells = <2>;
2419 #interrupt-cells = <2>;
2423 compatible = "rockchip,gpio-bank";
2426 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
2427 gpio-controller;
2428 gpio-ranges = <&pinctrl 0 32 32>;
2429 interrupt-controller;
2430 #gpio-cells = <2>;
2431 #interrupt-cells = <2>;
2435 compatible = "rockchip,gpio-bank";
2438 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
2439 gpio-controller;
2440 gpio-ranges = <&pinctrl 0 64 32>;
2441 interrupt-controller;
2442 #gpio-cells = <2>;
2443 #interrupt-cells = <2>;
2447 compatible = "rockchip,gpio-bank";
2450 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
2451 gpio-controller;
2452 gpio-ranges = <&pinctrl 0 96 32>;
2453 interrupt-controller;
2454 #gpio-cells = <2>;
2455 #interrupt-cells = <2>;
2459 compatible = "rockchip,gpio-bank";
2462 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
2463 gpio-controller;
2464 gpio-ranges = <&pinctrl 0 128 32>;
2465 interrupt-controller;
2466 #gpio-cells = <2>;
2467 #interrupt-cells = <2>;
2471 av1d: video-codec@fdc70000 {
2472 compatible = "rockchip,rk3588-av1-vpu";
2475 interrupt-names = "vdpu";
2476 assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
2477 assigned-clock-rates = <400000000>, <400000000>;
2478 clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
2479 clock-names = "aclk", "hclk";
2480 power-domains = <&power RK3588_PD_AV1>;
2481 resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>;
2485 #include "rk3588s-pinctrl.dtsi"