Lines Matching +full:i2s +full:- +full:rx
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "rk3588-pinctrl.dtsi"
11 compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
16 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
20 i2s8_8ch: i2s@fddc8000 {
21 compatible = "rockchip,rk3588-i2s-tdm";
25 clock-names = "mclk_tx", "mclk_rx", "hclk";
26 assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>;
27 assigned-clock-parents = <&cru PLL_AUPLL>;
29 dma-names = "tx";
30 power-domains = <&power RK3588_PD_VO0>;
32 reset-names = "tx-m";
33 #sound-dai-cells = <0>;
37 i2s6_8ch: i2s@fddf4000 {
38 compatible = "rockchip,rk3588-i2s-tdm";
42 clock-names = "mclk_tx", "mclk_rx", "hclk";
43 assigned-clocks = <&cru CLK_I2S6_8CH_TX_SRC>;
44 assigned-clock-parents = <&cru PLL_AUPLL>;
46 dma-names = "tx";
47 power-domains = <&power RK3588_PD_VO1>;
49 reset-names = "tx-m";
50 #sound-dai-cells = <0>;
54 i2s7_8ch: i2s@fddf8000 {
55 compatible = "rockchip,rk3588-i2s-tdm";
59 clock-names = "mclk_tx", "mclk_rx", "hclk";
60 assigned-clocks = <&cru CLK_I2S7_8CH_RX_SRC>;
61 assigned-clock-parents = <&cru PLL_AUPLL>;
63 dma-names = "rx";
64 power-domains = <&power RK3588_PD_VO1>;
66 reset-names = "rx-m";
67 #sound-dai-cells = <0>;
71 i2s10_8ch: i2s@fde00000 {
72 compatible = "rockchip,rk3588-i2s-tdm";
76 clock-names = "mclk_tx", "mclk_rx", "hclk";
77 assigned-clocks = <&cru CLK_I2S10_8CH_RX_SRC>;
78 assigned-clock-parents = <&cru PLL_AUPLL>;
80 dma-names = "rx";
81 power-domains = <&power RK3588_PD_VO1>;
83 reset-names = "rx-m";
84 #sound-dai-cells = <0>;
89 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
90 #address-cells = <3>;
91 #size-cells = <2>;
92 bus-range = <0x00 0x0f>;
96 clock-names = "aclk_mst", "aclk_slv",
105 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
106 #interrupt-cells = <1>;
107 interrupt-map-mask = <0 0 0 7>;
108 interrupt-map = <0 0 0 1 &pcie3x4_intc 0>,
112 linux,pci-domain = <0>;
113 max-link-speed = <3>;
114 msi-map = <0x0000 &its1 0x0000 0x1000>;
115 num-lanes = <4>;
117 phy-names = "pcie-phy";
118 power-domains = <&power RK3588_PD_PCIE>;
125 reg-names = "dbi", "apb", "config";
127 reset-names = "pwr", "pipe";
130 pcie3x4_intc: legacy-interrupt-controller {
131 interrupt-controller;
132 #address-cells = <0>;
133 #interrupt-cells = <1>;
134 interrupt-parent = <&gic>;
140 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
141 #address-cells = <3>;
142 #size-cells = <2>;
143 bus-range = <0x10 0x1f>;
147 clock-names = "aclk_mst", "aclk_slv",
156 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
157 #interrupt-cells = <1>;
158 interrupt-map-mask = <0 0 0 7>;
159 interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
163 linux,pci-domain = <1>;
164 max-link-speed = <3>;
165 msi-map = <0x1000 &its1 0x1000 0x1000>;
166 num-lanes = <2>;
168 phy-names = "pcie-phy";
169 power-domains = <&power RK3588_PD_PCIE>;
176 reg-names = "dbi", "apb", "config";
178 reset-names = "pwr", "pipe";
181 pcie3x2_intc: legacy-interrupt-controller {
182 interrupt-controller;
183 #address-cells = <0>;
184 #interrupt-cells = <1>;
185 interrupt-parent = <&gic>;
191 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
192 bus-range = <0x20 0x2f>;
196 clock-names = "aclk_mst", "aclk_slv",
205 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
206 #interrupt-cells = <1>;
207 interrupt-map-mask = <0 0 0 7>;
208 interrupt-map = <0 0 0 1 &pcie2x1l0_intc 0>,
212 linux,pci-domain = <2>;
213 max-link-speed = <2>;
214 msi-map = <0x2000 &its0 0x2000 0x1000>;
215 num-lanes = <1>;
217 phy-names = "pcie-phy";
218 power-domains = <&power RK3588_PD_PCIE>;
225 reg-names = "dbi", "apb", "config";
227 reset-names = "pwr", "pipe";
228 #address-cells = <3>;
229 #size-cells = <2>;
232 pcie2x1l0_intc: legacy-interrupt-controller {
233 interrupt-controller;
234 #address-cells = <0>;
235 #interrupt-cells = <1>;
236 interrupt-parent = <&gic>;
242 compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
246 interrupt-names = "macirq", "eth_wake_irq";
250 clock-names = "stmmaceth", "clk_mac_ref",
253 power-domains = <&power RK3588_PD_GMAC>;
255 reset-names = "stmmaceth";
257 rockchip,php-grf = <&php_grf>;
258 snps,axi-config = <&gmac0_stmmac_axi_setup>;
259 snps,mixed-burst;
260 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
261 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
266 compatible = "snps,dwmac-mdio";
267 #address-cells = <0x1>;
268 #size-cells = <0x0>;
271 gmac0_stmmac_axi_setup: stmmac-axi-config {
277 gmac0_mtl_rx_setup: rx-queues-config {
278 snps,rx-queues-to-use = <2>;
283 gmac0_mtl_tx_setup: tx-queues-config {
284 snps,tx-queues-to-use = <2>;
291 compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
297 clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
298 ports-implemented = <0x1>;
299 #address-cells = <1>;
300 #size-cells = <0>;
303 sata-port@0 {
305 hba-port-cap = <HBA_PORT_FBSCP>;
307 phy-names = "sata-phy";
308 snps,rx-ts-max = <32>;
309 snps,tx-ts-max = <32>;
314 compatible = "rockchip,rk3588-naneng-combphy";
318 clock-names = "ref", "apb", "pipe";
319 assigned-clocks = <&cru CLK_REF_PIPE_PHY1>;
320 assigned-clock-rates = <100000000>;
321 #phy-cells = <1>;
323 reset-names = "phy", "apb";
324 rockchip,pipe-grf = <&php_grf>;
325 rockchip,pipe-phy-grf = <&pipe_phy1_grf>;
330 compatible = "rockchip,rk3588-pcie3-phy";
332 #phy-cells = <0>;
334 clock-names = "pclk";
336 reset-names = "phy";
337 rockchip,pipe-grf = <&php_grf>;
338 rockchip,phy-grf = <&pcie30_phy_grf>;