Lines Matching +full:opp +full:- +full:816000000
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3568-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3568-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
49 #address-cells = <2>;
50 #size-cells = <0>;
54 compatible = "arm,cortex-a55";
57 #cooling-cells = <2>;
58 enable-method = "psci";
59 operating-points-v2 = <&cpu0_opp_table>;
64 compatible = "arm,cortex-a55";
66 #cooling-cells = <2>;
67 enable-method = "psci";
68 operating-points-v2 = <&cpu0_opp_table>;
73 compatible = "arm,cortex-a55";
75 #cooling-cells = <2>;
76 enable-method = "psci";
77 operating-points-v2 = <&cpu0_opp_table>;
82 compatible = "arm,cortex-a55";
84 #cooling-cells = <2>;
85 enable-method = "psci";
86 operating-points-v2 = <&cpu0_opp_table>;
90 cpu0_opp_table: opp-table-0 {
91 compatible = "operating-points-v2";
92 opp-shared;
94 opp-408000000 {
95 opp-hz = /bits/ 64 <408000000>;
96 opp-microvolt = <900000 900000 1150000>;
97 clock-latency-ns = <40000>;
100 opp-600000000 {
101 opp-hz = /bits/ 64 <600000000>;
102 opp-microvolt = <900000 900000 1150000>;
105 opp-816000000 {
106 opp-hz = /bits/ 64 <816000000>;
107 opp-microvolt = <900000 900000 1150000>;
108 opp-suspend;
111 opp-1104000000 {
112 opp-hz = /bits/ 64 <1104000000>;
113 opp-microvolt = <900000 900000 1150000>;
116 opp-1416000000 {
117 opp-hz = /bits/ 64 <1416000000>;
118 opp-microvolt = <900000 900000 1150000>;
121 opp-1608000000 {
122 opp-hz = /bits/ 64 <1608000000>;
123 opp-microvolt = <975000 975000 1150000>;
126 opp-1800000000 {
127 opp-hz = /bits/ 64 <1800000000>;
128 opp-microvolt = <1050000 1050000 1150000>;
132 display_subsystem: display-subsystem {
133 compatible = "rockchip,display-subsystem";
139 compatible = "arm,scmi-smc";
140 arm,smc-id = <0x82000010>;
142 #address-cells = <1>;
143 #size-cells = <0>;
147 #clock-cells = <1>;
152 gpu_opp_table: opp-table-1 {
153 compatible = "operating-points-v2";
155 opp-200000000 {
156 opp-hz = /bits/ 64 <200000000>;
157 opp-microvolt = <825000>;
160 opp-300000000 {
161 opp-hz = /bits/ 64 <300000000>;
162 opp-microvolt = <825000>;
165 opp-400000000 {
166 opp-hz = /bits/ 64 <400000000>;
167 opp-microvolt = <825000>;
170 opp-600000000 {
171 opp-hz = /bits/ 64 <600000000>;
172 opp-microvolt = <825000>;
175 opp-700000000 {
176 opp-hz = /bits/ 64 <700000000>;
177 opp-microvolt = <900000>;
180 opp-800000000 {
181 opp-hz = /bits/ 64 <800000000>;
182 opp-microvolt = <1000000>;
186 hdmi_sound: hdmi-sound {
187 compatible = "simple-audio-card";
188 simple-audio-card,name = "HDMI";
189 simple-audio-card,format = "i2s";
190 simple-audio-card,mclk-fs = <256>;
193 simple-audio-card,codec {
194 sound-dai = <&hdmi>;
197 simple-audio-card,cpu {
198 sound-dai = <&i2s0_8ch>;
203 compatible = "arm,cortex-a55-pmu";
208 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
212 compatible = "arm,psci-1.0";
217 compatible = "arm,armv8-timer";
222 arm,no-tick-in-suspend;
226 compatible = "fixed-clock";
227 clock-frequency = <24000000>;
228 clock-output-names = "xin24m";
229 #clock-cells = <0>;
233 compatible = "fixed-clock";
234 clock-frequency = <32768>;
235 clock-output-names = "xin32k";
236 pinctrl-0 = <&clk32k_out0>;
237 pinctrl-names = "default";
238 #clock-cells = <0>;
242 compatible = "mmio-sram";
244 #address-cells = <1>;
245 #size-cells = <1>;
249 compatible = "arm,scmi-shmem";
255 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
259 clock-names = "sata", "pmalive", "rxoob";
262 phy-names = "sata-phy";
263 ports-implemented = <0x1>;
264 power-domains = <&power RK3568_PD_PIPE>;
269 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
273 clock-names = "sata", "pmalive", "rxoob";
276 phy-names = "sata-phy";
277 ports-implemented = <0x1>;
278 power-domains = <&power RK3568_PD_PIPE>;
283 compatible = "rockchip,rk3568-dwc3", "snps,dwc3";
288 clock-names = "ref_clk", "suspend_clk",
292 power-domains = <&power RK3568_PD_PIPE>;
299 compatible = "rockchip,rk3568-dwc3", "snps,dwc3";
304 clock-names = "ref_clk", "suspend_clk",
308 phy-names = "usb2-phy", "usb3-phy";
310 power-domains = <&power RK3568_PD_PIPE>;
316 gic: interrupt-controller@fd400000 {
317 compatible = "arm,gic-v3";
321 interrupt-controller;
322 #interrupt-cells = <3>;
323 mbi-alias = <0x0 0xfd410000>;
324 mbi-ranges = <296 24>;
325 msi-controller;
329 compatible = "generic-ehci";
335 phy-names = "usb";
340 compatible = "generic-ohci";
346 phy-names = "usb";
351 compatible = "generic-ehci";
357 phy-names = "usb";
362 compatible = "generic-ohci";
368 phy-names = "usb";
373 compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd";
376 pmu_io_domains: io-domains {
377 compatible = "rockchip,rk3568-pmu-io-voltage-domain";
387 compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd";
392 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
397 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
402 compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
407 compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
411 pmucru: clock-controller@fdd00000 {
412 compatible = "rockchip,rk3568-pmucru";
414 #clock-cells = <1>;
415 #reset-cells = <1>;
418 cru: clock-controller@fdd20000 {
419 compatible = "rockchip,rk3568-cru";
422 clock-names = "xin24m";
423 #clock-cells = <1>;
424 #reset-cells = <1>;
425 assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, <&pmucru PLL_PPLL>;
426 assigned-clock-rates = <32768>, <1200000000>, <200000000>;
427 assigned-clock-parents = <&pmucru CLK_RTC32K_FRAC>;
432 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
436 clock-names = "i2c", "pclk";
437 pinctrl-0 = <&i2c0_xfer>;
438 pinctrl-names = "default";
439 #address-cells = <1>;
440 #size-cells = <0>;
445 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
449 clock-names = "baudclk", "apb_pclk";
451 pinctrl-0 = <&uart0_xfer>;
452 pinctrl-names = "default";
453 reg-io-width = <4>;
454 reg-shift = <2>;
459 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
462 clock-names = "pwm", "pclk";
463 pinctrl-0 = <&pwm0m0_pins>;
464 pinctrl-names = "default";
465 #pwm-cells = <3>;
470 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
473 clock-names = "pwm", "pclk";
474 pinctrl-0 = <&pwm1m0_pins>;
475 pinctrl-names = "default";
476 #pwm-cells = <3>;
481 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
484 clock-names = "pwm", "pclk";
485 pinctrl-0 = <&pwm2m0_pins>;
486 pinctrl-names = "default";
487 #pwm-cells = <3>;
492 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
495 clock-names = "pwm", "pclk";
496 pinctrl-0 = <&pwm3_pins>;
497 pinctrl-names = "default";
498 #pwm-cells = <3>;
502 pmu: power-management@fdd90000 {
503 compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd";
506 power: power-controller {
507 compatible = "rockchip,rk3568-power-controller";
508 #power-domain-cells = <1>;
509 #address-cells = <1>;
510 #size-cells = <0>;
513 power-domain@RK3568_PD_GPU {
518 #power-domain-cells = <0>;
522 power-domain@RK3568_PD_VI {
529 #power-domain-cells = <0>;
532 power-domain@RK3568_PD_VO {
540 #power-domain-cells = <0>;
543 power-domain@RK3568_PD_RGA {
553 #power-domain-cells = <0>;
556 power-domain@RK3568_PD_VPU {
560 #power-domain-cells = <0>;
563 power-domain@RK3568_PD_RKVDEC {
567 #power-domain-cells = <0>;
570 power-domain@RK3568_PD_RKVENC {
576 #power-domain-cells = <0>;
582 compatible = "rockchip,rk3568-mali", "arm,mali-bifrost";
587 interrupt-names = "job", "mmu", "gpu";
589 clock-names = "gpu", "bus";
590 #cooling-cells = <2>;
591 operating-points-v2 = <&gpu_opp_table>;
592 power-domains = <&power RK3568_PD_GPU>;
596 vpu: video-codec@fdea0400 {
597 compatible = "rockchip,rk3568-vpu";
601 clock-names = "aclk", "hclk";
603 power-domains = <&power RK3568_PD_VPU>;
607 compatible = "rockchip,rk3568-iommu";
610 clock-names = "aclk", "iface";
612 power-domains = <&power RK3568_PD_VPU>;
613 #iommu-cells = <0>;
617 compatible = "rockchip,rk3568-rga", "rockchip,rk3288-rga";
621 clock-names = "aclk", "hclk", "sclk";
623 reset-names = "core", "axi", "ahb";
624 power-domains = <&power RK3568_PD_RGA>;
627 vepu: video-codec@fdee0000 {
628 compatible = "rockchip,rk3568-vepu";
632 clock-names = "aclk", "hclk";
634 power-domains = <&power RK3568_PD_RGA>;
638 compatible = "rockchip,rk3568-iommu";
642 clock-names = "aclk", "iface";
643 power-domains = <&power RK3568_PD_RGA>;
644 #iommu-cells = <0>;
648 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
653 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
654 fifo-depth = <0x100>;
655 max-frequency = <150000000>;
657 reset-names = "reset";
662 compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
666 interrupt-names = "macirq", "eth_wake_irq";
671 clock-names = "stmmaceth", "mac_clk_rx",
676 reset-names = "stmmaceth";
678 snps,axi-config = <&gmac1_stmmac_axi_setup>;
679 snps,mixed-burst;
680 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
681 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
686 compatible = "snps,dwmac-mdio";
687 #address-cells = <0x1>;
688 #size-cells = <0x0>;
691 gmac1_stmmac_axi_setup: stmmac-axi-config {
697 gmac1_mtl_rx_setup: rx-queues-config {
698 snps,rx-queues-to-use = <1>;
702 gmac1_mtl_tx_setup: tx-queues-config {
703 snps,tx-queues-to-use = <1>;
710 reg-names = "vop", "gamma-lut";
714 clock-names = "aclk", "hclk", "dclk_vp0", "dclk_vp1", "dclk_vp2";
716 power-domains = <&power RK3568_PD_VO>;
721 #address-cells = <1>;
722 #size-cells = <0>;
726 #address-cells = <1>;
727 #size-cells = <0>;
732 #address-cells = <1>;
733 #size-cells = <0>;
738 #address-cells = <1>;
739 #size-cells = <0>;
745 compatible = "rockchip,rk3568-iommu";
749 clock-names = "aclk", "iface";
750 #iommu-cells = <0>;
755 compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi";
758 clock-names = "pclk";
760 phy-names = "dphy";
762 power-domains = <&power RK3568_PD_VO>;
763 reset-names = "apb";
769 #address-cells = <1>;
770 #size-cells = <0>;
783 compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi";
786 clock-names = "pclk";
788 phy-names = "dphy";
790 power-domains = <&power RK3568_PD_VO>;
791 reset-names = "apb";
797 #address-cells = <1>;
798 #size-cells = <0>;
811 compatible = "rockchip,rk3568-dw-hdmi";
819 clock-names = "iahb", "isfr", "cec", "ref";
820 pinctrl-names = "default";
821 pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>;
822 power-domains = <&power RK3568_PD_VO>;
823 reg-io-width = <4>;
825 #sound-dai-cells = <0>;
829 #address-cells = <1>;
830 #size-cells = <0>;
843 compatible = "rockchip,rk3568-qos", "syscon";
848 compatible = "rockchip,rk3568-qos", "syscon";
853 compatible = "rockchip,rk3568-qos", "syscon";
858 compatible = "rockchip,rk3568-qos", "syscon";
863 compatible = "rockchip,rk3568-qos", "syscon";
868 compatible = "rockchip,rk3568-qos", "syscon";
873 compatible = "rockchip,rk3568-qos", "syscon";
878 compatible = "rockchip,rk3568-qos", "syscon";
883 compatible = "rockchip,rk3568-qos", "syscon";
888 compatible = "rockchip,rk3568-qos", "syscon";
893 compatible = "rockchip,rk3568-qos", "syscon";
898 compatible = "rockchip,rk3568-qos", "syscon";
903 compatible = "rockchip,rk3568-qos", "syscon";
908 compatible = "rockchip,rk3568-qos", "syscon";
913 compatible = "rockchip,rk3568-qos", "syscon";
918 compatible = "rockchip,rk3568-qos", "syscon";
923 compatible = "rockchip,rk3568-qos", "syscon";
928 compatible = "rockchip,rk3568-qos", "syscon";
933 compatible = "rockchip,rk3568-qos", "syscon";
938 compatible = "rockchip,rk3568-qos", "syscon";
943 compatible = "rockchip,rk3568-qos", "syscon";
948 compatible = "rockchip,rk3568-qos", "syscon";
953 compatible = "rockchip,rk3568-qos", "syscon";
958 compatible = "rockchip,rk3568-qos", "syscon";
963 compatible = "rockchip,rk3568-dfi";
970 compatible = "rockchip,rk3568-pcie";
974 reg-names = "dbi", "apb", "config";
980 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
981 bus-range = <0x0 0xf>;
985 clock-names = "aclk_mst", "aclk_slv",
988 #interrupt-cells = <1>;
989 interrupt-map-mask = <0 0 0 7>;
990 interrupt-map = <0 0 0 1 &pcie_intc 0>,
994 linux,pci-domain = <0>;
995 num-ib-windows = <6>;
996 num-ob-windows = <2>;
997 max-link-speed = <2>;
998 msi-map = <0x0 &gic 0x0 0x1000>;
999 num-lanes = <1>;
1001 phy-names = "pcie-phy";
1002 power-domains = <&power RK3568_PD_PIPE>;
1007 reset-names = "pipe";
1008 #address-cells = <3>;
1009 #size-cells = <2>;
1012 pcie_intc: legacy-interrupt-controller {
1013 #address-cells = <0>;
1014 #interrupt-cells = <1>;
1015 interrupt-controller;
1016 interrupt-parent = <&gic>;
1022 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
1027 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1028 fifo-depth = <0x100>;
1029 max-frequency = <150000000>;
1031 reset-names = "reset";
1036 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
1041 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1042 fifo-depth = <0x100>;
1043 max-frequency = <150000000>;
1045 reset-names = "reset";
1054 clock-names = "clk_sfc", "hclk_sfc";
1055 pinctrl-0 = <&fspi_pins>;
1056 pinctrl-names = "default";
1061 compatible = "rockchip,rk3568-dwcmshc";
1064 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>;
1065 assigned-clock-rates = <200000000>, <24000000>;
1069 clock-names = "core", "bus", "axi", "block", "timer";
1074 compatible = "rockchip,rk3568-i2s-tdm";
1077 assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>;
1078 assigned-clock-rates = <1188000000>, <1188000000>;
1080 clock-names = "mclk_tx", "mclk_rx", "hclk";
1082 dma-names = "tx";
1084 reset-names = "tx-m", "rx-m";
1086 #sound-dai-cells = <0>;
1091 compatible = "rockchip,rk3568-i2s-tdm";
1094 assigned-clocks = <&cru CLK_I2S1_8CH_TX_SRC>, <&cru CLK_I2S1_8CH_RX_SRC>;
1095 assigned-clock-rates = <1188000000>, <1188000000>;
1098 clock-names = "mclk_tx", "mclk_rx", "hclk";
1100 dma-names = "rx", "tx";
1102 reset-names = "tx-m", "rx-m";
1104 pinctrl-names = "default";
1105 pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_sclkrx
1111 #sound-dai-cells = <0>;
1116 compatible = "rockchip,rk3568-i2s-tdm";
1119 assigned-clocks = <&cru CLK_I2S2_2CH_SRC>;
1120 assigned-clock-rates = <1188000000>;
1122 clock-names = "mclk_tx", "mclk_rx", "hclk";
1124 dma-names = "tx", "rx";
1126 reset-names = "m";
1128 pinctrl-names = "default";
1129 pinctrl-0 = <&i2s2m0_sclktx
1133 #sound-dai-cells = <0>;
1138 compatible = "rockchip,rk3568-i2s-tdm";
1143 clock-names = "mclk_tx", "mclk_rx", "hclk";
1145 dma-names = "tx", "rx";
1147 reset-names = "tx-m", "rx-m";
1149 #sound-dai-cells = <0>;
1154 compatible = "rockchip,rk3568-pdm";
1158 clock-names = "pdm_clk", "pdm_hclk";
1160 dma-names = "rx";
1161 pinctrl-0 = <&pdmm0_clk
1167 pinctrl-names = "default";
1169 reset-names = "pdm-m";
1170 #sound-dai-cells = <0>;
1175 compatible = "rockchip,rk3568-spdif";
1178 clock-names = "mclk", "hclk";
1181 dma-names = "tx";
1182 pinctrl-names = "default";
1183 pinctrl-0 = <&spdifm0_tx>;
1184 #sound-dai-cells = <0>;
1188 dmac0: dma-controller@fe530000 {
1193 arm,pl330-periph-burst;
1195 clock-names = "apb_pclk";
1196 #dma-cells = <1>;
1199 dmac1: dma-controller@fe550000 {
1204 arm,pl330-periph-burst;
1206 clock-names = "apb_pclk";
1207 #dma-cells = <1>;
1211 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1215 clock-names = "i2c", "pclk";
1216 pinctrl-0 = <&i2c1_xfer>;
1217 pinctrl-names = "default";
1218 #address-cells = <1>;
1219 #size-cells = <0>;
1224 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1228 clock-names = "i2c", "pclk";
1229 pinctrl-0 = <&i2c2m0_xfer>;
1230 pinctrl-names = "default";
1231 #address-cells = <1>;
1232 #size-cells = <0>;
1237 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1241 clock-names = "i2c", "pclk";
1242 pinctrl-0 = <&i2c3m0_xfer>;
1243 pinctrl-names = "default";
1244 #address-cells = <1>;
1245 #size-cells = <0>;
1250 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1254 clock-names = "i2c", "pclk";
1255 pinctrl-0 = <&i2c4m0_xfer>;
1256 pinctrl-names = "default";
1257 #address-cells = <1>;
1258 #size-cells = <0>;
1263 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1267 clock-names = "i2c", "pclk";
1268 pinctrl-0 = <&i2c5m0_xfer>;
1269 pinctrl-names = "default";
1270 #address-cells = <1>;
1271 #size-cells = <0>;
1276 compatible = "rockchip,rk3568-wdt", "snps,dw-wdt";
1280 clock-names = "tclk", "pclk";
1284 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
1288 clock-names = "spiclk", "apb_pclk";
1290 dma-names = "tx", "rx";
1291 pinctrl-names = "default";
1292 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
1293 #address-cells = <1>;
1294 #size-cells = <0>;
1299 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
1303 clock-names = "spiclk", "apb_pclk";
1305 dma-names = "tx", "rx";
1306 pinctrl-names = "default";
1307 pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>;
1308 #address-cells = <1>;
1309 #size-cells = <0>;
1314 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
1318 clock-names = "spiclk", "apb_pclk";
1320 dma-names = "tx", "rx";
1321 pinctrl-names = "default";
1322 pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>;
1323 #address-cells = <1>;
1324 #size-cells = <0>;
1329 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
1333 clock-names = "spiclk", "apb_pclk";
1335 dma-names = "tx", "rx";
1336 pinctrl-names = "default";
1337 pinctrl-0 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins>;
1338 #address-cells = <1>;
1339 #size-cells = <0>;
1344 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1348 clock-names = "baudclk", "apb_pclk";
1350 pinctrl-0 = <&uart1m0_xfer>;
1351 pinctrl-names = "default";
1352 reg-io-width = <4>;
1353 reg-shift = <2>;
1358 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1362 clock-names = "baudclk", "apb_pclk";
1364 pinctrl-0 = <&uart2m0_xfer>;
1365 pinctrl-names = "default";
1366 reg-io-width = <4>;
1367 reg-shift = <2>;
1372 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1376 clock-names = "baudclk", "apb_pclk";
1378 pinctrl-0 = <&uart3m0_xfer>;
1379 pinctrl-names = "default";
1380 reg-io-width = <4>;
1381 reg-shift = <2>;
1386 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1390 clock-names = "baudclk", "apb_pclk";
1392 pinctrl-0 = <&uart4m0_xfer>;
1393 pinctrl-names = "default";
1394 reg-io-width = <4>;
1395 reg-shift = <2>;
1400 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1404 clock-names = "baudclk", "apb_pclk";
1406 pinctrl-0 = <&uart5m0_xfer>;
1407 pinctrl-names = "default";
1408 reg-io-width = <4>;
1409 reg-shift = <2>;
1414 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1418 clock-names = "baudclk", "apb_pclk";
1420 pinctrl-0 = <&uart6m0_xfer>;
1421 pinctrl-names = "default";
1422 reg-io-width = <4>;
1423 reg-shift = <2>;
1428 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1432 clock-names = "baudclk", "apb_pclk";
1434 pinctrl-0 = <&uart7m0_xfer>;
1435 pinctrl-names = "default";
1436 reg-io-width = <4>;
1437 reg-shift = <2>;
1442 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1446 clock-names = "baudclk", "apb_pclk";
1448 pinctrl-0 = <&uart8m0_xfer>;
1449 pinctrl-names = "default";
1450 reg-io-width = <4>;
1451 reg-shift = <2>;
1456 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1460 clock-names = "baudclk", "apb_pclk";
1462 pinctrl-0 = <&uart9m0_xfer>;
1463 pinctrl-names = "default";
1464 reg-io-width = <4>;
1465 reg-shift = <2>;
1469 thermal_zones: thermal-zones {
1470 cpu_thermal: cpu-thermal {
1471 polling-delay-passive = <100>;
1472 polling-delay = <1000>;
1474 thermal-sensors = <&tsadc 0>;
1494 cooling-maps {
1497 cooling-device =
1506 gpu_thermal: gpu-thermal {
1507 polling-delay-passive = <20>; /* milliseconds */
1508 polling-delay = <1000>; /* milliseconds */
1510 thermal-sensors = <&tsadc 1>;
1513 gpu_threshold: gpu-threshold {
1518 gpu_target: gpu-target {
1523 gpu_crit: gpu-crit {
1530 cooling-maps {
1533 cooling-device =
1541 compatible = "rockchip,rk3568-tsadc";
1544 assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>;
1545 assigned-clock-rates = <17000000>, <700000>;
1547 clock-names = "tsadc", "apb_pclk";
1551 rockchip,hw-tshut-temp = <95000>;
1552 pinctrl-names = "init", "default", "sleep";
1553 pinctrl-0 = <&tsadc_pin>;
1554 pinctrl-1 = <&tsadc_shutorg>;
1555 pinctrl-2 = <&tsadc_pin>;
1556 #thermal-sensor-cells = <1>;
1561 compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc";
1565 clock-names = "saradc", "apb_pclk";
1567 reset-names = "saradc-apb";
1568 #io-channel-cells = <1>;
1573 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1576 clock-names = "pwm", "pclk";
1577 pinctrl-0 = <&pwm4_pins>;
1578 pinctrl-names = "default";
1579 #pwm-cells = <3>;
1584 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1587 clock-names = "pwm", "pclk";
1588 pinctrl-0 = <&pwm5_pins>;
1589 pinctrl-names = "default";
1590 #pwm-cells = <3>;
1595 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1598 clock-names = "pwm", "pclk";
1599 pinctrl-0 = <&pwm6_pins>;
1600 pinctrl-names = "default";
1601 #pwm-cells = <3>;
1606 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1609 clock-names = "pwm", "pclk";
1610 pinctrl-0 = <&pwm7_pins>;
1611 pinctrl-names = "default";
1612 #pwm-cells = <3>;
1617 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1620 clock-names = "pwm", "pclk";
1621 pinctrl-0 = <&pwm8m0_pins>;
1622 pinctrl-names = "default";
1623 #pwm-cells = <3>;
1628 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1631 clock-names = "pwm", "pclk";
1632 pinctrl-0 = <&pwm9m0_pins>;
1633 pinctrl-names = "default";
1634 #pwm-cells = <3>;
1639 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1642 clock-names = "pwm", "pclk";
1643 pinctrl-0 = <&pwm10m0_pins>;
1644 pinctrl-names = "default";
1645 #pwm-cells = <3>;
1650 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1653 clock-names = "pwm", "pclk";
1654 pinctrl-0 = <&pwm11m0_pins>;
1655 pinctrl-names = "default";
1656 #pwm-cells = <3>;
1661 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1664 clock-names = "pwm", "pclk";
1665 pinctrl-0 = <&pwm12m0_pins>;
1666 pinctrl-names = "default";
1667 #pwm-cells = <3>;
1672 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1675 clock-names = "pwm", "pclk";
1676 pinctrl-0 = <&pwm13m0_pins>;
1677 pinctrl-names = "default";
1678 #pwm-cells = <3>;
1683 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1686 clock-names = "pwm", "pclk";
1687 pinctrl-0 = <&pwm14m0_pins>;
1688 pinctrl-names = "default";
1689 #pwm-cells = <3>;
1694 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1697 clock-names = "pwm", "pclk";
1698 pinctrl-0 = <&pwm15m0_pins>;
1699 pinctrl-names = "default";
1700 #pwm-cells = <3>;
1705 compatible = "rockchip,rk3568-naneng-combphy";
1710 clock-names = "ref", "apb", "pipe";
1711 assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>;
1712 assigned-clock-rates = <100000000>;
1714 rockchip,pipe-grf = <&pipegrf>;
1715 rockchip,pipe-phy-grf = <&pipe_phy_grf1>;
1716 #phy-cells = <1>;
1721 compatible = "rockchip,rk3568-naneng-combphy";
1726 clock-names = "ref", "apb", "pipe";
1727 assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>;
1728 assigned-clock-rates = <100000000>;
1730 rockchip,pipe-grf = <&pipegrf>;
1731 rockchip,pipe-phy-grf = <&pipe_phy_grf2>;
1732 #phy-cells = <1>;
1737 compatible = "rockchip,rk3568-csi-dphy";
1740 clock-names = "pclk";
1741 #phy-cells = <0>;
1743 reset-names = "apb";
1748 dsi_dphy0: mipi-dphy@fe850000 {
1749 compatible = "rockchip,rk3568-dsi-dphy";
1751 clock-names = "ref", "pclk";
1753 #phy-cells = <0>;
1754 power-domains = <&power RK3568_PD_VO>;
1755 reset-names = "apb";
1760 dsi_dphy1: mipi-dphy@fe860000 {
1761 compatible = "rockchip,rk3568-dsi-dphy";
1763 clock-names = "ref", "pclk";
1765 #phy-cells = <0>;
1766 power-domains = <&power RK3568_PD_VO>;
1767 reset-names = "apb";
1773 compatible = "rockchip,rk3568-usb2phy";
1776 clock-names = "phyclk";
1777 clock-output-names = "clk_usbphy0_480m";
1780 #clock-cells = <0>;
1783 usb2phy0_host: host-port {
1784 #phy-cells = <0>;
1788 usb2phy0_otg: otg-port {
1789 #phy-cells = <0>;
1795 compatible = "rockchip,rk3568-usb2phy";
1798 clock-names = "phyclk";
1799 clock-output-names = "clk_usbphy1_480m";
1802 #clock-cells = <0>;
1805 usb2phy1_host: host-port {
1806 #phy-cells = <0>;
1810 usb2phy1_otg: otg-port {
1811 #phy-cells = <0>;
1817 compatible = "rockchip,rk3568-pinctrl";
1820 #address-cells = <2>;
1821 #size-cells = <2>;
1825 compatible = "rockchip,gpio-bank";
1829 gpio-controller;
1830 gpio-ranges = <&pinctrl 0 0 32>;
1831 #gpio-cells = <2>;
1832 interrupt-controller;
1833 #interrupt-cells = <2>;
1837 compatible = "rockchip,gpio-bank";
1841 gpio-controller;
1842 gpio-ranges = <&pinctrl 0 32 32>;
1843 #gpio-cells = <2>;
1844 interrupt-controller;
1845 #interrupt-cells = <2>;
1849 compatible = "rockchip,gpio-bank";
1853 gpio-controller;
1854 gpio-ranges = <&pinctrl 0 64 32>;
1855 #gpio-cells = <2>;
1856 interrupt-controller;
1857 #interrupt-cells = <2>;
1861 compatible = "rockchip,gpio-bank";
1865 gpio-controller;
1866 gpio-ranges = <&pinctrl 0 96 32>;
1867 #gpio-cells = <2>;
1868 interrupt-controller;
1869 #interrupt-cells = <2>;
1873 compatible = "rockchip,gpio-bank";
1877 gpio-controller;
1878 gpio-ranges = <&pinctrl 0 128 32>;
1879 #gpio-cells = <2>;
1880 interrupt-controller;
1881 #interrupt-cells = <2>;
1886 #include "rk3568-pinctrl.dtsi"