Lines Matching full:cru
6 #include <dt-bindings/clock/rk3568-cru.h>
257 clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>,
258 <&cru CLK_SATA1_RXOOB>;
271 clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>,
272 <&cru CLK_SATA2_RXOOB>;
286 clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>,
287 <&cru ACLK_USB3OTG0>;
293 resets = <&cru SRST_USB3OTG0>;
302 clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>,
303 <&cru ACLK_USB3OTG1>;
311 resets = <&cru SRST_USB3OTG1>;
332 clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>,
333 <&cru PCLK_USB>;
343 clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>,
344 <&cru PCLK_USB>;
354 clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>,
355 <&cru PCLK_USB>;
365 clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>,
366 <&cru PCLK_USB>;
418 cru: clock-controller@fdd20000 {
419 compatible = "rockchip,rk3568-cru";
425 assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, <&pmucru PLL_PPLL>;
515 clocks = <&cru ACLK_GPU_PRE>,
516 <&cru PCLK_GPU_PRE>;
524 clocks = <&cru HCLK_VI>,
525 <&cru PCLK_VI>;
534 clocks = <&cru HCLK_VO>,
535 <&cru PCLK_VO>,
536 <&cru ACLK_VOP_PRE>;
545 clocks = <&cru HCLK_RGA_PRE>,
546 <&cru PCLK_RGA_PRE>;
558 clocks = <&cru HCLK_VPU_PRE>;
564 clocks = <&cru HCLK_RKVDEC_PRE>;
572 clocks = <&cru HCLK_RKVENC_PRE>;
588 clocks = <&scmi_clk 1>, <&cru CLK_GPU>;
600 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
611 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
620 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru CLK_RGA_CORE>;
622 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
631 clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>;
641 clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>;
651 clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>,
652 <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>;
656 resets = <&cru SRST_SDMMC2>;
667 clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>,
668 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>,
669 <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>,
670 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>;
675 resets = <&cru SRST_A_GMAC1>;
712 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>, <&cru DCLK_VOP0>,
713 <&cru DCLK_VOP1>, <&cru DCLK_VOP2>;
748 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
759 clocks = <&cru PCLK_DSITX_0>;
764 resets = <&cru SRST_P_DSITX_0>;
787 clocks = <&cru PCLK_DSITX_1>;
792 resets = <&cru SRST_P_DSITX_1>;
814 clocks = <&cru PCLK_HDMI_HOST>,
815 <&cru CLK_HDMI_SFR>,
816 <&cru CLK_HDMI_CEC>,
818 <&cru HCLK_VO>;
982 clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>,
983 <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>,
984 <&cru CLK_PCIE20_AUX_NDFT>;
1006 resets = <&cru SRST_PCIE20_POWERUP>;
1025 clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>,
1026 <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>;
1030 resets = <&cru SRST_SDMMC0>;
1039 clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>,
1040 <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>;
1044 resets = <&cru SRST_SDMMC1>;
1053 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
1064 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>;
1066 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
1067 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
1068 <&cru TCLK_EMMC>;
1077 assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>;
1079 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>;
1083 resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>;
1094 assigned-clocks = <&cru CLK_I2S1_8CH_TX_SRC>, <&cru CLK_I2S1_8CH_RX_SRC>;
1096 clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>,
1097 <&cru HCLK_I2S1_8CH>;
1101 resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>;
1119 assigned-clocks = <&cru CLK_I2S2_2CH_SRC>;
1121 clocks = <&cru MCLK_I2S2_2CH>, <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>;
1125 resets = <&cru SRST_M_I2S2_2CH>;
1141 clocks = <&cru MCLK_I2S3_2CH_TX>, <&cru MCLK_I2S3_2CH_RX>,
1142 <&cru HCLK_I2S3_2CH>;
1146 resets = <&cru SRST_M_I2S3_2CH_TX>, <&cru SRST_M_I2S3_2CH_RX>;
1157 clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>;
1168 resets = <&cru SRST_M_PDM>;
1179 clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>;
1194 clocks = <&cru ACLK_BUS>;
1205 clocks = <&cru ACLK_BUS>;
1214 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
1227 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
1240 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
1253 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
1266 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
1279 clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>;
1287 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
1302 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
1317 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>;
1332 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>;
1347 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
1361 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
1375 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
1389 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
1403 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
1417 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
1431 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
1445 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
1459 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
1544 assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>;
1546 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
1548 resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>,
1549 <&cru SRST_TSADCPHY>;
1564 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
1566 resets = <&cru SRST_P_SARADC>;
1575 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1586 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1597 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1608 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1619 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1630 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1641 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1652 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1663 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
1674 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
1685 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
1696 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
1708 <&cru PCLK_PIPEPHY1>,
1709 <&cru PCLK_PIPE>;
1713 resets = <&cru SRST_PIPEPHY1>;
1724 <&cru PCLK_PIPEPHY2>,
1725 <&cru PCLK_PIPE>;
1729 resets = <&cru SRST_PIPEPHY2>;
1739 clocks = <&cru PCLK_MIPICSIPHY>;
1742 resets = <&cru SRST_P_MIPICSIPHY>;
1752 clocks = <&pmucru CLK_MIPIDSIPHY0_REF>, <&cru PCLK_MIPIDSIPHY0>;
1756 resets = <&cru SRST_P_MIPIDSIPHY0>;
1764 clocks = <&pmucru CLK_MIPIDSIPHY1_REF>, <&cru PCLK_MIPIDSIPHY1>;
1768 resets = <&cru SRST_P_MIPIDSIPHY1>;
1840 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
1852 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
1864 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
1876 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;