Lines Matching +full:0 +full:xfc400000
50 #size-cells = <0>;
52 cpu0: cpu@0 {
55 reg = <0x0 0x0>;
56 clocks = <&scmi_clk 0>;
65 reg = <0x0 0x100>;
74 reg = <0x0 0x200>;
83 reg = <0x0 0x300>;
90 cpu0_opp_table: opp-table-0 {
140 arm,smc-id = <0x82000010>;
143 #size-cells = <0>;
146 reg = <0x14>;
229 #clock-cells = <0>;
236 pinctrl-0 = <&clk32k_out0>;
238 #clock-cells = <0>;
243 reg = <0x0 0x0010f000 0x0 0x100>;
246 ranges = <0 0x0 0x0010f000 0x100>;
248 scmi_shmem: sram@0 {
250 reg = <0x0 0x100>;
256 reg = <0 0xfc400000 0 0x1000>;
263 ports-implemented = <0x1>;
270 reg = <0 0xfc800000 0 0x1000>;
277 ports-implemented = <0x1>;
284 reg = <0x0 0xfcc00000 0x0 0x400000>;
300 reg = <0x0 0xfd000000 0x0 0x400000>;
318 reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
319 <0x0 0xfd460000 0 0x80000>; /* GICR */
323 mbi-alias = <0x0 0xfd410000>;
330 reg = <0x0 0xfd800000 0x0 0x40000>;
341 reg = <0x0 0xfd840000 0x0 0x40000>;
352 reg = <0x0 0xfd880000 0x0 0x40000>;
363 reg = <0x0 0xfd8c0000 0x0 0x40000>;
374 reg = <0x0 0xfdc20000 0x0 0x10000>;
383 reg = <0x0 0xfdc50000 0x0 0x1000>;
388 reg = <0x0 0xfdc60000 0x0 0x10000>;
393 reg = <0x0 0xfdc80000 0x0 0x1000>;
398 reg = <0x0 0xfdc90000 0x0 0x1000>;
403 reg = <0x0 0xfdca0000 0x0 0x8000>;
408 reg = <0x0 0xfdca8000 0x0 0x8000>;
413 reg = <0x0 0xfdd00000 0x0 0x1000>;
420 reg = <0x0 0xfdd20000 0x0 0x1000>;
433 reg = <0x0 0xfdd40000 0x0 0x1000>;
437 pinctrl-0 = <&i2c0_xfer>;
440 #size-cells = <0>;
446 reg = <0x0 0xfdd50000 0x0 0x100>;
450 dmas = <&dmac0 0>, <&dmac0 1>;
451 pinctrl-0 = <&uart0_xfer>;
460 reg = <0x0 0xfdd70000 0x0 0x10>;
463 pinctrl-0 = <&pwm0m0_pins>;
471 reg = <0x0 0xfdd70010 0x0 0x10>;
474 pinctrl-0 = <&pwm1m0_pins>;
482 reg = <0x0 0xfdd70020 0x0 0x10>;
485 pinctrl-0 = <&pwm2m0_pins>;
493 reg = <0x0 0xfdd70030 0x0 0x10>;
496 pinctrl-0 = <&pwm3_pins>;
504 reg = <0x0 0xfdd90000 0x0 0x1000>;
510 #size-cells = <0>;
518 #power-domain-cells = <0>;
529 #power-domain-cells = <0>;
540 #power-domain-cells = <0>;
553 #power-domain-cells = <0>;
560 #power-domain-cells = <0>;
567 #power-domain-cells = <0>;
576 #power-domain-cells = <0>;
583 reg = <0x0 0xfde60000 0x0 0x4000>;
598 reg = <0x0 0xfdea0000 0x0 0x800>;
608 reg = <0x0 0xfdea0800 0x0 0x40>;
613 #iommu-cells = <0>;
618 reg = <0x0 0xfdeb0000 0x0 0x180>;
629 reg = <0x0 0xfdee0000 0x0 0x800>;
639 reg = <0x0 0xfdee0800 0x0 0x40>;
644 #iommu-cells = <0>;
649 reg = <0x0 0xfe000000 0x0 0x4000>;
654 fifo-depth = <0x100>;
663 reg = <0x0 0xfe010000 0x0 0x10000>;
687 #address-cells = <0x1>;
688 #size-cells = <0x0>;
692 snps,blen = <0 0 0 0 16 8 4>;
709 reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>;
722 #size-cells = <0>;
724 vp0: port@0 {
725 reg = <0>;
727 #size-cells = <0>;
733 #size-cells = <0>;
739 #size-cells = <0>;
746 reg = <0x0 0xfe043e00 0x0 0x100>, <0x0 0xfe043f00 0x0 0x100>;
750 #iommu-cells = <0>;
756 reg = <0x00 0xfe060000 0x00 0x10000>;
770 #size-cells = <0>;
772 dsi0_in: port@0 {
773 reg = <0>;
784 reg = <0x0 0xfe070000 0x0 0x10000>;
798 #size-cells = <0>;
800 dsi1_in: port@0 {
801 reg = <0>;
812 reg = <0x0 0xfe0a0000 0x0 0x20000>;
821 pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>;
825 #sound-dai-cells = <0>;
830 #size-cells = <0>;
832 hdmi_in: port@0 {
833 reg = <0>;
844 reg = <0x0 0xfe128000 0x0 0x20>;
849 reg = <0x0 0xfe138080 0x0 0x20>;
854 reg = <0x0 0xfe138100 0x0 0x20>;
859 reg = <0x0 0xfe138180 0x0 0x20>;
864 reg = <0x0 0xfe148000 0x0 0x20>;
869 reg = <0x0 0xfe148080 0x0 0x20>;
874 reg = <0x0 0xfe148100 0x0 0x20>;
879 reg = <0x0 0xfe150000 0x0 0x20>;
884 reg = <0x0 0xfe158000 0x0 0x20>;
889 reg = <0x0 0xfe158100 0x0 0x20>;
894 reg = <0x0 0xfe158180 0x0 0x20>;
899 reg = <0x0 0xfe158200 0x0 0x20>;
904 reg = <0x0 0xfe158280 0x0 0x20>;
909 reg = <0x0 0xfe158300 0x0 0x20>;
914 reg = <0x0 0xfe180000 0x0 0x20>;
919 reg = <0x0 0xfe190000 0x0 0x20>;
924 reg = <0x0 0xfe190280 0x0 0x20>;
929 reg = <0x0 0xfe190300 0x0 0x20>;
934 reg = <0x0 0xfe190380 0x0 0x20>;
939 reg = <0x0 0xfe190400 0x0 0x20>;
944 reg = <0x0 0xfe198000 0x0 0x20>;
949 reg = <0x0 0xfe1a8000 0x0 0x20>;
954 reg = <0x0 0xfe1a8080 0x0 0x20>;
959 reg = <0x0 0xfe1a8100 0x0 0x20>;
964 reg = <0x00 0xfe230000 0x00 0x400>;
971 reg = <0x3 0xc0000000 0x0 0x00400000>,
972 <0x0 0xfe260000 0x0 0x00010000>,
973 <0x0 0xf4000000 0x0 0x00100000>;
981 bus-range = <0x0 0xf>;
989 interrupt-map-mask = <0 0 0 7>;
990 interrupt-map = <0 0 0 1 &pcie_intc 0>,
991 <0 0 0 2 &pcie_intc 1>,
992 <0 0 0 3 &pcie_intc 2>,
993 <0 0 0 4 &pcie_intc 3>;
994 linux,pci-domain = <0>;
998 msi-map = <0x0 &gic 0x0 0x1000>;
1003 ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
1004 <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x01e00000>,
1005 <0x03000000 0x0 0x40000000 0x3 0x00000000 0x0 0x40000000>;
1013 #address-cells = <0>;
1023 reg = <0x0 0xfe2b0000 0x0 0x4000>;
1028 fifo-depth = <0x100>;
1037 reg = <0x0 0xfe2c0000 0x0 0x4000>;
1042 fifo-depth = <0x100>;
1051 reg = <0x0 0xfe300000 0x0 0x4000>;
1055 pinctrl-0 = <&fspi_pins>;
1062 reg = <0x0 0xfe310000 0x0 0x10000>;
1075 reg = <0x0 0xfe400000 0x0 0x1000>;
1081 dmas = <&dmac1 0>;
1086 #sound-dai-cells = <0>;
1092 reg = <0x0 0xfe410000 0x0 0x1000>;
1105 pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_sclkrx
1111 #sound-dai-cells = <0>;
1117 reg = <0x0 0xfe420000 0x0 0x1000>;
1129 pinctrl-0 = <&i2s2m0_sclktx
1133 #sound-dai-cells = <0>;
1139 reg = <0x0 0xfe430000 0x0 0x1000>;
1149 #sound-dai-cells = <0>;
1155 reg = <0x0 0xfe440000 0x0 0x1000>;
1161 pinctrl-0 = <&pdmm0_clk
1170 #sound-dai-cells = <0>;
1176 reg = <0x0 0xfe460000 0x0 0x1000>;
1183 pinctrl-0 = <&spdifm0_tx>;
1184 #sound-dai-cells = <0>;
1190 reg = <0x0 0xfe530000 0x0 0x4000>;
1201 reg = <0x0 0xfe550000 0x0 0x4000>;
1212 reg = <0x0 0xfe5a0000 0x0 0x1000>;
1216 pinctrl-0 = <&i2c1_xfer>;
1219 #size-cells = <0>;
1225 reg = <0x0 0xfe5b0000 0x0 0x1000>;
1229 pinctrl-0 = <&i2c2m0_xfer>;
1232 #size-cells = <0>;
1238 reg = <0x0 0xfe5c0000 0x0 0x1000>;
1242 pinctrl-0 = <&i2c3m0_xfer>;
1245 #size-cells = <0>;
1251 reg = <0x0 0xfe5d0000 0x0 0x1000>;
1255 pinctrl-0 = <&i2c4m0_xfer>;
1258 #size-cells = <0>;
1264 reg = <0x0 0xfe5e0000 0x0 0x1000>;
1268 pinctrl-0 = <&i2c5m0_xfer>;
1271 #size-cells = <0>;
1277 reg = <0x0 0xfe600000 0x0 0x100>;
1285 reg = <0x0 0xfe610000 0x0 0x1000>;
1292 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
1294 #size-cells = <0>;
1300 reg = <0x0 0xfe620000 0x0 0x1000>;
1307 pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>;
1309 #size-cells = <0>;
1315 reg = <0x0 0xfe630000 0x0 0x1000>;
1322 pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>;
1324 #size-cells = <0>;
1330 reg = <0x0 0xfe640000 0x0 0x1000>;
1337 pinctrl-0 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins>;
1339 #size-cells = <0>;
1345 reg = <0x0 0xfe650000 0x0 0x100>;
1350 pinctrl-0 = <&uart1m0_xfer>;
1359 reg = <0x0 0xfe660000 0x0 0x100>;
1364 pinctrl-0 = <&uart2m0_xfer>;
1373 reg = <0x0 0xfe670000 0x0 0x100>;
1378 pinctrl-0 = <&uart3m0_xfer>;
1387 reg = <0x0 0xfe680000 0x0 0x100>;
1392 pinctrl-0 = <&uart4m0_xfer>;
1401 reg = <0x0 0xfe690000 0x0 0x100>;
1406 pinctrl-0 = <&uart5m0_xfer>;
1415 reg = <0x0 0xfe6a0000 0x0 0x100>;
1420 pinctrl-0 = <&uart6m0_xfer>;
1429 reg = <0x0 0xfe6b0000 0x0 0x100>;
1434 pinctrl-0 = <&uart7m0_xfer>;
1443 reg = <0x0 0xfe6c0000 0x0 0x100>;
1448 pinctrl-0 = <&uart8m0_xfer>;
1457 reg = <0x0 0xfe6d0000 0x0 0x100>;
1462 pinctrl-0 = <&uart9m0_xfer>;
1474 thermal-sensors = <&tsadc 0>;
1542 reg = <0x0 0xfe710000 0x0 0x100>;
1553 pinctrl-0 = <&tsadc_pin>;
1562 reg = <0x0 0xfe720000 0x0 0x100>;
1574 reg = <0x0 0xfe6e0000 0x0 0x10>;
1577 pinctrl-0 = <&pwm4_pins>;
1585 reg = <0x0 0xfe6e0010 0x0 0x10>;
1588 pinctrl-0 = <&pwm5_pins>;
1596 reg = <0x0 0xfe6e0020 0x0 0x10>;
1599 pinctrl-0 = <&pwm6_pins>;
1607 reg = <0x0 0xfe6e0030 0x0 0x10>;
1610 pinctrl-0 = <&pwm7_pins>;
1618 reg = <0x0 0xfe6f0000 0x0 0x10>;
1621 pinctrl-0 = <&pwm8m0_pins>;
1629 reg = <0x0 0xfe6f0010 0x0 0x10>;
1632 pinctrl-0 = <&pwm9m0_pins>;
1640 reg = <0x0 0xfe6f0020 0x0 0x10>;
1643 pinctrl-0 = <&pwm10m0_pins>;
1651 reg = <0x0 0xfe6f0030 0x0 0x10>;
1654 pinctrl-0 = <&pwm11m0_pins>;
1662 reg = <0x0 0xfe700000 0x0 0x10>;
1665 pinctrl-0 = <&pwm12m0_pins>;
1673 reg = <0x0 0xfe700010 0x0 0x10>;
1676 pinctrl-0 = <&pwm13m0_pins>;
1684 reg = <0x0 0xfe700020 0x0 0x10>;
1687 pinctrl-0 = <&pwm14m0_pins>;
1695 reg = <0x0 0xfe700030 0x0 0x10>;
1698 pinctrl-0 = <&pwm15m0_pins>;
1706 reg = <0x0 0xfe830000 0x0 0x100>;
1722 reg = <0x0 0xfe840000 0x0 0x100>;
1738 reg = <0x0 0xfe870000 0x0 0x10000>;
1741 #phy-cells = <0>;
1750 reg = <0x0 0xfe850000 0x0 0x10000>;
1753 #phy-cells = <0>;
1762 reg = <0x0 0xfe860000 0x0 0x10000>;
1765 #phy-cells = <0>;
1774 reg = <0x0 0xfe8a0000 0x0 0x10000>;
1780 #clock-cells = <0>;
1784 #phy-cells = <0>;
1789 #phy-cells = <0>;
1796 reg = <0x0 0xfe8b0000 0x0 0x10000>;
1802 #clock-cells = <0>;
1806 #phy-cells = <0>;
1811 #phy-cells = <0>;
1826 reg = <0x0 0xfdd60000 0x0 0x100>;
1830 gpio-ranges = <&pinctrl 0 0 32>;
1838 reg = <0x0 0xfe740000 0x0 0x100>;
1842 gpio-ranges = <&pinctrl 0 32 32>;
1850 reg = <0x0 0xfe750000 0x0 0x100>;
1854 gpio-ranges = <&pinctrl 0 64 32>;
1862 reg = <0x0 0xfe760000 0x0 0x100>;
1866 gpio-ranges = <&pinctrl 0 96 32>;
1874 reg = <0x0 0xfe770000 0x0 0x100>;
1878 gpio-ranges = <&pinctrl 0 128 32>;