Lines Matching +full:pcie +full:- +full:ob
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
12 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
16 clock-names = "sata", "pmalive", "rxoob";
19 phy-names = "sata-phy";
20 ports-implemented = <0x1>;
21 power-domains = <&power RK3568_PD_PIPE>;
26 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
31 compatible = "rockchip,rk3568-qos", "syscon";
36 compatible = "rockchip,rk3568-qos", "syscon";
41 compatible = "rockchip,rk3568-qos", "syscon";
46 compatible = "rockchip,rk3568-pcie3-phy-grf", "syscon";
51 compatible = "rockchip,rk3568-pcie3-phy";
53 #phy-cells = <0>;
56 clock-names = "refclk_m", "refclk_n", "pclk";
58 reset-names = "phy";
59 rockchip,phy-grf = <&pcie30_phy_grf>;
63 pcie3x1: pcie@fe270000 {
64 compatible = "rockchip,rk3568-pcie";
65 #address-cells = <3>;
66 #size-cells = <2>;
67 bus-range = <0x0 0xf>;
71 clock-names = "aclk_mst", "aclk_slv",
79 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
80 #interrupt-cells = <1>;
81 interrupt-map-mask = <0 0 0 7>;
82 interrupt-map = <0 0 0 1 &pcie3x1_intc 0>,
86 linux,pci-domain = <1>;
87 num-ib-windows = <6>;
88 num-ob-windows = <2>;
89 max-link-speed = <3>;
90 msi-map = <0x0 &gic 0x1000 0x1000>;
91 num-lanes = <1>;
93 phy-names = "pcie-phy";
94 power-domains = <&power RK3568_PD_PIPE>;
101 reg-names = "dbi", "apb", "config";
103 reset-names = "pipe";
107 pcie3x1_intc: legacy-interrupt-controller {
108 interrupt-controller;
109 #address-cells = <0>;
110 #interrupt-cells = <1>;
111 interrupt-parent = <&gic>;
116 pcie3x2: pcie@fe280000 {
117 compatible = "rockchip,rk3568-pcie";
118 #address-cells = <3>;
119 #size-cells = <2>;
120 bus-range = <0x0 0xf>;
124 clock-names = "aclk_mst", "aclk_slv",
132 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
133 #interrupt-cells = <1>;
134 interrupt-map-mask = <0 0 0 7>;
135 interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
139 linux,pci-domain = <2>;
140 num-ib-windows = <6>;
141 num-ob-windows = <2>;
142 max-link-speed = <3>;
143 msi-map = <0x0 &gic 0x2000 0x1000>;
144 num-lanes = <2>;
146 phy-names = "pcie-phy";
147 power-domains = <&power RK3568_PD_PIPE>;
154 reg-names = "dbi", "apb", "config";
156 reset-names = "pipe";
160 pcie3x2_intc: legacy-interrupt-controller {
161 interrupt-controller;
162 #address-cells = <0>;
163 #interrupt-cells = <1>;
164 interrupt-parent = <&gic>;
170 compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
174 interrupt-names = "macirq", "eth_wake_irq";
179 clock-names = "stmmaceth", "mac_clk_rx",
184 reset-names = "stmmaceth";
186 snps,axi-config = <&gmac0_stmmac_axi_setup>;
187 snps,mixed-burst;
188 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
189 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
194 compatible = "snps,dwmac-mdio";
195 #address-cells = <0x1>;
196 #size-cells = <0x0>;
199 gmac0_stmmac_axi_setup: stmmac-axi-config {
205 gmac0_mtl_rx_setup: rx-queues-config {
206 snps,rx-queues-to-use = <1>;
210 gmac0_mtl_tx_setup: tx-queues-config {
211 snps,tx-queues-to-use = <1>;
217 compatible = "rockchip,rk3568-naneng-combphy";
222 clock-names = "ref", "apb", "pipe";
223 assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
224 assigned-clock-rates = <100000000>;
226 rockchip,pipe-grf = <&pipegrf>;
227 rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
228 #phy-cells = <1>;
234 opp-1992000000 {
235 opp-hz = /bits/ 64 <1992000000>;
236 opp-microvolt = <1150000 1150000 1150000>;
241 compatible = "rockchip,rk3568-pipe-grf", "syscon";
245 power-domain@RK3568_PD_PIPE {
256 #power-domain-cells = <0>;
262 phy-names = "usb2-phy", "usb3-phy";
266 compatible = "rockchip,rk3568-vop";