Lines Matching +full:0 +full:xf0100000

13 		reg = <0 0xfc000000 0 0x1000>;
20 		ports-implemented = <0x1>;
27 		reg = <0x0 0xfdc70000 0x0 0x1000>;
32 		reg = <0x0 0xfe190080 0x0 0x20>;
37 		reg = <0x0 0xfe190100 0x0 0x20>;
42 		reg = <0x0 0xfe190200 0x0 0x20>;
47 		reg = <0x0 0xfdcb8000 0x0 0x10000>;
52 		reg = <0x0 0xfe8c0000 0x0 0x20000>;
53 		#phy-cells = <0>;
67 		bus-range = <0x0 0xf>;
81 		interrupt-map-mask = <0 0 0 7>;
82 		interrupt-map = <0 0 0 1 &pcie3x1_intc 0>,
83 				<0 0 0 2 &pcie3x1_intc 1>,
84 				<0 0 0 3 &pcie3x1_intc 2>,
85 				<0 0 0 4 &pcie3x1_intc 3>;
90 		msi-map = <0x0 &gic 0x1000 0x1000>;
95 		reg = <0x3 0xc0400000 0x0 0x00400000>,
96 		      <0x0 0xfe270000 0x0 0x00010000>,
97 		      <0x0 0xf2000000 0x0 0x00100000>;
98 		ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>,
99 			 <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x01e00000>,
100 			 <0x03000000 0x0 0x40000000 0x3 0x40000000 0x0 0x40000000>;
109 			#address-cells = <0>;
120 		bus-range = <0x0 0xf>;
134 		interrupt-map-mask = <0 0 0 7>;
135 		interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
136 				<0 0 0 2 &pcie3x2_intc 1>,
137 				<0 0 0 3 &pcie3x2_intc 2>,
138 				<0 0 0 4 &pcie3x2_intc 3>;
143 		msi-map = <0x0 &gic 0x2000 0x1000>;
148 		reg = <0x3 0xc0800000 0x0 0x00400000>,
149 		      <0x0 0xfe280000 0x0 0x00010000>,
150 		      <0x0 0xf0000000 0x0 0x00100000>;
151 		ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>,
152 			 <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x01e00000>,
153 			 <0x03000000 0x0 0x40000000 0x3 0x80000000 0x0 0x40000000>;
162 			#address-cells = <0>;
171 		reg = <0x0 0xfe2a0000 0x0 0x10000>;
195 			#address-cells = <0x1>;
196 			#size-cells = <0x0>;
200 			snps,blen = <0 0 0 0 16 8 4>;
218 		reg = <0x0 0xfe820000 0x0 0x100>;
256 		#power-domain-cells = <0>;