Lines Matching +full:rk3399 +full:- +full:qos
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/clock/rockchip,rk3528-cru.h>
12 #include <dt-bindings/reset/rockchip,rk3528-cru.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
30 #address-cells = <1>;
31 #size-cells = <0>;
33 cpu-map {
51 compatible = "arm,cortex-a53";
54 enable-method = "psci";
59 compatible = "arm,cortex-a53";
62 enable-method = "psci";
67 compatible = "arm,cortex-a53";
70 enable-method = "psci";
75 compatible = "arm,cortex-a53";
78 enable-method = "psci";
85 compatible = "arm,scmi-smc";
86 arm,smc-id = <0x82000010>;
88 #address-cells = <1>;
89 #size-cells = <0>;
93 #clock-cells = <1>;
98 gpu_opp_table: opp-table-gpu {
99 compatible = "operating-points-v2";
101 opp-300000000 {
102 opp-hz = /bits/ 64 <300000000>;
103 opp-microvolt = <875000 875000 1000000>;
104 opp-suspend;
107 opp-500000000 {
108 opp-hz = /bits/ 64 <500000000>;
109 opp-microvolt = <875000 875000 1000000>;
112 opp-600000000 {
113 opp-hz = /bits/ 64 <600000000>;
114 opp-microvolt = <875000 875000 1000000>;
117 opp-700000000 {
118 opp-hz = /bits/ 64 <700000000>;
119 opp-microvolt = <900000 900000 1000000>;
122 opp-800000000 {
123 opp-hz = /bits/ 64 <800000000>;
124 opp-microvolt = <950000 950000 1000000>;
129 compatible = "rockchip,rk3528-pinctrl";
131 #address-cells = <2>;
132 #size-cells = <2>;
136 compatible = "rockchip,gpio-bank";
140 gpio-controller;
141 #gpio-cells = <2>;
142 gpio-ranges = <&pinctrl 0 0 32>;
143 interrupt-controller;
144 #interrupt-cells = <2>;
148 compatible = "rockchip,gpio-bank";
152 gpio-controller;
153 #gpio-cells = <2>;
154 gpio-ranges = <&pinctrl 0 32 32>;
155 interrupt-controller;
156 #interrupt-cells = <2>;
160 compatible = "rockchip,gpio-bank";
164 gpio-controller;
165 #gpio-cells = <2>;
166 gpio-ranges = <&pinctrl 0 64 32>;
167 interrupt-controller;
168 #interrupt-cells = <2>;
172 compatible = "rockchip,gpio-bank";
176 gpio-controller;
177 #gpio-cells = <2>;
178 gpio-ranges = <&pinctrl 0 96 32>;
179 interrupt-controller;
180 #interrupt-cells = <2>;
184 compatible = "rockchip,gpio-bank";
188 gpio-controller;
189 #gpio-cells = <2>;
190 gpio-ranges = <&pinctrl 0 128 32>;
191 interrupt-controller;
192 #interrupt-cells = <2>;
197 compatible = "arm,psci-1.0", "arm,psci-0.2";
201 reserved-memory {
202 #address-cells = <2>;
203 #size-cells = <2>;
207 compatible = "arm,scmi-shmem";
209 no-map;
214 compatible = "arm,armv8-timer";
221 xin24m: clock-xin24m {
222 compatible = "fixed-clock";
223 clock-frequency = <24000000>;
224 clock-output-names = "xin24m";
225 #clock-cells = <0>;
228 gmac0_clk: clock-gmac50m {
229 compatible = "fixed-clock";
230 clock-frequency = <50000000>;
231 clock-output-names = "gmac0";
232 #clock-cells = <0>;
236 compatible = "simple-bus";
238 #address-cells = <2>;
239 #size-cells = <2>;
241 gic: interrupt-controller@fed01000 {
242 compatible = "arm,gic-400";
249 interrupt-controller;
250 #address-cells = <0>;
251 #interrupt-cells = <3>;
254 qos_crypto_a: qos@ff200000 {
255 compatible = "rockchip,rk3528-qos", "syscon";
259 qos_crypto_p: qos@ff200080 {
260 compatible = "rockchip,rk3528-qos", "syscon";
264 qos_dcf: qos@ff200100 {
265 compatible = "rockchip,rk3528-qos", "syscon";
269 qos_dft2apb: qos@ff200200 {
270 compatible = "rockchip,rk3528-qos", "syscon";
274 qos_dma2ddr: qos@ff200280 {
275 compatible = "rockchip,rk3528-qos", "syscon";
279 qos_dmac: qos@ff200300 {
280 compatible = "rockchip,rk3528-qos", "syscon";
284 qos_keyreader: qos@ff200380 {
285 compatible = "rockchip,rk3528-qos", "syscon";
289 qos_cpu: qos@ff210000 {
290 compatible = "rockchip,rk3528-qos", "syscon";
294 qos_debug: qos@ff210080 {
295 compatible = "rockchip,rk3528-qos", "syscon";
299 qos_gpu_m0: qos@ff220000 {
300 compatible = "rockchip,rk3528-qos", "syscon";
304 qos_gpu_m1: qos@ff220080 {
305 compatible = "rockchip,rk3528-qos", "syscon";
309 qos_pmu_mcu: qos@ff240000 {
310 compatible = "rockchip,rk3528-qos", "syscon";
314 qos_rkvdec: qos@ff250000 {
315 compatible = "rockchip,rk3528-qos", "syscon";
319 qos_rkvenc: qos@ff260000 {
320 compatible = "rockchip,rk3528-qos", "syscon";
324 qos_gmac0: qos@ff270000 {
325 compatible = "rockchip,rk3528-qos", "syscon";
329 qos_hdcp: qos@ff270080 {
330 compatible = "rockchip,rk3528-qos", "syscon";
334 qos_jpegdec: qos@ff270100 {
335 compatible = "rockchip,rk3528-qos", "syscon";
339 qos_rga2_m0ro: qos@ff270200 {
340 compatible = "rockchip,rk3528-qos", "syscon";
344 qos_rga2_m0wo: qos@ff270280 {
345 compatible = "rockchip,rk3528-qos", "syscon";
349 qos_sdmmc0: qos@ff270300 {
350 compatible = "rockchip,rk3528-qos", "syscon";
354 qos_usb2host: qos@ff270380 {
355 compatible = "rockchip,rk3528-qos", "syscon";
359 qos_vdpp: qos@ff270480 {
360 compatible = "rockchip,rk3528-qos", "syscon";
364 qos_vop: qos@ff270500 {
365 compatible = "rockchip,rk3528-qos", "syscon";
369 qos_emmc: qos@ff280000 {
370 compatible = "rockchip,rk3528-qos", "syscon";
374 qos_fspi: qos@ff280080 {
375 compatible = "rockchip,rk3528-qos", "syscon";
379 qos_gmac1: qos@ff280100 {
380 compatible = "rockchip,rk3528-qos", "syscon";
384 qos_pcie: qos@ff280180 {
385 compatible = "rockchip,rk3528-qos", "syscon";
389 qos_sdio0: qos@ff280200 {
390 compatible = "rockchip,rk3528-qos", "syscon";
394 qos_sdio1: qos@ff280280 {
395 compatible = "rockchip,rk3528-qos", "syscon";
399 qos_tsp: qos@ff280300 {
400 compatible = "rockchip,rk3528-qos", "syscon";
404 qos_usb3otg: qos@ff280380 {
405 compatible = "rockchip,rk3528-qos", "syscon";
409 qos_vpu: qos@ff280400 {
410 compatible = "rockchip,rk3528-qos", "syscon";
415 compatible = "rockchip,rk3528-vpu-grf", "syscon";
420 compatible = "rockchip,rk3528-vo-grf", "syscon";
424 cru: clock-controller@ff4a0000 {
425 compatible = "rockchip,rk3528-cru";
427 assigned-clocks =
444 assigned-clock-rates =
462 clock-names = "xin24m", "gmac0";
463 #clock-cells = <1>;
464 #reset-cells = <1>;
468 compatible = "rockchip,rk3528-ioc-grf", "syscon";
472 pmu: power-management@ff600000 {
473 compatible = "rockchip,rk3528-pmu", "syscon", "simple-mfd";
476 power: power-controller {
477 compatible = "rockchip,rk3528-power-controller";
478 #power-domain-cells = <1>;
479 #address-cells = <1>;
480 #size-cells = <0>;
483 power-domain@4 {
489 #power-domain-cells = <0>;
493 power-domain@5 {
496 #power-domain-cells = <0>;
499 power-domain@6 {
502 #power-domain-cells = <0>;
505 power-domain@7 {
516 #power-domain-cells = <0>;
519 power-domain@8 {
530 #power-domain-cells = <0>;
537 compatible = "rockchip,rk3528-mali", "arm,mali-450";
539 assigned-clocks = <&cru ACLK_GPU_MALI>,
541 assigned-clock-rates = <297000000>, <300000000>;
543 clock-names = "bus", "core";
551 interrupt-names = "gp",
558 operating-points-v2 = <&gpu_opp_table>;
559 power-domains = <&power 4>;
565 compatible = "rockchip,rk3528-spi",
566 "rockchip,rk3066-spi";
569 clock-names = "spiclk", "apb_pclk";
572 dma-names = "tx", "rx";
573 #address-cells = <1>;
574 #size-cells = <0>;
579 compatible = "rockchip,rk3528-spi",
580 "rockchip,rk3066-spi";
583 clock-names = "spiclk", "apb_pclk";
586 dma-names = "tx", "rx";
587 #address-cells = <1>;
588 #size-cells = <0>;
593 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
596 clock-names = "baudclk", "apb_pclk";
599 reg-io-width = <4>;
600 reg-shift = <2>;
605 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
608 clock-names = "baudclk", "apb_pclk";
611 reg-io-width = <4>;
612 reg-shift = <2>;
617 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
620 clock-names = "baudclk", "apb_pclk";
623 reg-io-width = <4>;
624 reg-shift = <2>;
629 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
632 clock-names = "baudclk", "apb_pclk";
635 reg-io-width = <4>;
636 reg-shift = <2>;
641 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
644 clock-names = "baudclk", "apb_pclk";
647 reg-io-width = <4>;
648 reg-shift = <2>;
653 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
656 clock-names = "baudclk", "apb_pclk";
659 reg-io-width = <4>;
660 reg-shift = <2>;
665 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
668 clock-names = "baudclk", "apb_pclk";
671 reg-io-width = <4>;
672 reg-shift = <2>;
677 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
680 clock-names = "baudclk", "apb_pclk";
683 reg-io-width = <4>;
684 reg-shift = <2>;
689 compatible = "rockchip,rk3528-i2c",
690 "rockchip,rk3399-i2c";
693 clock-names = "i2c", "pclk";
695 #address-cells = <1>;
696 #size-cells = <0>;
701 compatible = "rockchip,rk3528-i2c",
702 "rockchip,rk3399-i2c";
705 clock-names = "i2c", "pclk";
707 #address-cells = <1>;
708 #size-cells = <0>;
713 compatible = "rockchip,rk3528-i2c",
714 "rockchip,rk3399-i2c";
717 clock-names = "i2c", "pclk";
719 pinctrl-names = "default";
720 pinctrl-0 = <&i2c2m1_xfer>;
721 #address-cells = <1>;
722 #size-cells = <0>;
727 compatible = "rockchip,rk3528-i2c",
728 "rockchip,rk3399-i2c";
731 clock-names = "i2c", "pclk";
733 #address-cells = <1>;
734 #size-cells = <0>;
739 compatible = "rockchip,rk3528-i2c",
740 "rockchip,rk3399-i2c";
743 clock-names = "i2c", "pclk";
745 pinctrl-names = "default";
746 pinctrl-0 = <&i2c4_xfer>;
747 #address-cells = <1>;
748 #size-cells = <0>;
753 compatible = "rockchip,rk3528-i2c",
754 "rockchip,rk3399-i2c";
757 clock-names = "i2c", "pclk";
759 #address-cells = <1>;
760 #size-cells = <0>;
765 compatible = "rockchip,rk3528-i2c",
766 "rockchip,rk3399-i2c";
769 clock-names = "i2c", "pclk";
771 #address-cells = <1>;
772 #size-cells = <0>;
777 compatible = "rockchip,rk3528-i2c",
778 "rockchip,rk3399-i2c";
781 clock-names = "i2c", "pclk";
783 pinctrl-names = "default";
784 pinctrl-0 = <&i2c7_xfer>;
785 #address-cells = <1>;
786 #size-cells = <0>;
791 compatible = "rockchip,rk3528-pwm",
792 "rockchip,rk3328-pwm";
795 clock-names = "pwm", "pclk";
796 #pwm-cells = <3>;
801 compatible = "rockchip,rk3528-pwm",
802 "rockchip,rk3328-pwm";
805 clock-names = "pwm", "pclk";
806 #pwm-cells = <3>;
811 compatible = "rockchip,rk3528-pwm",
812 "rockchip,rk3328-pwm";
815 clock-names = "pwm", "pclk";
816 #pwm-cells = <3>;
821 compatible = "rockchip,rk3528-pwm",
822 "rockchip,rk3328-pwm";
825 clock-names = "pwm", "pclk";
826 #pwm-cells = <3>;
831 compatible = "rockchip,rk3528-pwm",
832 "rockchip,rk3328-pwm";
835 clock-names = "pwm", "pclk";
836 #pwm-cells = <3>;
841 compatible = "rockchip,rk3528-pwm",
842 "rockchip,rk3328-pwm";
845 clock-names = "pwm", "pclk";
846 #pwm-cells = <3>;
851 compatible = "rockchip,rk3528-pwm",
852 "rockchip,rk3328-pwm";
855 clock-names = "pwm", "pclk";
856 #pwm-cells = <3>;
861 compatible = "rockchip,rk3528-pwm",
862 "rockchip,rk3328-pwm";
865 clock-names = "pwm", "pclk";
866 #pwm-cells = <3>;
871 compatible = "rockchip,rk3528-saradc";
874 clock-names = "saradc", "apb_pclk";
877 reset-names = "saradc-apb";
878 #io-channel-cells = <1>;
883 compatible = "rockchip,rk3528-gmac", "snps,dwmac-4.20a";
888 clock-names = "stmmaceth", "clk_mac_ref",
893 interrupt-names = "macirq", "eth_wake_irq";
894 phy-handle = <&rmii0_phy>;
895 phy-mode = "rmii";
897 reset-names = "stmmaceth";
899 snps,axi-config = <&gmac0_stmmac_axi_setup>;
900 snps,mixed-burst;
901 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
902 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
907 compatible = "snps,dwmac-mdio";
908 #address-cells = <0x1>;
909 #size-cells = <0x0>;
911 rmii0_phy: ethernet-phy@2 {
912 compatible = "ethernet-phy-ieee802.3-c22";
915 phy-is-integrated;
916 pinctrl-names = "default";
917 pinctrl-0 = <&fephym0_led_link>,
923 gmac0_stmmac_axi_setup: stmmac-axi-config {
929 gmac0_mtl_rx_setup: rx-queues-config {
930 snps,rx-queues-to-use = <1>;
934 gmac0_mtl_tx_setup: tx-queues-config {
935 snps,tx-queues-to-use = <1>;
941 compatible = "rockchip,rk3528-gmac", "snps,dwmac-4.20a";
947 clock-names = "stmmaceth",
953 interrupt-names = "macirq", "eth_wake_irq";
955 reset-names = "stmmaceth";
957 snps,axi-config = <&gmac1_stmmac_axi_setup>;
958 snps,mixed-burst;
959 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
960 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
965 compatible = "snps,dwmac-mdio";
966 #address-cells = <0x1>;
967 #size-cells = <0x0>;
970 gmac1_stmmac_axi_setup: stmmac-axi-config {
976 gmac1_mtl_rx_setup: rx-queues-config {
977 snps,rx-queues-to-use = <1>;
981 gmac1_mtl_tx_setup: tx-queues-config {
982 snps,tx-queues-to-use = <1>;
988 compatible = "rockchip,rk3528-dwcmshc",
989 "rockchip,rk3588-dwcmshc";
991 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>,
993 assigned-clock-rates = <200000000>, <24000000>,
998 clock-names = "core", "bus", "axi", "block", "timer";
1000 max-frequency = <200000000>;
1001 pinctrl-names = "default";
1002 pinctrl-0 = <&emmc_bus8>, <&emmc_clk>, <&emmc_cmd>,
1007 reset-names = "core", "bus", "axi", "block", "timer";
1012 compatible = "rockchip,rk3528-dw-mshc",
1013 "rockchip,rk3288-dw-mshc";
1019 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1020 fifo-depth = <0x100>;
1022 max-frequency = <200000000>;
1023 pinctrl-names = "default";
1024 pinctrl-0 = <&sdio0_bus4>, <&sdio0_clk>, <&sdio0_cmd>;
1026 reset-names = "reset";
1031 compatible = "rockchip,rk3528-dw-mshc",
1032 "rockchip,rk3288-dw-mshc";
1038 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1039 fifo-depth = <0x100>;
1041 max-frequency = <200000000>;
1042 pinctrl-names = "default";
1043 pinctrl-0 = <&sdio1_bus4>, <&sdio1_clk>, <&sdio1_cmd>;
1045 reset-names = "reset";
1050 compatible = "rockchip,rk3528-dw-mshc",
1051 "rockchip,rk3288-dw-mshc";
1057 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1058 fifo-depth = <0x100>;
1060 max-frequency = <150000000>;
1061 pinctrl-names = "default";
1062 pinctrl-0 = <&sdmmc_bus4>, <&sdmmc_clk>, <&sdmmc_cmd>,
1065 reset-names = "reset";
1066 rockchip,default-sample-phase = <90>;
1070 dmac: dma-controller@ffd60000 {
1074 clock-names = "apb_pclk";
1084 #dma-cells = <1>;
1085 arm,pl330-periph-burst;
1090 #include "rk3528-pinctrl.dtsi"