Lines Matching full:cru
6 #include <dt-bindings/clock/rk3399-cru.h>
79 clocks = <&cru ARMCLKL>;
91 clocks = <&cru ARMCLKL>;
103 clocks = <&cru ARMCLKL>;
115 clocks = <&cru ARMCLKL>;
127 clocks = <&cru ARMCLKB>;
145 clocks = <&cru ARMCLKB>;
189 clocks = <&cru SCLK_DDRC>;
236 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
237 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
257 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
258 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
259 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
260 <&cru SRST_A_PCIE>;
277 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
278 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
283 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
284 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
285 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
286 <&cru SRST_A_PCIE>;
304 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
305 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
306 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
307 <&cru PCLK_GMAC>;
313 resets = <&cru SRST_A_GMAC>;
326 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
327 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
331 resets = <&cru SRST_SDIO0>;
342 assigned-clocks = <&cru HCLK_SD>;
344 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
345 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
349 resets = <&cru SRST_SDMMC>;
359 assigned-clocks = <&cru SCLK_EMMC>;
361 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
376 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
387 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
398 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
409 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
419 clocks = <&cru PCLK_COREDBG_L>;
427 clocks = <&cru PCLK_COREDBG_L>;
435 clocks = <&cru PCLK_COREDBG_L>;
443 clocks = <&cru PCLK_COREDBG_L>;
451 clocks = <&cru PCLK_COREDBG_B>;
459 clocks = <&cru PCLK_COREDBG_B>;
469 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
470 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
471 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
475 resets = <&cru SRST_A_USB3_OTG0>;
483 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru ACLK_USB3OTG0>,
484 <&cru SCLK_USB3OTG0_SUSPEND>;
505 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
506 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
507 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
511 resets = <&cru SRST_A_USB3_OTG1>;
519 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru ACLK_USB3OTG1>,
520 <&cru SCLK_USB3OTG1_SUSPEND>;
540 assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>;
542 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
543 <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
547 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
548 <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
609 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
611 resets = <&cru SRST_P_SARADC>;
620 clocks = <&cru HCLK_M_CRYPTO0>, <&cru HCLK_S_CRYPTO0>, <&cru SCLK_CRYPTO0>;
622 resets = <&cru SRST_CRYPTO0>, <&cru SRST_CRYPTO0_S>, <&cru SRST_CRYPTO0_M>;
630 clocks = <&cru HCLK_M_CRYPTO1>, <&cru HCLK_S_CRYPTO1>, <&cru SCLK_CRYPTO1>;
632 resets = <&cru SRST_CRYPTO1>, <&cru SRST_CRYPTO1_S>, <&cru SRST_CRYPTO1_M>;
639 assigned-clocks = <&cru SCLK_I2C1>;
641 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
654 assigned-clocks = <&cru SCLK_I2C2>;
656 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
669 assigned-clocks = <&cru SCLK_I2C3>;
671 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
684 assigned-clocks = <&cru SCLK_I2C5>;
686 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
699 assigned-clocks = <&cru SCLK_I2C6>;
701 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
714 assigned-clocks = <&cru SCLK_I2C7>;
716 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
729 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
742 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
755 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
768 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
781 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
796 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
811 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
826 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
841 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
932 assigned-clocks = <&cru SCLK_TSADC>;
934 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
936 resets = <&cru SRST_TSADC>;
1093 clocks = <&cru ACLK_IEP>,
1094 <&cru HCLK_IEP>;
1100 clocks = <&cru ACLK_RGA>,
1101 <&cru HCLK_RGA>;
1108 clocks = <&cru ACLK_VCODEC>,
1109 <&cru HCLK_VCODEC>;
1115 clocks = <&cru ACLK_VDU>,
1116 <&cru HCLK_VDU>,
1117 <&cru SCLK_VDU_CA>,
1118 <&cru SCLK_VDU_CORE>;
1127 clocks = <&cru ACLK_GPU>;
1135 clocks = <&cru PCLK_EDP_CTRL>;
1140 clocks = <&cru ACLK_EMMC>;
1146 clocks = <&cru ACLK_GMAC>,
1147 <&cru PCLK_GMAC>;
1153 clocks = <&cru HCLK_SDMMC>,
1154 <&cru SCLK_SDMMC>;
1160 clocks = <&cru HCLK_SDIO>;
1166 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1167 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1172 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1173 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1178 clocks = <&cru ACLK_USB3>;
1191 clocks = <&cru ACLK_HDCP>,
1192 <&cru HCLK_HDCP>,
1193 <&cru PCLK_HDCP>;
1199 clocks = <&cru ACLK_ISP0>,
1200 <&cru HCLK_ISP0>;
1207 clocks = <&cru ACLK_ISP1>,
1208 <&cru HCLK_ISP1>;
1221 clocks = <&cru ACLK_VOP0>,
1222 <&cru HCLK_VOP0>;
1229 clocks = <&cru ACLK_VOP1>,
1230 <&cru HCLK_VOP1>;
1365 clocks = <&cru PCLK_DDR_MON>;
1375 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1385 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1395 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,
1396 <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>;
1406 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>;
1416 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
1426 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1428 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1438 clocks = <&cru PCLK_EFUSE1024NS>;
1472 clocks = <&cru ACLK_DMAC0_PERILP>;
1483 clocks = <&cru ACLK_DMAC1_PERILP>;
1499 cru: clock-controller@ff760000 {
1500 compatible = "rockchip,rk3399-cru";
1508 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1509 <&cru PLL_NPLL>,
1510 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1511 <&cru PCLK_PERIHP>,
1512 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1513 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
1514 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
1515 <&cru ACLK_VIO>, <&cru ACLK_HDCP>,
1516 <&cru ACLK_GIC_PRE>,
1517 <&cru PCLK_DDR>,
1518 <&cru ACLK_VDU>;
1546 clocks = <&cru SCLK_MIPIDPHY_REF>,
1547 <&cru SCLK_DPHY_RX0_CFG>,
1548 <&cru PCLK_VIO_GRF>;
1558 clocks = <&cru SCLK_USB2PHY0_REF>;
1585 clocks = <&cru SCLK_USB2PHY1_REF>;
1621 clocks = <&cru SCLK_PCIEPHY_REF>;
1624 resets = <&cru SRST_PCIEPHY>;
1633 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1634 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1636 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1639 resets = <&cru SRST_UPHY0>,
1640 <&cru SRST_UPHY0_PIPE_L00>,
1641 <&cru SRST_P_UPHY0_TCPHY>;
1658 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1659 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1661 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1664 resets = <&cru SRST_UPHY1>,
1665 <&cru SRST_UPHY1_PIPE_L00>,
1666 <&cru SRST_P_UPHY1_TCPHY>;
1683 clocks = <&cru PCLK_WDT>;
1691 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1702 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1718 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1734 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1749 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1759 assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1761 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1765 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1804 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1815 assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1817 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1821 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1860 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1871 clocks = <&cru SCLK_ISP0>,
1872 <&cru ACLK_ISP0_WRAPPER>,
1873 <&cru HCLK_ISP0_WRAPPER>;
1897 clocks = <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>;
1908 clocks = <&cru SCLK_ISP1>,
1909 <&cru ACLK_ISP1_WRAPPER>,
1910 <&cru HCLK_ISP1_WRAPPER>;
1934 clocks = <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>;
1960 clocks = <&cru PCLK_HDMI_CTRL>,
1961 <&cru SCLK_HDMI_SFR>,
1962 <&cru SCLK_HDMI_CEC>,
1963 <&cru PCLK_VIO_GRF>,
1964 <&cru PLL_VPLL>;
1993 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>,
1994 <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>;
1997 resets = <&cru SRST_P_MIPI_DSI0>;
2034 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>,
2035 <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>;
2038 resets = <&cru SRST_P_MIPI_DSI1>;
2076 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>;
2081 resets = <&cru SRST_P_EDP_CTRL>;
2119 clocks = <&cru ACLK_GPU>;
2163 clocks = <&cru PCLK_GPIO2>;
2176 clocks = <&cru PCLK_GPIO3>;
2189 clocks = <&cru PCLK_GPIO4>;