Lines Matching +full:bus +full:- +full:dmc
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3399-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3399-power.h>
12 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
44 #address-cells = <2>;
45 #size-cells = <0>;
47 cpu-map {
75 compatible = "arm,cortex-a53";
77 enable-method = "psci";
78 capacity-dmips-mhz = <485>;
80 #cooling-cells = <2>; /* min followed by max */
81 dynamic-power-coefficient = <100>;
82 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
87 compatible = "arm,cortex-a53";
89 enable-method = "psci";
90 capacity-dmips-mhz = <485>;
92 #cooling-cells = <2>; /* min followed by max */
93 dynamic-power-coefficient = <100>;
94 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
99 compatible = "arm,cortex-a53";
101 enable-method = "psci";
102 capacity-dmips-mhz = <485>;
104 #cooling-cells = <2>; /* min followed by max */
105 dynamic-power-coefficient = <100>;
106 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
111 compatible = "arm,cortex-a53";
113 enable-method = "psci";
114 capacity-dmips-mhz = <485>;
116 #cooling-cells = <2>; /* min followed by max */
117 dynamic-power-coefficient = <100>;
118 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
123 compatible = "arm,cortex-a72";
125 enable-method = "psci";
126 capacity-dmips-mhz = <1024>;
128 #cooling-cells = <2>; /* min followed by max */
129 dynamic-power-coefficient = <436>;
130 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
132 thermal-idle {
133 #cooling-cells = <2>;
134 duration-us = <10000>;
135 exit-latency-us = <500>;
141 compatible = "arm,cortex-a72";
143 enable-method = "psci";
144 capacity-dmips-mhz = <1024>;
146 #cooling-cells = <2>; /* min followed by max */
147 dynamic-power-coefficient = <436>;
148 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
150 thermal-idle {
151 #cooling-cells = <2>;
152 duration-us = <10000>;
153 exit-latency-us = <500>;
157 idle-states {
158 entry-method = "psci";
160 CPU_SLEEP: cpu-sleep {
161 compatible = "arm,idle-state";
162 local-timer-stop;
163 arm,psci-suspend-param = <0x0010000>;
164 entry-latency-us = <120>;
165 exit-latency-us = <250>;
166 min-residency-us = <900>;
169 CLUSTER_SLEEP: cluster-sleep {
170 compatible = "arm,idle-state";
171 local-timer-stop;
172 arm,psci-suspend-param = <0x1010000>;
173 entry-latency-us = <400>;
174 exit-latency-us = <500>;
175 min-residency-us = <2000>;
180 display-subsystem {
181 compatible = "rockchip,display-subsystem";
185 dmc: memory-controller {
186 compatible = "rockchip,rk3399-dmc";
188 devfreq-events = <&dfi>;
190 clock-names = "dmc_clk";
195 compatible = "arm,cortex-a53-pmu";
200 compatible = "arm,cortex-a72-pmu";
205 compatible = "arm,psci-1.0";
210 compatible = "arm,armv8-timer";
215 arm,no-tick-in-suspend;
219 compatible = "fixed-clock";
220 clock-frequency = <24000000>;
221 clock-output-names = "xin24m";
222 #clock-cells = <0>;
226 compatible = "rockchip,rk3399-pcie";
229 reg-names = "axi-base", "apb-base";
231 #address-cells = <3>;
232 #size-cells = <2>;
233 #interrupt-cells = <1>;
234 aspm-no-l0s;
235 bus-range = <0x0 0x1f>;
238 clock-names = "aclk", "aclk-perf",
243 interrupt-names = "sys", "legacy", "client";
244 interrupt-map-mask = <0 0 0 7>;
245 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
249 max-link-speed = <1>;
250 msi-map = <0x0 &its 0x0 0x1000>;
253 phy-names = "pcie-phy-0", "pcie-phy-1",
254 "pcie-phy-2", "pcie-phy-3";
261 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
265 pcie0_intc: interrupt-controller {
266 interrupt-controller;
267 #address-cells = <0>;
268 #interrupt-cells = <1>;
272 pcie0_ep: pcie-ep@f8000000 {
273 compatible = "rockchip,rk3399-pcie-ep";
276 reg-names = "apb-base", "mem-base";
279 clock-names = "aclk", "aclk-perf",
281 max-functions = /bits/ 8 <8>;
282 num-lanes = <4>;
287 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
291 phy-names = "pcie-phy-0", "pcie-phy-1",
292 "pcie-phy-2", "pcie-phy-3";
293 rockchip,max-outbound-regions = <32>;
294 pinctrl-names = "default";
295 pinctrl-0 = <&pcie_clkreqnb_cpm>;
300 compatible = "rockchip,rk3399-gmac";
303 interrupt-names = "macirq";
308 clock-names = "stmmaceth", "mac_clk_rx",
312 power-domains = <&power RK3399_PD_GMAC>;
314 reset-names = "stmmaceth";
321 compatible = "rockchip,rk3399-dw-mshc",
322 "rockchip,rk3288-dw-mshc";
325 max-frequency = <150000000>;
328 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
329 fifo-depth = <0x100>;
330 power-domains = <&power RK3399_PD_SDIOAUDIO>;
332 reset-names = "reset";
337 compatible = "rockchip,rk3399-dw-mshc",
338 "rockchip,rk3288-dw-mshc";
341 max-frequency = <150000000>;
342 assigned-clocks = <&cru HCLK_SD>;
343 assigned-clock-rates = <200000000>;
346 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
347 fifo-depth = <0x100>;
348 power-domains = <&power RK3399_PD_SD>;
350 reset-names = "reset";
355 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
358 arasan,soc-ctl-syscon = <&grf>;
359 assigned-clocks = <&cru SCLK_EMMC>;
360 assigned-clock-rates = <200000000>;
362 clock-names = "clk_xin", "clk_ahb";
363 clock-output-names = "emmc_cardclock";
364 #clock-cells = <0>;
366 phy-names = "phy_arasan";
367 power-domains = <&power RK3399_PD_EMMC>;
368 disable-cqe-dcmd;
373 compatible = "generic-ehci";
379 phy-names = "usb";
384 compatible = "generic-ohci";
390 phy-names = "usb";
395 compatible = "generic-ehci";
401 phy-names = "usb";
406 compatible = "generic-ohci";
412 phy-names = "usb";
417 compatible = "arm,coresight-cpu-debug", "arm,primecell";
420 clock-names = "apb_pclk";
425 compatible = "arm,coresight-cpu-debug", "arm,primecell";
428 clock-names = "apb_pclk";
433 compatible = "arm,coresight-cpu-debug", "arm,primecell";
436 clock-names = "apb_pclk";
441 compatible = "arm,coresight-cpu-debug", "arm,primecell";
444 clock-names = "apb_pclk";
449 compatible = "arm,coresight-cpu-debug", "arm,primecell";
452 clock-names = "apb_pclk";
457 compatible = "arm,coresight-cpu-debug", "arm,primecell";
460 clock-names = "apb_pclk";
465 compatible = "rockchip,rk3399-dwc3";
466 #address-cells = <2>;
467 #size-cells = <2>;
472 clock-names = "ref_clk", "suspend_clk",
476 reset-names = "usb3-otg";
485 clock-names = "ref", "bus_early", "suspend";
488 phy-names = "usb2-phy", "usb3-phy";
491 snps,dis-u2-freeclk-exists-quirk;
493 snps,dis-del-phy-power-chg-quirk;
494 snps,dis-tx-ipgap-linecheck-quirk;
495 power-domains = <&power RK3399_PD_USB3>;
501 compatible = "rockchip,rk3399-dwc3";
502 #address-cells = <2>;
503 #size-cells = <2>;
508 clock-names = "ref_clk", "suspend_clk",
512 reset-names = "usb3-otg";
521 clock-names = "ref", "bus_early", "suspend";
524 phy-names = "usb2-phy", "usb3-phy";
527 snps,dis-u2-freeclk-exists-quirk;
529 snps,dis-del-phy-power-chg-quirk;
530 snps,dis-tx-ipgap-linecheck-quirk;
531 power-domains = <&power RK3399_PD_USB3>;
537 compatible = "rockchip,rk3399-cdn-dp";
540 assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>;
541 assigned-clock-rates = <100000000>, <200000000>;
544 clock-names = "core-clk", "pclk", "spdif", "grf";
546 power-domains = <&power RK3399_PD_HDCP>;
549 reset-names = "spdif", "dptx", "apb", "core";
551 #sound-dai-cells = <1>;
556 #address-cells = <1>;
557 #size-cells = <0>;
561 remote-endpoint = <&vopb_out_dp>;
566 remote-endpoint = <&vopl_out_dp>;
572 gic: interrupt-controller@fee00000 {
573 compatible = "arm,gic-v3";
574 #interrupt-cells = <4>;
575 #address-cells = <2>;
576 #size-cells = <2>;
578 interrupt-controller;
586 its: msi-controller@fee20000 {
587 compatible = "arm,gic-v3-its";
588 msi-controller;
589 #msi-cells = <1>;
593 ppi-partitions {
594 ppi_cluster0: interrupt-partition-0 {
598 ppi_cluster1: interrupt-partition-1 {
605 compatible = "rockchip,rk3399-saradc";
608 #io-channel-cells = <1>;
610 clock-names = "saradc", "apb_pclk";
612 reset-names = "saradc-apb";
617 compatible = "rockchip,rk3399-crypto";
621 clock-names = "hclk_master", "hclk_slave", "sclk";
623 reset-names = "master", "slave", "crypto-rst";
627 compatible = "rockchip,rk3399-crypto";
631 clock-names = "hclk_master", "hclk_slave", "sclk";
633 reset-names = "master", "slave", "crypto-rst";
637 compatible = "rockchip,rk3399-i2c";
639 assigned-clocks = <&cru SCLK_I2C1>;
640 assigned-clock-rates = <200000000>;
642 clock-names = "i2c", "pclk";
644 pinctrl-names = "default";
645 pinctrl-0 = <&i2c1_xfer>;
646 #address-cells = <1>;
647 #size-cells = <0>;
652 compatible = "rockchip,rk3399-i2c";
654 assigned-clocks = <&cru SCLK_I2C2>;
655 assigned-clock-rates = <200000000>;
657 clock-names = "i2c", "pclk";
659 pinctrl-names = "default";
660 pinctrl-0 = <&i2c2_xfer>;
661 #address-cells = <1>;
662 #size-cells = <0>;
667 compatible = "rockchip,rk3399-i2c";
669 assigned-clocks = <&cru SCLK_I2C3>;
670 assigned-clock-rates = <200000000>;
672 clock-names = "i2c", "pclk";
674 pinctrl-names = "default";
675 pinctrl-0 = <&i2c3_xfer>;
676 #address-cells = <1>;
677 #size-cells = <0>;
682 compatible = "rockchip,rk3399-i2c";
684 assigned-clocks = <&cru SCLK_I2C5>;
685 assigned-clock-rates = <200000000>;
687 clock-names = "i2c", "pclk";
689 pinctrl-names = "default";
690 pinctrl-0 = <&i2c5_xfer>;
691 #address-cells = <1>;
692 #size-cells = <0>;
697 compatible = "rockchip,rk3399-i2c";
699 assigned-clocks = <&cru SCLK_I2C6>;
700 assigned-clock-rates = <200000000>;
702 clock-names = "i2c", "pclk";
704 pinctrl-names = "default";
705 pinctrl-0 = <&i2c6_xfer>;
706 #address-cells = <1>;
707 #size-cells = <0>;
712 compatible = "rockchip,rk3399-i2c";
714 assigned-clocks = <&cru SCLK_I2C7>;
715 assigned-clock-rates = <200000000>;
717 clock-names = "i2c", "pclk";
719 pinctrl-names = "default";
720 pinctrl-0 = <&i2c7_xfer>;
721 #address-cells = <1>;
722 #size-cells = <0>;
727 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
730 clock-names = "baudclk", "apb_pclk";
732 reg-shift = <2>;
733 reg-io-width = <4>;
734 pinctrl-names = "default";
735 pinctrl-0 = <&uart0_xfer>;
740 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
743 clock-names = "baudclk", "apb_pclk";
745 reg-shift = <2>;
746 reg-io-width = <4>;
747 pinctrl-names = "default";
748 pinctrl-0 = <&uart1_xfer>;
753 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
756 clock-names = "baudclk", "apb_pclk";
758 reg-shift = <2>;
759 reg-io-width = <4>;
760 pinctrl-names = "default";
761 pinctrl-0 = <&uart2c_xfer>;
766 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
769 clock-names = "baudclk", "apb_pclk";
771 reg-shift = <2>;
772 reg-io-width = <4>;
773 pinctrl-names = "default";
774 pinctrl-0 = <&uart3_xfer>;
779 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
782 clock-names = "spiclk", "apb_pclk";
785 dma-names = "tx", "rx";
786 pinctrl-names = "default";
787 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
788 #address-cells = <1>;
789 #size-cells = <0>;
794 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
797 clock-names = "spiclk", "apb_pclk";
800 dma-names = "tx", "rx";
801 pinctrl-names = "default";
802 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
803 #address-cells = <1>;
804 #size-cells = <0>;
809 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
812 clock-names = "spiclk", "apb_pclk";
815 dma-names = "tx", "rx";
816 pinctrl-names = "default";
817 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
818 #address-cells = <1>;
819 #size-cells = <0>;
824 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
827 clock-names = "spiclk", "apb_pclk";
830 dma-names = "tx", "rx";
831 pinctrl-names = "default";
832 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
833 #address-cells = <1>;
834 #size-cells = <0>;
839 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
842 clock-names = "spiclk", "apb_pclk";
845 dma-names = "tx", "rx";
846 pinctrl-names = "default";
847 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
848 power-domains = <&power RK3399_PD_SDIOAUDIO>;
849 #address-cells = <1>;
850 #size-cells = <0>;
854 thermal_zones: thermal-zones {
855 cpu_thermal: cpu-thermal {
856 polling-delay-passive = <100>;
857 polling-delay = <1000>;
859 thermal-sensors = <&tsadc 0>;
879 cooling-maps {
882 cooling-device =
888 cooling-device =
899 gpu_thermal: gpu-thermal {
900 polling-delay-passive = <100>;
901 polling-delay = <1000>;
903 thermal-sensors = <&tsadc 1>;
918 cooling-maps {
921 cooling-device =
929 compatible = "rockchip,rk3399-tsadc";
932 assigned-clocks = <&cru SCLK_TSADC>;
933 assigned-clock-rates = <750000>;
935 clock-names = "tsadc", "apb_pclk";
937 reset-names = "tsadc-apb";
939 rockchip,hw-tshut-temp = <95000>;
940 pinctrl-names = "init", "default", "sleep";
941 pinctrl-0 = <&otp_pin>;
942 pinctrl-1 = <&otp_out>;
943 pinctrl-2 = <&otp_pin>;
944 #thermal-sensor-cells = <1>;
949 compatible = "rockchip,rk3399-qos", "syscon";
954 compatible = "rockchip,rk3399-qos", "syscon";
959 compatible = "rockchip,rk3399-qos", "syscon";
964 compatible = "rockchip,rk3399-qos", "syscon";
969 compatible = "rockchip,rk3399-qos", "syscon";
974 compatible = "rockchip,rk3399-qos", "syscon";
979 compatible = "rockchip,rk3399-qos", "syscon";
984 compatible = "rockchip,rk3399-qos", "syscon";
989 compatible = "rockchip,rk3399-qos", "syscon";
994 compatible = "rockchip,rk3399-qos", "syscon";
999 compatible = "rockchip,rk3399-qos", "syscon";
1004 compatible = "rockchip,rk3399-qos", "syscon";
1009 compatible = "rockchip,rk3399-qos", "syscon";
1014 compatible = "rockchip,rk3399-qos", "syscon";
1019 compatible = "rockchip,rk3399-qos", "syscon";
1024 compatible = "rockchip,rk3399-qos", "syscon";
1029 compatible = "rockchip,rk3399-qos", "syscon";
1034 compatible = "rockchip,rk3399-qos", "syscon";
1039 compatible = "rockchip,rk3399-qos", "syscon";
1044 compatible = "rockchip,rk3399-qos", "syscon";
1049 compatible = "rockchip,rk3399-qos", "syscon";
1054 compatible = "rockchip,rk3399-qos", "syscon";
1059 compatible = "rockchip,rk3399-qos", "syscon";
1064 compatible = "rockchip,rk3399-qos", "syscon";
1069 compatible = "rockchip,rk3399-qos", "syscon";
1073 pmu: power-management@ff310000 {
1074 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
1084 power: power-controller {
1085 compatible = "rockchip,rk3399-power-controller";
1086 #power-domain-cells = <1>;
1087 #address-cells = <1>;
1088 #size-cells = <0>;
1091 power-domain@RK3399_PD_IEP {
1096 #power-domain-cells = <0>;
1098 power-domain@RK3399_PD_RGA {
1104 #power-domain-cells = <0>;
1106 power-domain@RK3399_PD_VCODEC {
1111 #power-domain-cells = <0>;
1113 power-domain@RK3399_PD_VDU {
1121 #power-domain-cells = <0>;
1125 power-domain@RK3399_PD_GPU {
1129 #power-domain-cells = <0>;
1133 power-domain@RK3399_PD_EDP {
1136 #power-domain-cells = <0>;
1138 power-domain@RK3399_PD_EMMC {
1142 #power-domain-cells = <0>;
1144 power-domain@RK3399_PD_GMAC {
1149 #power-domain-cells = <0>;
1151 power-domain@RK3399_PD_SD {
1156 #power-domain-cells = <0>;
1158 power-domain@RK3399_PD_SDIOAUDIO {
1162 #power-domain-cells = <0>;
1164 power-domain@RK3399_PD_TCPD0 {
1168 #power-domain-cells = <0>;
1170 power-domain@RK3399_PD_TCPD1 {
1174 #power-domain-cells = <0>;
1176 power-domain@RK3399_PD_USB3 {
1181 #power-domain-cells = <0>;
1183 power-domain@RK3399_PD_VIO {
1185 #power-domain-cells = <1>;
1186 #address-cells = <1>;
1187 #size-cells = <0>;
1189 power-domain@RK3399_PD_HDCP {
1195 #power-domain-cells = <0>;
1197 power-domain@RK3399_PD_ISP0 {
1203 #power-domain-cells = <0>;
1205 power-domain@RK3399_PD_ISP1 {
1211 #power-domain-cells = <0>;
1213 power-domain@RK3399_PD_VO {
1215 #power-domain-cells = <1>;
1216 #address-cells = <1>;
1217 #size-cells = <0>;
1219 power-domain@RK3399_PD_VOPB {
1225 #power-domain-cells = <0>;
1227 power-domain@RK3399_PD_VOPL {
1232 #power-domain-cells = <0>;
1240 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1243 pmu_io_domains: io-domains {
1244 compatible = "rockchip,rk3399-pmu-io-voltage-domain";
1250 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1253 clock-names = "spiclk", "apb_pclk";
1255 pinctrl-names = "default";
1256 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1257 #address-cells = <1>;
1258 #size-cells = <0>;
1263 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1266 clock-names = "baudclk", "apb_pclk";
1268 reg-shift = <2>;
1269 reg-io-width = <4>;
1270 pinctrl-names = "default";
1271 pinctrl-0 = <&uart4_xfer>;
1276 compatible = "rockchip,rk3399-i2c";
1278 assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
1279 assigned-clock-rates = <200000000>;
1281 clock-names = "i2c", "pclk";
1283 pinctrl-names = "default";
1284 pinctrl-0 = <&i2c0_xfer>;
1285 #address-cells = <1>;
1286 #size-cells = <0>;
1291 compatible = "rockchip,rk3399-i2c";
1293 assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
1294 assigned-clock-rates = <200000000>;
1296 clock-names = "i2c", "pclk";
1298 pinctrl-names = "default";
1299 pinctrl-0 = <&i2c4_xfer>;
1300 #address-cells = <1>;
1301 #size-cells = <0>;
1306 compatible = "rockchip,rk3399-i2c";
1308 assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
1309 assigned-clock-rates = <200000000>;
1311 clock-names = "i2c", "pclk";
1313 pinctrl-names = "default";
1314 pinctrl-0 = <&i2c8_xfer>;
1315 #address-cells = <1>;
1316 #size-cells = <0>;
1321 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1323 #pwm-cells = <3>;
1324 pinctrl-names = "default";
1325 pinctrl-0 = <&pwm0_pin>;
1331 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1333 #pwm-cells = <3>;
1334 pinctrl-names = "default";
1335 pinctrl-0 = <&pwm1_pin>;
1341 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1343 #pwm-cells = <3>;
1344 pinctrl-names = "default";
1345 pinctrl-0 = <&pwm2_pin>;
1351 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1353 #pwm-cells = <3>;
1354 pinctrl-names = "default";
1355 pinctrl-0 = <&pwm3a_pin>;
1362 compatible = "rockchip,rk3399-dfi";
1366 clock-names = "pclk_ddr_mon";
1369 vpu: video-codec@ff650000 {
1370 compatible = "rockchip,rk3399-vpu";
1374 interrupt-names = "vepu", "vdpu";
1376 clock-names = "aclk", "hclk";
1378 power-domains = <&power RK3399_PD_VCODEC>;
1386 clock-names = "aclk", "iface";
1387 #iommu-cells = <0>;
1388 power-domains = <&power RK3399_PD_VCODEC>;
1391 vdec: video-codec@ff660000 {
1392 compatible = "rockchip,rk3399-vdec";
1397 clock-names = "axi", "ahb", "cabac", "core";
1399 power-domains = <&power RK3399_PD_VDU>;
1407 clock-names = "aclk", "iface";
1408 power-domains = <&power RK3399_PD_VDU>;
1409 #iommu-cells = <0>;
1417 clock-names = "aclk", "iface";
1418 #iommu-cells = <0>;
1423 compatible = "rockchip,rk3399-rga";
1427 clock-names = "aclk", "hclk", "sclk";
1429 reset-names = "core", "axi", "ahb";
1430 power-domains = <&power RK3399_PD_RGA>;
1434 compatible = "rockchip,rk3399-efuse";
1436 #address-cells = <1>;
1437 #size-cells = <1>;
1439 clock-names = "pclk_efuse";
1442 cpu_id: cpu-id@7 {
1445 cpub_leakage: cpu-leakage@17 {
1448 gpu_leakage: gpu-leakage@18 {
1451 center_leakage: center-leakage@19 {
1454 cpul_leakage: cpu-leakage@1a {
1457 logic_leakage: logic-leakage@1b {
1460 wafer_info: wafer-info@1c {
1465 dmac_bus: dma-controller@ff6d0000 {
1470 #dma-cells = <1>;
1471 arm,pl330-periph-burst;
1473 clock-names = "apb_pclk";
1476 dmac_peri: dma-controller@ff6e0000 {
1481 #dma-cells = <1>;
1482 arm,pl330-periph-burst;
1484 clock-names = "apb_pclk";
1487 pmucru: clock-controller@ff750000 {
1488 compatible = "rockchip,rk3399-pmucru";
1491 clock-names = "xin24m";
1493 #clock-cells = <1>;
1494 #reset-cells = <1>;
1495 assigned-clocks = <&pmucru PLL_PPLL>;
1496 assigned-clock-rates = <676000000>;
1499 cru: clock-controller@ff760000 {
1500 compatible = "rockchip,rk3399-cru";
1503 clock-names = "xin24m";
1505 #clock-cells = <1>;
1506 #reset-cells = <1>;
1507 assigned-clocks =
1519 assigned-clock-rates =
1534 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1536 #address-cells = <1>;
1537 #size-cells = <1>;
1539 io_domains: io-domains {
1540 compatible = "rockchip,rk3399-io-voltage-domain";
1544 mipi_dphy_rx0: mipi-dphy-rx0 {
1545 compatible = "rockchip,rk3399-mipi-dphy-rx0";
1549 clock-names = "dphy-ref", "dphy-cfg", "grf";
1550 power-domains = <&power RK3399_PD_VIO>;
1551 #phy-cells = <0>;
1556 compatible = "rockchip,rk3399-usb2phy";
1559 clock-names = "phyclk";
1560 #clock-cells = <0>;
1561 clock-output-names = "clk_usbphy0_480m";
1564 u2phy0_host: host-port {
1565 #phy-cells = <0>;
1567 interrupt-names = "linestate";
1571 u2phy0_otg: otg-port {
1572 #phy-cells = <0>;
1576 interrupt-names = "otg-bvalid", "otg-id",
1583 compatible = "rockchip,rk3399-usb2phy";
1586 clock-names = "phyclk";
1587 #clock-cells = <0>;
1588 clock-output-names = "clk_usbphy1_480m";
1591 u2phy1_host: host-port {
1592 #phy-cells = <0>;
1594 interrupt-names = "linestate";
1598 u2phy1_otg: otg-port {
1599 #phy-cells = <0>;
1603 interrupt-names = "otg-bvalid", "otg-id",
1610 compatible = "rockchip,rk3399-emmc-phy";
1613 clock-names = "emmcclk";
1614 drive-impedance-ohm = <50>;
1615 #phy-cells = <0>;
1619 pcie_phy: pcie-phy {
1620 compatible = "rockchip,rk3399-pcie-phy";
1622 clock-names = "refclk";
1623 #phy-cells = <1>;
1625 reset-names = "phy";
1631 compatible = "rockchip,rk3399-typec-phy";
1635 clock-names = "tcpdcore", "tcpdphy-ref";
1636 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1637 assigned-clock-rates = <50000000>;
1638 power-domains = <&power RK3399_PD_TCPD0>;
1642 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1646 tcphy0_dp: dp-port {
1647 #phy-cells = <0>;
1650 tcphy0_usb3: usb3-port {
1651 #phy-cells = <0>;
1656 compatible = "rockchip,rk3399-typec-phy";
1660 clock-names = "tcpdcore", "tcpdphy-ref";
1661 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1662 assigned-clock-rates = <50000000>;
1663 power-domains = <&power RK3399_PD_TCPD1>;
1667 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1671 tcphy1_dp: dp-port {
1672 #phy-cells = <0>;
1675 tcphy1_usb3: usb3-port {
1676 #phy-cells = <0>;
1681 compatible = "rockchip,rk3399-wdt", "snps,dw-wdt";
1688 compatible = "rockchip,rk3399-timer";
1692 clock-names = "pclk", "timer";
1696 compatible = "rockchip,rk3399-spdif";
1700 dma-names = "tx";
1701 clock-names = "mclk", "hclk";
1703 pinctrl-names = "default";
1704 pinctrl-0 = <&spdif_bus>;
1705 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1706 #sound-dai-cells = <0>;
1711 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1716 dma-names = "tx", "rx";
1717 clock-names = "i2s_clk", "i2s_hclk";
1719 pinctrl-names = "bclk_on", "bclk_off";
1720 pinctrl-0 = <&i2s0_8ch_bus>;
1721 pinctrl-1 = <&i2s0_8ch_bus_bclk_off>;
1722 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1723 #sound-dai-cells = <0>;
1728 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1732 dma-names = "tx", "rx";
1733 clock-names = "i2s_clk", "i2s_hclk";
1735 pinctrl-names = "default";
1736 pinctrl-0 = <&i2s1_2ch_bus>;
1737 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1738 #sound-dai-cells = <0>;
1743 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1747 dma-names = "tx", "rx";
1748 clock-names = "i2s_clk", "i2s_hclk";
1750 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1751 #sound-dai-cells = <0>;
1756 compatible = "rockchip,rk3399-vop-lit";
1759 assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1760 assigned-clock-rates = <400000000>, <100000000>;
1762 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1764 power-domains = <&power RK3399_PD_VOPL>;
1766 reset-names = "axi", "ahb", "dclk";
1770 #address-cells = <1>;
1771 #size-cells = <0>;
1775 remote-endpoint = <&mipi_in_vopl>;
1780 remote-endpoint = <&edp_in_vopl>;
1785 remote-endpoint = <&hdmi_in_vopl>;
1790 remote-endpoint = <&mipi1_in_vopl>;
1795 remote-endpoint = <&dp_in_vopl>;
1805 clock-names = "aclk", "iface";
1806 power-domains = <&power RK3399_PD_VOPL>;
1807 #iommu-cells = <0>;
1812 compatible = "rockchip,rk3399-vop-big";
1815 assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1816 assigned-clock-rates = <400000000>, <100000000>;
1818 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1820 power-domains = <&power RK3399_PD_VOPB>;
1822 reset-names = "axi", "ahb", "dclk";
1826 #address-cells = <1>;
1827 #size-cells = <0>;
1831 remote-endpoint = <&edp_in_vopb>;
1836 remote-endpoint = <&mipi_in_vopb>;
1841 remote-endpoint = <&hdmi_in_vopb>;
1846 remote-endpoint = <&mipi1_in_vopb>;
1851 remote-endpoint = <&dp_in_vopb>;
1861 clock-names = "aclk", "iface";
1862 power-domains = <&power RK3399_PD_VOPB>;
1863 #iommu-cells = <0>;
1868 compatible = "rockchip,rk3399-cif-isp";
1874 clock-names = "isp", "aclk", "hclk";
1877 phy-names = "dphy";
1878 power-domains = <&power RK3399_PD_ISP0>;
1882 #address-cells = <1>;
1883 #size-cells = <0>;
1887 #address-cells = <1>;
1888 #size-cells = <0>;
1898 clock-names = "aclk", "iface";
1899 #iommu-cells = <0>;
1900 power-domains = <&power RK3399_PD_ISP0>;
1901 rockchip,disable-mmu-reset;
1905 compatible = "rockchip,rk3399-cif-isp";
1911 clock-names = "isp", "aclk", "hclk";
1914 phy-names = "dphy";
1915 power-domains = <&power RK3399_PD_ISP1>;
1919 #address-cells = <1>;
1920 #size-cells = <0>;
1924 #address-cells = <1>;
1925 #size-cells = <0>;
1935 clock-names = "aclk", "iface";
1936 #iommu-cells = <0>;
1937 power-domains = <&power RK3399_PD_ISP1>;
1938 rockchip,disable-mmu-reset;
1941 hdmi_sound: hdmi-sound {
1942 compatible = "simple-audio-card";
1943 simple-audio-card,format = "i2s";
1944 simple-audio-card,mclk-fs = <256>;
1945 simple-audio-card,name = "hdmi-sound";
1948 simple-audio-card,cpu {
1949 sound-dai = <&i2s2>;
1951 simple-audio-card,codec {
1952 sound-dai = <&hdmi>;
1957 compatible = "rockchip,rk3399-dw-hdmi";
1965 clock-names = "iahb", "isfr", "cec", "grf", "ref";
1966 power-domains = <&power RK3399_PD_HDCP>;
1967 reg-io-width = <4>;
1969 #sound-dai-cells = <0>;
1974 #address-cells = <1>;
1975 #size-cells = <0>;
1979 remote-endpoint = <&vopb_out_hdmi>;
1983 remote-endpoint = <&vopl_out_hdmi>;
1990 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1995 clock-names = "ref", "pclk", "phy_cfg", "grf";
1996 power-domains = <&power RK3399_PD_VIO>;
1998 reset-names = "apb";
2000 #address-cells = <1>;
2001 #size-cells = <0>;
2005 #address-cells = <1>;
2006 #size-cells = <0>;
2010 #address-cells = <1>;
2011 #size-cells = <0>;
2015 remote-endpoint = <&vopb_out_mipi>;
2020 remote-endpoint = <&vopl_out_mipi>;
2031 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
2036 clock-names = "ref", "pclk", "phy_cfg", "grf";
2037 power-domains = <&power RK3399_PD_VIO>;
2039 reset-names = "apb";
2041 #address-cells = <1>;
2042 #size-cells = <0>;
2043 #phy-cells = <0>;
2047 #address-cells = <1>;
2048 #size-cells = <0>;
2052 #address-cells = <1>;
2053 #size-cells = <0>;
2057 remote-endpoint = <&vopb_out_mipi1>;
2062 remote-endpoint = <&vopl_out_mipi1>;
2073 compatible = "rockchip,rk3399-edp";
2077 clock-names = "dp", "pclk", "grf";
2078 pinctrl-names = "default";
2079 pinctrl-0 = <&edp_hpd>;
2080 power-domains = <&power RK3399_PD_EDP>;
2082 reset-names = "dp";
2087 #address-cells = <1>;
2088 #size-cells = <0>;
2092 #address-cells = <1>;
2093 #size-cells = <0>;
2097 remote-endpoint = <&vopb_out_edp>;
2102 remote-endpoint = <&vopl_out_edp>;
2113 compatible = "rockchip,rk3399-mali", "arm,mali-t860";
2118 interrupt-names = "job", "mmu", "gpu";
2120 #cooling-cells = <2>;
2121 dynamic-power-coefficient = <2640>;
2122 power-domains = <&power RK3399_PD_GPU>;
2127 compatible = "rockchip,rk3399-pinctrl";
2130 #address-cells = <2>;
2131 #size-cells = <2>;
2135 compatible = "rockchip,gpio-bank";
2140 gpio-controller;
2141 #gpio-cells = <0x2>;
2143 interrupt-controller;
2144 #interrupt-cells = <0x2>;
2148 compatible = "rockchip,gpio-bank";
2153 gpio-controller;
2154 #gpio-cells = <0x2>;
2156 interrupt-controller;
2157 #interrupt-cells = <0x2>;
2161 compatible = "rockchip,gpio-bank";
2166 gpio-controller;
2167 #gpio-cells = <0x2>;
2169 interrupt-controller;
2170 #interrupt-cells = <0x2>;
2174 compatible = "rockchip,gpio-bank";
2179 gpio-controller;
2180 #gpio-cells = <0x2>;
2182 interrupt-controller;
2183 #interrupt-cells = <0x2>;
2187 compatible = "rockchip,gpio-bank";
2192 gpio-controller;
2193 #gpio-cells = <0x2>;
2195 interrupt-controller;
2196 #interrupt-cells = <0x2>;
2199 pcfg_pull_up: pcfg-pull-up {
2200 bias-pull-up;
2203 pcfg_pull_down: pcfg-pull-down {
2204 bias-pull-down;
2207 pcfg_pull_none: pcfg-pull-none {
2208 bias-disable;
2211 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
2212 bias-disable;
2213 drive-strength = <12>;
2216 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
2217 bias-disable;
2218 drive-strength = <13>;
2221 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
2222 bias-disable;
2223 drive-strength = <18>;
2226 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
2227 bias-disable;
2228 drive-strength = <20>;
2231 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
2232 bias-pull-up;
2233 drive-strength = <2>;
2236 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
2237 bias-pull-up;
2238 drive-strength = <8>;
2241 pcfg_pull_up_18ma: pcfg-pull-up-18ma {
2242 bias-pull-up;
2243 drive-strength = <18>;
2246 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
2247 bias-pull-up;
2248 drive-strength = <20>;
2251 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
2252 bias-pull-down;
2253 drive-strength = <4>;
2256 pcfg_pull_down_8ma: pcfg-pull-down-8ma {
2257 bias-pull-down;
2258 drive-strength = <8>;
2261 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
2262 bias-pull-down;
2263 drive-strength = <12>;
2266 pcfg_pull_down_18ma: pcfg-pull-down-18ma {
2267 bias-pull-down;
2268 drive-strength = <18>;
2271 pcfg_pull_down_20ma: pcfg-pull-down-20ma {
2272 bias-pull-down;
2273 drive-strength = <20>;
2276 pcfg_output_high: pcfg-output-high {
2277 output-high;
2280 pcfg_output_low: pcfg-output-low {
2281 output-low;
2284 pcfg_input_enable: pcfg-input-enable {
2285 input-enable;
2288 pcfg_input_pull_up: pcfg-input-pull-up {
2289 input-enable;
2290 bias-pull-up;
2293 pcfg_input_pull_down: pcfg-input-pull-down {
2294 input-enable;
2295 bias-pull-down;
2299 clk_32k: clk-32k {
2305 cif_clkin: cif-clkin {
2310 cif_clkouta: cif-clkouta {
2317 edp_hpd: edp-hpd {
2324 rgmii_pins: rgmii-pins {
2358 rmii_pins: rmii-pins {
2384 i2c0_xfer: i2c0-xfer {
2392 i2c1_xfer: i2c1-xfer {
2400 i2c2_xfer: i2c2-xfer {
2408 i2c3_xfer: i2c3-xfer {
2416 i2c4_xfer: i2c4-xfer {
2424 i2c5_xfer: i2c5-xfer {
2432 i2c6_xfer: i2c6-xfer {
2440 i2c7_xfer: i2c7-xfer {
2448 i2c8_xfer: i2c8-xfer {
2456 i2s0_2ch_bus: i2s0-2ch-bus {
2466 i2s0_2ch_bus_bclk_off: i2s0-2ch-bus-bclk-off {
2476 i2s0_8ch_bus: i2s0-8ch-bus {
2489 i2s0_8ch_bus_bclk_off: i2s0-8ch-bus-bclk-off {
2504 i2s1_2ch_bus: i2s1-2ch-bus {
2513 i2s1_2ch_bus_bclk_off: i2s1-2ch-bus-bclk-off {
2524 sdio0_bus1: sdio0-bus1 {
2529 sdio0_bus4: sdio0-bus4 {
2537 sdio0_cmd: sdio0-cmd {
2542 sdio0_clk: sdio0-clk {
2547 sdio0_cd: sdio0-cd {
2552 sdio0_pwr: sdio0-pwr {
2557 sdio0_bkpwr: sdio0-bkpwr {
2562 sdio0_wp: sdio0-wp {
2567 sdio0_int: sdio0-int {
2574 sdmmc_bus1: sdmmc-bus1 {
2579 sdmmc_bus4: sdmmc-bus4 {
2587 sdmmc_clk: sdmmc-clk {
2592 sdmmc_cmd: sdmmc-cmd {
2597 sdmmc_cd: sdmmc-cd {
2602 sdmmc_wp: sdmmc-wp {
2609 ap_pwroff: ap-pwroff {
2613 ddrio_pwroff: ddrio-pwroff {
2619 spdif_bus: spdif-bus {
2624 spdif_bus_1: spdif-bus-1 {
2631 spi0_clk: spi0-clk {
2635 spi0_cs0: spi0-cs0 {
2639 spi0_cs1: spi0-cs1 {
2643 spi0_tx: spi0-tx {
2647 spi0_rx: spi0-rx {
2654 spi1_clk: spi1-clk {
2658 spi1_cs0: spi1-cs0 {
2662 spi1_rx: spi1-rx {
2666 spi1_tx: spi1-tx {
2673 spi2_clk: spi2-clk {
2677 spi2_cs0: spi2-cs0 {
2681 spi2_rx: spi2-rx {
2685 spi2_tx: spi2-tx {
2692 spi3_clk: spi3-clk {
2696 spi3_cs0: spi3-cs0 {
2700 spi3_rx: spi3-rx {
2704 spi3_tx: spi3-tx {
2711 spi4_clk: spi4-clk {
2715 spi4_cs0: spi4-cs0 {
2719 spi4_rx: spi4-rx {
2723 spi4_tx: spi4-tx {
2730 spi5_clk: spi5-clk {
2734 spi5_cs0: spi5-cs0 {
2738 spi5_rx: spi5-rx {
2742 spi5_tx: spi5-tx {
2749 test_clkout0: test-clkout0 {
2754 test_clkout1: test-clkout1 {
2759 test_clkout2: test-clkout2 {
2766 otp_pin: otp-pin {
2770 otp_out: otp-out {
2776 uart0_xfer: uart0-xfer {
2782 uart0_cts: uart0-cts {
2787 uart0_rts: uart0-rts {
2794 uart1_xfer: uart1-xfer {
2802 uart2a_xfer: uart2a-xfer {
2810 uart2b_xfer: uart2b-xfer {
2818 uart2c_xfer: uart2c-xfer {
2826 uart3_xfer: uart3-xfer {
2832 uart3_cts: uart3-cts {
2837 uart3_rts: uart3-rts {
2844 uart4_xfer: uart4-xfer {
2852 uarthdcp_xfer: uarthdcp-xfer {
2860 pwm0_pin: pwm0-pin {
2865 pwm0_pin_pull_down: pwm0-pin-pull-down {
2870 vop0_pwm_pin: vop0-pwm-pin {
2875 vop1_pwm_pin: vop1-pwm-pin {
2882 pwm1_pin: pwm1-pin {
2887 pwm1_pin_pull_down: pwm1-pin-pull-down {
2894 pwm2_pin: pwm2-pin {
2899 pwm2_pin_pull_down: pwm2-pin-pull-down {
2906 pwm3a_pin: pwm3a-pin {
2913 pwm3b_pin: pwm3b-pin {
2920 hdmi_i2c_xfer: hdmi-i2c-xfer {
2926 hdmi_cec: hdmi-cec {
2933 pcie_clkreqn_cpm: pci-clkreqn-cpm {
2938 pcie_clkreqnb_cpm: pci-clkreqnb-cpm {