Lines Matching full:cru
6 #include <dt-bindings/clock/rk3368-cru.h>
186 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
187 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
191 resets = <&cru SRST_MMC0>;
200 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
201 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
205 resets = <&cru SRST_SDIO0>;
214 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
215 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
219 resets = <&cru SRST_EMMC>;
229 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
231 resets = <&cru SRST_SARADC>;
239 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
252 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
265 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
282 clocks = <&cru PCLK_I2C2>;
295 clocks = <&cru PCLK_I2C3>;
308 clocks = <&cru PCLK_I2C4>;
321 clocks = <&cru PCLK_I2C5>;
331 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
343 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
355 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
367 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
383 clocks = <&cru ACLK_DMAC_PERI>;
468 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
470 resets = <&cru SRST_TSADC>;
487 clocks = <&cru SCLK_MAC>,
488 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
489 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
490 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
502 clocks = <&cru HCLK_HOST0>;
511 clocks = <&cru HCLK_OTG0>;
528 clocks = <&cru ACLK_DMAC_BUS>;
535 clocks = <&cru PCLK_I2C0>;
552 clocks = <&cru PCLK_I2C1>;
564 clocks = <&cru PCLK_PWM1>;
574 clocks = <&cru PCLK_PWM1>;
582 clocks = <&cru PCLK_PWM1>;
592 clocks = <&cru PCLK_PWM1>;
599 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
616 clocks = <&cru PCLK_MAILBOX>;
657 clocks = <&cru ACLK_IEP>,
658 <&cru ACLK_ISP>,
659 <&cru ACLK_VIP>,
660 <&cru ACLK_RGA>,
661 <&cru ACLK_VOP>,
662 <&cru ACLK_VOP_IEP>,
663 <&cru DCLK_VOP>,
664 <&cru HCLK_IEP>,
665 <&cru HCLK_ISP>,
666 <&cru HCLK_RGA>,
667 <&cru HCLK_VIP>,
668 <&cru HCLK_VOP>,
669 <&cru HCLK_VIO_HDCPMMU>,
670 <&cru PCLK_EDP_CTRL>,
671 <&cru PCLK_HDMI_CTRL>,
672 <&cru PCLK_HDCP>,
673 <&cru PCLK_ISP>,
674 <&cru PCLK_VIP>,
675 <&cru PCLK_DPHYRX>,
676 <&cru PCLK_DPHYTX0>,
677 <&cru PCLK_MIPI_CSI>,
678 <&cru PCLK_MIPI_DSI0>,
679 <&cru SCLK_VOP0_PWM>,
680 <&cru SCLK_EDP_24M>,
681 <&cru SCLK_EDP>,
682 <&cru SCLK_HDCP>,
683 <&cru SCLK_ISP>,
684 <&cru SCLK_RGA>,
685 <&cru SCLK_HDMI_CEC>,
686 <&cru SCLK_HDMI_HDCP>;
706 clocks = <&cru ACLK_VIDEO>,
707 <&cru HCLK_VIDEO>,
708 <&cru SCLK_HEVC_CABAC>,
709 <&cru SCLK_HEVC_CORE>;
722 clocks = <&cru ACLK_GPU_CFG>,
723 <&cru ACLK_GPU_MEM>,
724 <&cru SCLK_GPU_CORE>;
750 cru: clock-controller@ff760000 {
751 compatible = "rockchip,rk3368-cru";
773 clocks = <&cru PCLK_WDT>;
782 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
790 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
804 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
815 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
827 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
839 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
851 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
863 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
874 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
950 clocks = <&cru PCLK_EFUSE256>;
986 clocks = <&cru PCLK_GPIO0>;
999 clocks = <&cru PCLK_GPIO1>;
1012 clocks = <&cru PCLK_GPIO2>;
1025 clocks = <&cru PCLK_GPIO3>;