Lines Matching +full:ns +full:- +full:cru
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3328-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3328-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
37 #address-cells = <2>;
38 #size-cells = <0>;
42 compatible = "arm,cortex-a53";
44 clocks = <&cru ARMCLK>;
45 #cooling-cells = <2>;
46 cpu-idle-states = <&CPU_SLEEP>;
47 dynamic-power-coefficient = <120>;
48 enable-method = "psci";
49 next-level-cache = <&l2>;
50 operating-points-v2 = <&cpu0_opp_table>;
55 compatible = "arm,cortex-a53";
57 clocks = <&cru ARMCLK>;
58 #cooling-cells = <2>;
59 cpu-idle-states = <&CPU_SLEEP>;
60 dynamic-power-coefficient = <120>;
61 enable-method = "psci";
62 next-level-cache = <&l2>;
63 operating-points-v2 = <&cpu0_opp_table>;
68 compatible = "arm,cortex-a53";
70 clocks = <&cru ARMCLK>;
71 #cooling-cells = <2>;
72 cpu-idle-states = <&CPU_SLEEP>;
73 dynamic-power-coefficient = <120>;
74 enable-method = "psci";
75 next-level-cache = <&l2>;
76 operating-points-v2 = <&cpu0_opp_table>;
81 compatible = "arm,cortex-a53";
83 clocks = <&cru ARMCLK>;
84 #cooling-cells = <2>;
85 cpu-idle-states = <&CPU_SLEEP>;
86 dynamic-power-coefficient = <120>;
87 enable-method = "psci";
88 next-level-cache = <&l2>;
89 operating-points-v2 = <&cpu0_opp_table>;
92 idle-states {
93 entry-method = "psci";
95 CPU_SLEEP: cpu-sleep {
96 compatible = "arm,idle-state";
97 local-timer-stop;
98 arm,psci-suspend-param = <0x0010000>;
99 entry-latency-us = <120>;
100 exit-latency-us = <250>;
101 min-residency-us = <900>;
105 l2: l2-cache0 {
107 cache-level = <2>;
108 cache-unified;
112 cpu0_opp_table: opp-table-0 {
113 compatible = "operating-points-v2";
114 opp-shared;
116 opp-408000000 {
117 opp-hz = /bits/ 64 <408000000>;
118 opp-microvolt = <950000>;
119 clock-latency-ns = <40000>;
120 opp-suspend;
122 opp-600000000 {
123 opp-hz = /bits/ 64 <600000000>;
124 opp-microvolt = <950000>;
125 clock-latency-ns = <40000>;
127 opp-816000000 {
128 opp-hz = /bits/ 64 <816000000>;
129 opp-microvolt = <1000000>;
130 clock-latency-ns = <40000>;
132 opp-1008000000 {
133 opp-hz = /bits/ 64 <1008000000>;
134 opp-microvolt = <1100000>;
135 clock-latency-ns = <40000>;
137 opp-1200000000 {
138 opp-hz = /bits/ 64 <1200000000>;
139 opp-microvolt = <1225000>;
140 clock-latency-ns = <40000>;
142 opp-1296000000 {
143 opp-hz = /bits/ 64 <1296000000>;
144 opp-microvolt = <1300000>;
145 clock-latency-ns = <40000>;
149 analog_sound: analog-sound {
150 compatible = "simple-audio-card";
151 simple-audio-card,format = "i2s";
152 simple-audio-card,mclk-fs = <256>;
153 simple-audio-card,name = "Analog";
156 simple-audio-card,cpu {
157 sound-dai = <&i2s1>;
160 simple-audio-card,codec {
161 sound-dai = <&codec>;
165 arm-pmu {
166 compatible = "arm,cortex-a53-pmu";
171 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
174 display_subsystem: display-subsystem {
175 compatible = "rockchip,display-subsystem";
179 hdmi_sound: hdmi-sound {
180 compatible = "simple-audio-card";
181 simple-audio-card,format = "i2s";
182 simple-audio-card,mclk-fs = <128>;
183 simple-audio-card,name = "HDMI";
186 simple-audio-card,cpu {
187 sound-dai = <&i2s0>;
190 simple-audio-card,codec {
191 sound-dai = <&hdmi>;
196 compatible = "arm,psci-1.0", "arm,psci-0.2";
201 compatible = "arm,armv8-timer";
209 compatible = "fixed-clock";
210 #clock-cells = <0>;
211 clock-frequency = <24000000>;
212 clock-output-names = "xin24m";
216 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
219 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
220 clock-names = "i2s_clk", "i2s_hclk";
222 dma-names = "tx", "rx";
223 #sound-dai-cells = <0>;
228 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
231 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
232 clock-names = "i2s_clk", "i2s_hclk";
234 dma-names = "tx", "rx";
235 #sound-dai-cells = <0>;
240 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
243 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
244 clock-names = "i2s_clk", "i2s_hclk";
246 dma-names = "tx", "rx";
247 #sound-dai-cells = <0>;
252 compatible = "rockchip,rk3328-spdif";
255 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
256 clock-names = "mclk", "hclk";
258 dma-names = "tx";
259 pinctrl-names = "default";
260 pinctrl-0 = <&spdifm2_tx>;
261 #sound-dai-cells = <0>;
268 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>;
269 clock-names = "pdm_clk", "pdm_hclk";
271 dma-names = "rx";
272 pinctrl-names = "default", "sleep";
273 pinctrl-0 = <&pdmm0_clk
278 pinctrl-1 = <&pdmm0_clk_sleep
287 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
290 io_domains: io-domains {
291 compatible = "rockchip,rk3328-io-voltage-domain";
296 compatible = "rockchip,rk3328-grf-gpio";
297 gpio-controller;
298 #gpio-cells = <2>;
301 power: power-controller {
302 compatible = "rockchip,rk3328-power-controller";
303 #power-domain-cells = <1>;
304 #address-cells = <1>;
305 #size-cells = <0>;
307 power-domain@RK3328_PD_HEVC {
309 #power-domain-cells = <0>;
311 power-domain@RK3328_PD_VIDEO {
313 clocks = <&cru ACLK_RKVDEC>,
314 <&cru HCLK_RKVDEC>,
315 <&cru SCLK_VDEC_CABAC>,
316 <&cru SCLK_VDEC_CORE>;
317 #power-domain-cells = <0>;
319 power-domain@RK3328_PD_VPU {
321 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
322 #power-domain-cells = <0>;
326 reboot-mode {
327 compatible = "syscon-reboot-mode";
329 mode-normal = <BOOT_NORMAL>;
330 mode-recovery = <BOOT_RECOVERY>;
331 mode-bootloader = <BOOT_FASTBOOT>;
332 mode-loader = <BOOT_BL_DOWNLOAD>;
337 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
340 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
341 clock-names = "baudclk", "apb_pclk";
343 dma-names = "tx", "rx";
344 pinctrl-names = "default";
345 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
346 reg-io-width = <4>;
347 reg-shift = <2>;
352 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
355 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
356 clock-names = "baudclk", "apb_pclk";
358 dma-names = "tx", "rx";
359 pinctrl-names = "default";
360 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
361 reg-io-width = <4>;
362 reg-shift = <2>;
367 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
370 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
371 clock-names = "baudclk", "apb_pclk";
373 dma-names = "tx", "rx";
374 pinctrl-names = "default";
375 pinctrl-0 = <&uart2m1_xfer>;
376 reg-io-width = <4>;
377 reg-shift = <2>;
382 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
385 #address-cells = <1>;
386 #size-cells = <0>;
387 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
388 clock-names = "i2c", "pclk";
389 pinctrl-names = "default";
390 pinctrl-0 = <&i2c0_xfer>;
395 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
398 #address-cells = <1>;
399 #size-cells = <0>;
400 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
401 clock-names = "i2c", "pclk";
402 pinctrl-names = "default";
403 pinctrl-0 = <&i2c1_xfer>;
408 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
411 #address-cells = <1>;
412 #size-cells = <0>;
413 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
414 clock-names = "i2c", "pclk";
415 pinctrl-names = "default";
416 pinctrl-0 = <&i2c2_xfer>;
421 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
424 #address-cells = <1>;
425 #size-cells = <0>;
426 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
427 clock-names = "i2c", "pclk";
428 pinctrl-names = "default";
429 pinctrl-0 = <&i2c3_xfer>;
434 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
437 #address-cells = <1>;
438 #size-cells = <0>;
439 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
440 clock-names = "spiclk", "apb_pclk";
442 dma-names = "tx", "rx";
443 pinctrl-names = "default";
444 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
449 compatible = "rockchip,rk3328-wdt", "snps,dw-wdt";
452 clocks = <&cru PCLK_WDT>;
456 compatible = "rockchip,rk3328-pwm";
458 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
459 clock-names = "pwm", "pclk";
460 pinctrl-names = "default";
461 pinctrl-0 = <&pwm0_pin>;
462 #pwm-cells = <3>;
467 compatible = "rockchip,rk3328-pwm";
469 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
470 clock-names = "pwm", "pclk";
471 pinctrl-names = "default";
472 pinctrl-0 = <&pwm1_pin>;
473 #pwm-cells = <3>;
478 compatible = "rockchip,rk3328-pwm";
480 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
481 clock-names = "pwm", "pclk";
482 pinctrl-names = "default";
483 pinctrl-0 = <&pwm2_pin>;
484 #pwm-cells = <3>;
489 compatible = "rockchip,rk3328-pwm";
491 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
492 clock-names = "pwm", "pclk";
493 pinctrl-names = "default";
494 pinctrl-0 = <&pwmir_pin>;
495 #pwm-cells = <3>;
499 dmac: dma-controller@ff1f0000 {
504 arm,pl330-periph-burst;
505 clocks = <&cru ACLK_DMAC>;
506 clock-names = "apb_pclk";
507 #dma-cells = <1>;
510 thermal-zones {
511 soc_thermal: soc-thermal {
512 polling-delay-passive = <20>;
513 polling-delay = <1000>;
514 sustainable-power = <1000>;
516 thermal-sensors = <&tsadc 0>;
519 threshold: trip-point0 {
524 target: trip-point1 {
529 soc_crit: soc-crit {
536 cooling-maps {
539 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
551 compatible = "rockchip,rk3328-tsadc";
554 assigned-clocks = <&cru SCLK_TSADC>;
555 assigned-clock-rates = <50000>;
556 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
557 clock-names = "tsadc", "apb_pclk";
558 pinctrl-names = "init", "default", "sleep";
559 pinctrl-0 = <&otp_pin>;
560 pinctrl-1 = <&otp_out>;
561 pinctrl-2 = <&otp_pin>;
562 resets = <&cru SRST_TSADC>;
563 reset-names = "tsadc-apb";
565 rockchip,hw-tshut-temp = <100000>;
566 #thermal-sensor-cells = <1>;
571 compatible = "rockchip,rk3328-efuse";
573 #address-cells = <1>;
574 #size-cells = <1>;
575 clocks = <&cru SCLK_EFUSE>;
576 clock-names = "pclk_efuse";
577 rockchip,efuse-size = <0x20>;
583 cpu_leakage: cpu-leakage@17 {
586 logic_leakage: logic-leakage@19 {
589 efuse_cpu_version: cpu-version@1a {
596 compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc";
599 #io-channel-cells = <1>;
600 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
601 clock-names = "saradc", "apb_pclk";
602 resets = <&cru SRST_SARADC_P>;
603 reset-names = "saradc-apb";
608 compatible = "rockchip,rk3328-mali", "arm,mali-450";
617 interrupt-names = "gp",
624 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
625 clock-names = "bus", "core";
626 resets = <&cru SRST_GPU_A>;
633 clocks = <&cru ACLK_H265>, <&cru PCLK_H265>;
634 clock-names = "aclk", "iface";
635 #iommu-cells = <0>;
643 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
644 clock-names = "aclk", "iface";
645 #iommu-cells = <0>;
649 vpu: video-codec@ff350000 {
650 compatible = "rockchip,rk3328-vpu";
653 interrupt-names = "vdpu";
654 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
655 clock-names = "aclk", "hclk";
657 power-domains = <&power RK3328_PD_VPU>;
664 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
665 clock-names = "aclk", "iface";
666 #iommu-cells = <0>;
667 power-domains = <&power RK3328_PD_VPU>;
670 vdec: video-codec@ff360000 {
671 compatible = "rockchip,rk3328-vdec", "rockchip,rk3399-vdec";
674 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,
675 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>;
676 clock-names = "axi", "ahb", "cabac", "core";
677 assigned-clocks = <&cru ACLK_RKVDEC>, <&cru SCLK_VDEC_CABAC>,
678 <&cru SCLK_VDEC_CORE>;
679 assigned-clock-rates = <400000000>, <400000000>, <300000000>;
681 power-domains = <&power RK3328_PD_VIDEO>;
688 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
689 clock-names = "aclk", "iface";
690 #iommu-cells = <0>;
691 power-domains = <&power RK3328_PD_VIDEO>;
695 compatible = "rockchip,rk3328-vop";
698 clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>;
699 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
700 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
701 reset-names = "axi", "ahb", "dclk";
706 #address-cells = <1>;
707 #size-cells = <0>;
711 remote-endpoint = <&hdmi_in_vop>;
720 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
721 clock-names = "aclk", "iface";
722 #iommu-cells = <0>;
727 compatible = "rockchip,rk3328-dw-hdmi";
729 reg-io-width = <4>;
732 clocks = <&cru PCLK_HDMI>,
733 <&cru SCLK_HDMI_SFC>,
734 <&cru SCLK_RTC32K>;
735 clock-names = "iahb",
739 phy-names = "hdmi";
740 pinctrl-names = "default";
741 pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>;
743 #sound-dai-cells = <0>;
749 remote-endpoint = <&vop_out_hdmi>;
756 compatible = "rockchip,rk3328-codec";
758 clocks = <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>;
759 clock-names = "pclk", "mclk";
761 #sound-dai-cells = <0>;
766 compatible = "rockchip,rk3328-hdmi-phy";
769 clocks = <&cru PCLK_HDMIPHY>, <&xin24m>, <&cru DCLK_HDMIPHY>;
770 clock-names = "sysclk", "refoclk", "refpclk";
771 clock-output-names = "hdmi_phy";
772 #clock-cells = <0>;
773 nvmem-cells = <&efuse_cpu_version>;
774 nvmem-cell-names = "cpu-version";
775 #phy-cells = <0>;
779 cru: clock-controller@ff440000 {
780 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
783 #clock-cells = <1>;
784 #reset-cells = <1>;
785 assigned-clocks =
792 <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
793 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
794 <&cru SCLK_UART1>, <&cru SCLK_UART2>,
795 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
796 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
797 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
798 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
799 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
800 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
801 <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
802 <&cru SCLK_WIFI>, <&cru ARMCLK>,
803 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
804 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
805 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
806 <&cru HCLK_PERI>, <&cru PCLK_PERI>,
807 <&cru SCLK_RTC32K>;
808 assigned-clock-parents =
809 <&cru HDMIPHY>, <&cru PLL_APLL>,
810 <&cru PLL_GPLL>, <&xin24m>,
812 assigned-clock-rates =
832 compatible = "rockchip,rk3328-usb2phy-grf", "syscon",
833 "simple-mfd";
835 #address-cells = <1>;
836 #size-cells = <1>;
839 compatible = "rockchip,rk3328-usb2phy";
842 clock-names = "phyclk";
843 clock-output-names = "usb480m_phy";
844 #clock-cells = <0>;
845 assigned-clocks = <&cru USB480M>;
846 assigned-clock-parents = <&u2phy>;
849 u2phy_otg: otg-port {
850 #phy-cells = <0>;
854 interrupt-names = "otg-bvalid", "otg-id",
859 u2phy_host: host-port {
860 #phy-cells = <0>;
862 interrupt-names = "linestate";
869 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
872 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
873 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
874 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
875 fifo-depth = <0x100>;
876 max-frequency = <150000000>;
881 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
884 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
885 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
886 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
887 fifo-depth = <0x100>;
888 max-frequency = <150000000>;
893 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
896 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
897 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
898 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
899 fifo-depth = <0x100>;
900 max-frequency = <150000000>;
905 compatible = "rockchip,rk3328-gmac";
908 interrupt-names = "macirq";
909 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
910 <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>,
911 <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>,
912 <&cru PCLK_MAC2IO>;
913 clock-names = "stmmaceth", "mac_clk_rx",
917 resets = <&cru SRST_GMAC2IO_A>;
918 reset-names = "stmmaceth";
920 tx-fifo-depth = <2048>;
921 rx-fifo-depth = <4096>;
927 compatible = "rockchip,rk3328-gmac";
931 interrupt-names = "macirq";
932 clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>,
933 <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>,
934 <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>,
935 <&cru SCLK_MAC2PHY_OUT>;
936 clock-names = "stmmaceth", "mac_clk_rx",
940 resets = <&cru SRST_GMAC2PHY_A>;
941 reset-names = "stmmaceth";
942 phy-mode = "rmii";
943 phy-handle = <&phy>;
944 tx-fifo-depth = <2048>;
945 rx-fifo-depth = <4096>;
951 compatible = "snps,dwmac-mdio";
952 #address-cells = <1>;
953 #size-cells = <0>;
955 phy: ethernet-phy@0 {
956 compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";
958 clocks = <&cru SCLK_MAC2PHY_OUT>;
959 resets = <&cru SRST_MACPHY>;
960 pinctrl-names = "default";
961 pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>;
962 phy-is-integrated;
968 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
972 clocks = <&cru HCLK_OTG>;
973 clock-names = "otg";
975 g-np-tx-fifo-size = <16>;
976 g-rx-fifo-size = <280>;
977 g-tx-fifo-size = <256 128 128 64 32 16>;
979 phy-names = "usb2-phy";
984 compatible = "generic-ehci";
987 clocks = <&cru HCLK_HOST0>, <&u2phy>;
989 phy-names = "usb";
994 compatible = "generic-ohci";
997 clocks = <&cru HCLK_HOST0>, <&u2phy>;
999 phy-names = "usb";
1004 compatible = "rockchip,rk3328-dwc3", "snps,dwc3";
1007 clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,
1008 <&cru ACLK_USB3OTG>;
1009 clock-names = "ref_clk", "suspend_clk",
1013 snps,dis-del-phy-power-chg-quirk;
1015 snps,dis-tx-ipgap-linecheck-quirk;
1016 snps,dis-u2-freeclk-exists-quirk;
1022 gic: interrupt-controller@ff811000 {
1023 compatible = "arm,gic-400";
1024 #interrupt-cells = <3>;
1025 #address-cells = <0>;
1026 interrupt-controller;
1036 compatible = "rockchip,rk3328-crypto";
1039 clocks = <&cru HCLK_CRYPTO_MST>, <&cru HCLK_CRYPTO_SLV>,
1040 <&cru SCLK_CRYPTO>;
1041 clock-names = "hclk_master", "hclk_slave", "sclk";
1042 resets = <&cru SRST_CRYPTO>;
1043 reset-names = "crypto-rst";
1047 compatible = "rockchip,rk3328-pinctrl";
1049 #address-cells = <2>;
1050 #size-cells = <2>;
1054 compatible = "rockchip,gpio-bank";
1057 clocks = <&cru PCLK_GPIO0>;
1059 gpio-controller;
1060 #gpio-cells = <2>;
1062 interrupt-controller;
1063 #interrupt-cells = <2>;
1067 compatible = "rockchip,gpio-bank";
1070 clocks = <&cru PCLK_GPIO1>;
1072 gpio-controller;
1073 #gpio-cells = <2>;
1075 interrupt-controller;
1076 #interrupt-cells = <2>;
1080 compatible = "rockchip,gpio-bank";
1083 clocks = <&cru PCLK_GPIO2>;
1085 gpio-controller;
1086 #gpio-cells = <2>;
1088 interrupt-controller;
1089 #interrupt-cells = <2>;
1093 compatible = "rockchip,gpio-bank";
1096 clocks = <&cru PCLK_GPIO3>;
1098 gpio-controller;
1099 #gpio-cells = <2>;
1101 interrupt-controller;
1102 #interrupt-cells = <2>;
1105 pcfg_pull_up: pcfg-pull-up {
1106 bias-pull-up;
1109 pcfg_pull_down: pcfg-pull-down {
1110 bias-pull-down;
1113 pcfg_pull_none: pcfg-pull-none {
1114 bias-disable;
1117 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
1118 bias-disable;
1119 drive-strength = <2>;
1122 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1123 bias-pull-up;
1124 drive-strength = <2>;
1127 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
1128 bias-pull-up;
1129 drive-strength = <4>;
1132 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
1133 bias-disable;
1134 drive-strength = <4>;
1137 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1138 bias-pull-down;
1139 drive-strength = <4>;
1142 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
1143 bias-disable;
1144 drive-strength = <8>;
1147 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1148 bias-pull-up;
1149 drive-strength = <8>;
1152 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1153 bias-disable;
1154 drive-strength = <12>;
1157 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
1158 bias-pull-up;
1159 drive-strength = <12>;
1162 pcfg_output_high: pcfg-output-high {
1163 output-high;
1166 pcfg_output_low: pcfg-output-low {
1167 output-low;
1170 pcfg_input_high: pcfg-input-high {
1171 bias-pull-up;
1172 input-enable;
1175 pcfg_input: pcfg-input {
1176 input-enable;
1180 i2c0_xfer: i2c0-xfer {
1187 i2c1_xfer: i2c1-xfer {
1194 i2c2_xfer: i2c2-xfer {
1201 i2c3_xfer: i2c3-xfer {
1205 i2c3_pins: i2c3-pins {
1213 hdmii2c_xfer: hdmii2c-xfer {
1219 pdm-0 {
1220 pdmm0_clk: pdmm0-clk {
1224 pdmm0_fsync: pdmm0-fsync {
1228 pdmm0_sdi0: pdmm0-sdi0 {
1232 pdmm0_sdi1: pdmm0-sdi1 {
1236 pdmm0_sdi2: pdmm0-sdi2 {
1240 pdmm0_sdi3: pdmm0-sdi3 {
1244 pdmm0_clk_sleep: pdmm0-clk-sleep {
1249 pdmm0_sdi0_sleep: pdmm0-sdi0-sleep {
1254 pdmm0_sdi1_sleep: pdmm0-sdi1-sleep {
1259 pdmm0_sdi2_sleep: pdmm0-sdi2-sleep {
1264 pdmm0_sdi3_sleep: pdmm0-sdi3-sleep {
1269 pdmm0_fsync_sleep: pdmm0-fsync-sleep {
1276 otp_pin: otp-pin {
1280 otp_out: otp-out {
1286 uart0_xfer: uart0-xfer {
1291 uart0_cts: uart0-cts {
1295 uart0_rts: uart0-rts {
1299 uart0_rts_pin: uart0-rts-pin {
1305 uart1_xfer: uart1-xfer {
1310 uart1_cts: uart1-cts {
1314 uart1_rts: uart1-rts {
1318 uart1_rts_pin: uart1-rts-pin {
1323 uart2-0 {
1324 uart2m0_xfer: uart2m0-xfer {
1330 uart2-1 {
1331 uart2m1_xfer: uart2m1-xfer {
1337 spi0-0 {
1338 spi0m0_clk: spi0m0-clk {
1342 spi0m0_cs0: spi0m0-cs0 {
1346 spi0m0_tx: spi0m0-tx {
1350 spi0m0_rx: spi0m0-rx {
1354 spi0m0_cs1: spi0m0-cs1 {
1359 spi0-1 {
1360 spi0m1_clk: spi0m1-clk {
1364 spi0m1_cs0: spi0m1-cs0 {
1368 spi0m1_tx: spi0m1-tx {
1372 spi0m1_rx: spi0m1-rx {
1376 spi0m1_cs1: spi0m1-cs1 {
1381 spi0-2 {
1382 spi0m2_clk: spi0m2-clk {
1386 spi0m2_cs0: spi0m2-cs0 {
1390 spi0m2_tx: spi0m2-tx {
1394 spi0m2_rx: spi0m2-rx {
1400 i2s1_mclk: i2s1-mclk {
1404 i2s1_sclk: i2s1-sclk {
1408 i2s1_lrckrx: i2s1-lrckrx {
1412 i2s1_lrcktx: i2s1-lrcktx {
1416 i2s1_sdi: i2s1-sdi {
1420 i2s1_sdo: i2s1-sdo {
1424 i2s1_sdio1: i2s1-sdio1 {
1428 i2s1_sdio2: i2s1-sdio2 {
1432 i2s1_sdio3: i2s1-sdio3 {
1436 i2s1_sleep: i2s1-sleep {
1450 i2s2-0 {
1451 i2s2m0_mclk: i2s2m0-mclk {
1455 i2s2m0_sclk: i2s2m0-sclk {
1459 i2s2m0_lrckrx: i2s2m0-lrckrx {
1463 i2s2m0_lrcktx: i2s2m0-lrcktx {
1467 i2s2m0_sdi: i2s2m0-sdi {
1471 i2s2m0_sdo: i2s2m0-sdo {
1475 i2s2m0_sleep: i2s2m0-sleep {
1486 i2s2-1 {
1487 i2s2m1_mclk: i2s2m1-mclk {
1491 i2s2m1_sclk: i2s2m1-sclk {
1495 i2s2m1_lrckrx: i2sm1-lrckrx {
1499 i2s2m1_lrcktx: i2s2m1-lrcktx {
1503 i2s2m1_sdi: i2s2m1-sdi {
1507 i2s2m1_sdo: i2s2m1-sdo {
1511 i2s2m1_sleep: i2s2m1-sleep {
1521 spdif-0 {
1522 spdifm0_tx: spdifm0-tx {
1527 spdif-1 {
1528 spdifm1_tx: spdifm1-tx {
1533 spdif-2 {
1534 spdifm2_tx: spdifm2-tx {
1539 sdmmc0-0 {
1540 sdmmc0m0_pwren: sdmmc0m0-pwren {
1544 sdmmc0m0_pin: sdmmc0m0-pin {
1549 sdmmc0-1 {
1550 sdmmc0m1_pwren: sdmmc0m1-pwren {
1554 sdmmc0m1_pin: sdmmc0m1-pin {
1560 sdmmc0_clk: sdmmc0-clk {
1564 sdmmc0_cmd: sdmmc0-cmd {
1568 sdmmc0_dectn: sdmmc0-dectn {
1572 sdmmc0_wrprt: sdmmc0-wrprt {
1576 sdmmc0_bus1: sdmmc0-bus1 {
1580 sdmmc0_bus4: sdmmc0-bus4 {
1587 sdmmc0_pins: sdmmc0-pins {
1601 sdmmc0ext_clk: sdmmc0ext-clk {
1605 sdmmc0ext_cmd: sdmmc0ext-cmd {
1609 sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1613 sdmmc0ext_dectn: sdmmc0ext-dectn {
1617 sdmmc0ext_bus1: sdmmc0ext-bus1 {
1621 sdmmc0ext_bus4: sdmmc0ext-bus4 {
1629 sdmmc0ext_pins: sdmmc0ext-pins {
1643 sdmmc1_clk: sdmmc1-clk {
1647 sdmmc1_cmd: sdmmc1-cmd {
1651 sdmmc1_pwren: sdmmc1-pwren {
1655 sdmmc1_wrprt: sdmmc1-wrprt {
1659 sdmmc1_dectn: sdmmc1-dectn {
1663 sdmmc1_bus1: sdmmc1-bus1 {
1667 sdmmc1_bus4: sdmmc1-bus4 {
1674 sdmmc1_pins: sdmmc1-pins {
1689 emmc_clk: emmc-clk {
1693 emmc_cmd: emmc-cmd {
1697 emmc_pwren: emmc-pwren {
1701 emmc_rstnout: emmc-rstnout {
1705 emmc_bus1: emmc-bus1 {
1709 emmc_bus4: emmc-bus4 {
1717 emmc_bus8: emmc-bus8 {
1731 pwm0_pin: pwm0-pin {
1737 pwm1_pin: pwm1-pin {
1743 pwm2_pin: pwm2-pin {
1749 pwmir_pin: pwmir-pin {
1754 gmac-1 {
1755 rgmiim1_pins: rgmiim1-pins {
1804 rmiim1_pins: rmiim1-pins {
1843 fephyled_speed10: fephyled-speed10 {
1847 fephyled_duplex: fephyled-duplex {
1851 fephyled_rxm1: fephyled-rxm1 {
1855 fephyled_txm1: fephyled-txm1 {
1859 fephyled_linkm1: fephyled-linkm1 {
1865 tsadc_int: tsadc-int {
1868 tsadc_pin: tsadc-pin {
1874 hdmi_cec: hdmi-cec {
1878 hdmi_hpd: hdmi-hpd {
1883 cif-0 {
1884 dvp_d2d9_m0:dvp-d2d9-m0 {
1913 cif-1 {
1914 dvp_d2d9_m1:dvp-d2d9-m1 {