Lines Matching full:cru
6 #include <dt-bindings/clock/rk3328-cru.h>
44 clocks = <&cru ARMCLK>;
57 clocks = <&cru ARMCLK>;
70 clocks = <&cru ARMCLK>;
83 clocks = <&cru ARMCLK>;
219 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
231 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
243 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
255 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
268 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>;
313 clocks = <&cru ACLK_RKVDEC>,
314 <&cru HCLK_RKVDEC>,
315 <&cru SCLK_VDEC_CABAC>,
316 <&cru SCLK_VDEC_CORE>;
321 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
340 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
355 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
370 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
387 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
400 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
413 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
426 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
439 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
452 clocks = <&cru PCLK_WDT>;
458 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
469 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
480 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
491 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
505 clocks = <&cru ACLK_DMAC>;
554 assigned-clocks = <&cru SCLK_TSADC>;
556 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
562 resets = <&cru SRST_TSADC>;
575 clocks = <&cru SCLK_EFUSE>;
600 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
602 resets = <&cru SRST_SARADC_P>;
624 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
626 resets = <&cru SRST_GPU_A>;
633 clocks = <&cru ACLK_H265>, <&cru PCLK_H265>;
643 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
654 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
664 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
674 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,
675 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>;
677 assigned-clocks = <&cru ACLK_RKVDEC>, <&cru SCLK_VDEC_CABAC>,
678 <&cru SCLK_VDEC_CORE>;
688 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
698 clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>;
700 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
720 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
732 clocks = <&cru PCLK_HDMI>,
733 <&cru SCLK_HDMI_SFC>,
734 <&cru SCLK_RTC32K>;
758 clocks = <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>;
769 clocks = <&cru PCLK_HDMIPHY>, <&xin24m>, <&cru DCLK_HDMIPHY>;
779 cru: clock-controller@ff440000 {
780 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
792 <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
793 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
794 <&cru SCLK_UART1>, <&cru SCLK_UART2>,
795 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
796 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
797 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
798 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
799 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
800 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
801 <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
802 <&cru SCLK_WIFI>, <&cru ARMCLK>,
803 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
804 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
805 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
806 <&cru HCLK_PERI>, <&cru PCLK_PERI>,
807 <&cru SCLK_RTC32K>;
809 <&cru HDMIPHY>, <&cru PLL_APLL>,
810 <&cru PLL_GPLL>, <&xin24m>,
845 assigned-clocks = <&cru USB480M>;
872 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
873 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
884 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
885 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
896 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
897 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
909 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
910 <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>,
911 <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>,
912 <&cru PCLK_MAC2IO>;
917 resets = <&cru SRST_GMAC2IO_A>;
932 clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>,
933 <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>,
934 <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>,
935 <&cru SCLK_MAC2PHY_OUT>;
940 resets = <&cru SRST_GMAC2PHY_A>;
958 clocks = <&cru SCLK_MAC2PHY_OUT>;
959 resets = <&cru SRST_MACPHY>;
972 clocks = <&cru HCLK_OTG>;
987 clocks = <&cru HCLK_HOST0>, <&u2phy>;
997 clocks = <&cru HCLK_HOST0>, <&u2phy>;
1007 clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,
1008 <&cru ACLK_USB3OTG>;
1039 clocks = <&cru HCLK_CRYPTO_MST>, <&cru HCLK_CRYPTO_SLV>,
1040 <&cru SCLK_CRYPTO>;
1042 resets = <&cru SRST_CRYPTO>;
1057 clocks = <&cru PCLK_GPIO0>;
1070 clocks = <&cru PCLK_GPIO1>;
1083 clocks = <&cru PCLK_GPIO2>;
1096 clocks = <&cru PCLK_GPIO3>;