Lines Matching +full:0 +full:xff280000
38 #size-cells = <0>;
40 cpu0: cpu@0 {
43 reg = <0x0 0x0>;
56 reg = <0x0 0x1>;
69 reg = <0x0 0x2>;
82 reg = <0x0 0x3>;
98 arm,psci-suspend-param = <0x0010000>;
112 cpu0_opp_table: opp-table-0 {
210 #clock-cells = <0>;
217 reg = <0x0 0xff000000 0x0 0x1000>;
223 #sound-dai-cells = <0>;
229 reg = <0x0 0xff010000 0x0 0x1000>;
235 #sound-dai-cells = <0>;
241 reg = <0x0 0xff020000 0x0 0x1000>;
245 dmas = <&dmac 0>, <&dmac 1>;
247 #sound-dai-cells = <0>;
253 reg = <0x0 0xff030000 0x0 0x1000>;
260 pinctrl-0 = <&spdifm2_tx>;
261 #sound-dai-cells = <0>;
267 reg = <0x0 0xff040000 0x0 0x1000>;
273 pinctrl-0 = <&pdmm0_clk
288 reg = <0x0 0xff100000 0x0 0x1000>;
305 #size-cells = <0>;
309 #power-domain-cells = <0>;
317 #power-domain-cells = <0>;
322 #power-domain-cells = <0>;
328 offset = <0x5c8>;
338 reg = <0x0 0xff110000 0x0 0x100>;
345 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
353 reg = <0x0 0xff120000 0x0 0x100>;
360 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
368 reg = <0x0 0xff130000 0x0 0x100>;
375 pinctrl-0 = <&uart2m1_xfer>;
383 reg = <0x0 0xff150000 0x0 0x1000>;
386 #size-cells = <0>;
390 pinctrl-0 = <&i2c0_xfer>;
396 reg = <0x0 0xff160000 0x0 0x1000>;
399 #size-cells = <0>;
403 pinctrl-0 = <&i2c1_xfer>;
409 reg = <0x0 0xff170000 0x0 0x1000>;
412 #size-cells = <0>;
416 pinctrl-0 = <&i2c2_xfer>;
422 reg = <0x0 0xff180000 0x0 0x1000>;
425 #size-cells = <0>;
429 pinctrl-0 = <&i2c3_xfer>;
435 reg = <0x0 0xff190000 0x0 0x1000>;
438 #size-cells = <0>;
444 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
450 reg = <0x0 0xff1a0000 0x0 0x100>;
457 reg = <0x0 0xff1b0000 0x0 0x10>;
461 pinctrl-0 = <&pwm0_pin>;
468 reg = <0x0 0xff1b0010 0x0 0x10>;
472 pinctrl-0 = <&pwm1_pin>;
479 reg = <0x0 0xff1b0020 0x0 0x10>;
483 pinctrl-0 = <&pwm2_pin>;
490 reg = <0x0 0xff1b0030 0x0 0x10>;
494 pinctrl-0 = <&pwmir_pin>;
501 reg = <0x0 0xff1f0000 0x0 0x4000>;
502 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
516 thermal-sensors = <&tsadc 0>;
552 reg = <0x0 0xff250000 0x0 0x100>;
559 pinctrl-0 = <&otp_pin>;
572 reg = <0x0 0xff260000 0x0 0x50>;
577 rockchip,efuse-size = <0x20>;
581 reg = <0x07 0x10>;
584 reg = <0x17 0x1>;
587 reg = <0x19 0x1>;
590 reg = <0x1a 0x1>;
597 reg = <0x0 0xff280000 0x0 0x100>;
609 reg = <0x0 0xff300000 0x0 0x30000>;
631 reg = <0x0 0xff330200 0 0x100>;
635 #iommu-cells = <0>;
641 reg = <0x0 0xff340800 0x0 0x40>;
645 #iommu-cells = <0>;
651 reg = <0x0 0xff350000 0x0 0x800>;
662 reg = <0x0 0xff350800 0x0 0x40>;
666 #iommu-cells = <0>;
672 reg = <0x0 0xff360000 0x0 0x480>;
686 reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>;
690 #iommu-cells = <0>;
696 reg = <0x0 0xff370000 0x0 0x3efc>;
707 #size-cells = <0>;
709 vop_out_hdmi: endpoint@0 {
710 reg = <0>;
718 reg = <0x0 0xff373f00 0x0 0x100>;
722 #iommu-cells = <0>;
728 reg = <0x0 0xff3c0000 0x0 0x20000>;
741 pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>;
743 #sound-dai-cells = <0>;
757 reg = <0x0 0xff410000 0x0 0x1000>;
761 #sound-dai-cells = <0>;
767 reg = <0x0 0xff430000 0x0 0x10000>;
772 #clock-cells = <0>;
775 #phy-cells = <0>;
781 reg = <0x0 0xff440000 0x0 0x1000>;
813 <0>, <61440000>,
814 <0>, <24000000>,
834 reg = <0x0 0xff450000 0x0 0x10000>;
840 reg = <0x100 0x10>;
844 #clock-cells = <0>;
850 #phy-cells = <0>;
860 #phy-cells = <0>;
870 reg = <0x0 0xff500000 0x0 0x4000>;
875 fifo-depth = <0x100>;
882 reg = <0x0 0xff510000 0x0 0x4000>;
887 fifo-depth = <0x100>;
894 reg = <0x0 0xff520000 0x0 0x4000>;
899 fifo-depth = <0x100>;
906 reg = <0x0 0xff540000 0x0 0x10000>;
922 snps,txpbl = <0x4>;
928 reg = <0x0 0xff550000 0x0 0x10000>;
946 snps,txpbl = <0x4>;
953 #size-cells = <0>;
955 phy: ethernet-phy@0 {
957 reg = <0>;
961 pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>;
970 reg = <0x0 0xff580000 0x0 0x40000>;
985 reg = <0x0 0xff5c0000 0x0 0x10000>;
995 reg = <0x0 0xff5d0000 0x0 0x10000>;
1005 reg = <0x0 0xff600000 0x0 0x100000>;
1025 #address-cells = <0>;
1027 reg = <0x0 0xff811000 0 0x1000>,
1028 <0x0 0xff812000 0 0x2000>,
1029 <0x0 0xff814000 0 0x2000>,
1030 <0x0 0xff816000 0 0x2000>;
1037 reg = <0x0 0xff060000 0x0 0x4000>;
1055 reg = <0x0 0xff210000 0x0 0x100>;
1068 reg = <0x0 0xff220000 0x0 0x100>;
1081 reg = <0x0 0xff230000 0x0 0x100>;
1094 reg = <0x0 0xff240000 0x0 0x100>;
1202 rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>,
1203 <0 RK_PA6 2 &pcfg_pull_none>;
1207 <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>,
1208 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
1214 rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>,
1215 <0 RK_PA6 1 &pcfg_pull_none>;
1219 pdm-0 {
1323 uart2-0 {
1337 spi0-0 {
1450 i2s2-0 {
1521 spdif-0 {
1523 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
1535 rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>;
1539 sdmmc0-0 {
1551 rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>;
1555 rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1706 rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>;
1711 <0 RK_PA7 2 &pcfg_pull_up_12ma>,
1719 <0 RK_PA7 2 &pcfg_pull_up_12ma>,
1789 <0 RK_PB0 1 &pcfg_pull_none_8ma>,
1791 <0 RK_PB4 1 &pcfg_pull_none_8ma>,
1793 <0 RK_PD0 1 &pcfg_pull_none_4ma>,
1795 <0 RK_PC0 1 &pcfg_pull_none_8ma>,
1797 <0 RK_PC1 1 &pcfg_pull_none_8ma>,
1799 <0 RK_PC7 1 &pcfg_pull_none_8ma>,
1801 <0 RK_PC6 1 &pcfg_pull_none_8ma>;
1828 <0 RK_PB3 1 &pcfg_pull_none>,
1830 <0 RK_PB4 1 &pcfg_pull_none>,
1832 <0 RK_PD0 1 &pcfg_pull_none>,
1834 <0 RK_PC3 1 &pcfg_pull_none>,
1836 <0 RK_PC0 1 &pcfg_pull_none>,
1838 <0 RK_PC1 1 &pcfg_pull_none>;
1844 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>;
1848 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>;
1875 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
1879 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>;
1883 cif-0 {