Lines Matching +full:ns +full:- +full:cru
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/clock/rk3308-cru.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
43 #address-cells = <2>;
44 #size-cells = <0>;
48 compatible = "arm,cortex-a35";
50 enable-method = "psci";
51 clocks = <&cru ARMCLK>;
52 #cooling-cells = <2>;
53 dynamic-power-coefficient = <90>;
54 operating-points-v2 = <&cpu0_opp_table>;
55 cpu-idle-states = <&CPU_SLEEP>;
56 next-level-cache = <&l2>;
61 compatible = "arm,cortex-a35";
63 enable-method = "psci";
64 operating-points-v2 = <&cpu0_opp_table>;
65 cpu-idle-states = <&CPU_SLEEP>;
66 next-level-cache = <&l2>;
71 compatible = "arm,cortex-a35";
73 enable-method = "psci";
74 operating-points-v2 = <&cpu0_opp_table>;
75 cpu-idle-states = <&CPU_SLEEP>;
76 next-level-cache = <&l2>;
81 compatible = "arm,cortex-a35";
83 enable-method = "psci";
84 operating-points-v2 = <&cpu0_opp_table>;
85 cpu-idle-states = <&CPU_SLEEP>;
86 next-level-cache = <&l2>;
89 idle-states {
90 entry-method = "psci";
92 CPU_SLEEP: cpu-sleep {
93 compatible = "arm,idle-state";
94 local-timer-stop;
95 arm,psci-suspend-param = <0x0010000>;
96 entry-latency-us = <120>;
97 exit-latency-us = <250>;
98 min-residency-us = <900>;
102 l2: l2-cache {
104 cache-level = <2>;
105 cache-unified;
109 cpu0_opp_table: opp-table-0 {
110 compatible = "operating-points-v2";
111 opp-shared;
113 opp-408000000 {
114 opp-hz = /bits/ 64 <408000000>;
115 opp-microvolt = <950000 950000 1340000>;
116 clock-latency-ns = <40000>;
117 opp-suspend;
119 opp-600000000 {
120 opp-hz = /bits/ 64 <600000000>;
121 opp-microvolt = <950000 950000 1340000>;
122 clock-latency-ns = <40000>;
124 opp-816000000 {
125 opp-hz = /bits/ 64 <816000000>;
126 opp-microvolt = <1025000 1025000 1340000>;
127 clock-latency-ns = <40000>;
129 opp-1008000000 {
130 opp-hz = /bits/ 64 <1008000000>;
131 opp-microvolt = <1125000 1125000 1340000>;
132 clock-latency-ns = <40000>;
136 arm-pmu {
137 compatible = "arm,cortex-a35-pmu";
142 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
145 mac_clkin: external-mac-clock {
146 compatible = "fixed-clock";
147 clock-frequency = <50000000>;
148 clock-output-names = "mac_clkin";
149 #clock-cells = <0>;
153 compatible = "arm,psci-1.0";
158 compatible = "arm,armv8-timer";
166 compatible = "fixed-clock";
167 #clock-cells = <0>;
168 clock-frequency = <24000000>;
169 clock-output-names = "xin24m";
173 compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd";
176 reboot-mode {
177 compatible = "syscon-reboot-mode";
179 mode-bootloader = <BOOT_BL_DOWNLOAD>;
180 mode-loader = <BOOT_BL_DOWNLOAD>;
181 mode-normal = <BOOT_NORMAL>;
182 mode-recovery = <BOOT_RECOVERY>;
183 mode-fastboot = <BOOT_FASTBOOT>;
188 compatible = "rockchip,rk3308-usb2phy-grf", "syscon", "simple-mfd";
190 #address-cells = <1>;
191 #size-cells = <1>;
194 compatible = "rockchip,rk3308-usb2phy";
196 assigned-clocks = <&cru USB480M>;
197 assigned-clock-parents = <&u2phy>;
198 clocks = <&cru SCLK_USBPHY_REF>;
199 clock-names = "phyclk";
200 clock-output-names = "usb480m_phy";
201 #clock-cells = <0>;
204 u2phy_otg: otg-port {
208 interrupt-names = "otg-bvalid", "otg-id",
210 #phy-cells = <0>;
214 u2phy_host: host-port {
216 interrupt-names = "linestate";
217 #phy-cells = <0>;
224 compatible = "rockchip,rk3308-detect-grf", "syscon", "simple-mfd";
226 #address-cells = <1>;
227 #size-cells = <1>;
231 compatible = "rockchip,rk3308-core-grf", "syscon", "simple-mfd";
233 #address-cells = <1>;
234 #size-cells = <1>;
238 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
240 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
241 clock-names = "i2c", "pclk";
243 pinctrl-names = "default";
244 pinctrl-0 = <&i2c0_xfer>;
245 #address-cells = <1>;
246 #size-cells = <0>;
251 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
253 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
254 clock-names = "i2c", "pclk";
256 pinctrl-names = "default";
257 pinctrl-0 = <&i2c1_xfer>;
258 #address-cells = <1>;
259 #size-cells = <0>;
264 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
266 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
267 clock-names = "i2c", "pclk";
269 pinctrl-names = "default";
270 pinctrl-0 = <&i2c2_xfer>;
271 #address-cells = <1>;
272 #size-cells = <0>;
277 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
279 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
280 clock-names = "i2c", "pclk";
282 pinctrl-names = "default";
283 pinctrl-0 = <&i2c3m0_xfer>;
284 #address-cells = <1>;
285 #size-cells = <0>;
290 compatible = "rockchip,rk3308-wdt", "snps,dw-wdt";
292 clocks = <&cru PCLK_WDT>;
298 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
301 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
302 clock-names = "baudclk", "apb_pclk";
303 reg-shift = <2>;
304 reg-io-width = <4>;
305 pinctrl-names = "default";
306 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
311 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
314 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
315 clock-names = "baudclk", "apb_pclk";
316 reg-shift = <2>;
317 reg-io-width = <4>;
318 pinctrl-names = "default";
319 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
324 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
327 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
328 clock-names = "baudclk", "apb_pclk";
329 reg-shift = <2>;
330 reg-io-width = <4>;
331 pinctrl-names = "default";
332 pinctrl-0 = <&uart2m0_xfer>;
337 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
340 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
341 clock-names = "baudclk", "apb_pclk";
342 reg-shift = <2>;
343 reg-io-width = <4>;
344 pinctrl-names = "default";
345 pinctrl-0 = <&uart3_xfer>;
350 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
353 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
354 clock-names = "baudclk", "apb_pclk";
355 reg-shift = <2>;
356 reg-io-width = <4>;
357 pinctrl-names = "default";
358 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
363 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi";
366 #address-cells = <1>;
367 #size-cells = <0>;
368 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
369 clock-names = "spiclk", "apb_pclk";
371 dma-names = "tx", "rx";
372 pinctrl-names = "default";
373 pinctrl-0 = <&spi0_clk &spi0_csn0 &spi0_miso &spi0_mosi>;
378 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi";
381 #address-cells = <1>;
382 #size-cells = <0>;
383 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
384 clock-names = "spiclk", "apb_pclk";
386 dma-names = "tx", "rx";
387 pinctrl-names = "default";
388 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_miso &spi1_mosi>;
393 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi";
396 #address-cells = <1>;
397 #size-cells = <0>;
398 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
399 clock-names = "spiclk", "apb_pclk";
401 dma-names = "tx", "rx";
402 pinctrl-names = "default";
403 pinctrl-0 = <&spi2_clk &spi2_csn0 &spi2_miso &spi2_mosi>;
408 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
410 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
411 clock-names = "pwm", "pclk";
412 pinctrl-names = "default";
413 pinctrl-0 = <&pwm8_pin>;
414 #pwm-cells = <3>;
419 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
421 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
422 clock-names = "pwm", "pclk";
423 pinctrl-names = "default";
424 pinctrl-0 = <&pwm9_pin>;
425 #pwm-cells = <3>;
430 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
432 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
433 clock-names = "pwm", "pclk";
434 pinctrl-names = "default";
435 pinctrl-0 = <&pwm10_pin>;
436 #pwm-cells = <3>;
441 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
443 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
444 clock-names = "pwm", "pclk";
445 pinctrl-names = "default";
446 pinctrl-0 = <&pwm11_pin>;
447 #pwm-cells = <3>;
452 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
454 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
455 clock-names = "pwm", "pclk";
456 pinctrl-names = "default";
457 pinctrl-0 = <&pwm4_pin>;
458 #pwm-cells = <3>;
463 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
465 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
466 clock-names = "pwm", "pclk";
467 pinctrl-names = "default";
468 pinctrl-0 = <&pwm5_pin>;
469 #pwm-cells = <3>;
474 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
476 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
477 clock-names = "pwm", "pclk";
478 pinctrl-names = "default";
479 pinctrl-0 = <&pwm6_pin>;
480 #pwm-cells = <3>;
485 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
487 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
488 clock-names = "pwm", "pclk";
489 pinctrl-names = "default";
490 pinctrl-0 = <&pwm7_pin>;
491 #pwm-cells = <3>;
496 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
498 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
499 clock-names = "pwm", "pclk";
500 pinctrl-names = "default";
501 pinctrl-0 = <&pwm0_pin>;
502 #pwm-cells = <3>;
507 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
509 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
510 clock-names = "pwm", "pclk";
511 pinctrl-names = "default";
512 pinctrl-0 = <&pwm1_pin>;
513 #pwm-cells = <3>;
518 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
520 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
521 clock-names = "pwm", "pclk";
522 pinctrl-names = "default";
523 pinctrl-0 = <&pwm2_pin>;
524 #pwm-cells = <3>;
529 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
531 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
532 clock-names = "pwm", "pclk";
533 pinctrl-names = "default";
534 pinctrl-0 = <&pwm3_pin>;
535 #pwm-cells = <3>;
540 compatible = "rockchip,rk3288-timer";
543 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
544 clock-names = "pclk", "timer";
548 compatible = "rockchip,rk3308-saradc", "rockchip,rk3399-saradc";
551 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
552 clock-names = "saradc", "apb_pclk";
553 #io-channel-cells = <1>;
554 resets = <&cru SRST_SARADC_P>;
555 reset-names = "saradc-apb";
559 dmac0: dma-controller@ff2c0000 {
564 arm,pl330-periph-burst;
565 clocks = <&cru ACLK_DMAC0>;
566 clock-names = "apb_pclk";
567 #dma-cells = <1>;
570 dmac1: dma-controller@ff2d0000 {
575 arm,pl330-periph-burst;
576 clocks = <&cru ACLK_DMAC1>;
577 clock-names = "apb_pclk";
578 #dma-cells = <1>;
582 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s";
585 clocks = <&cru SCLK_I2S0_2CH>, <&cru HCLK_I2S0_2CH>;
586 clock-names = "i2s_clk", "i2s_hclk";
588 dma-names = "tx", "rx";
589 resets = <&cru SRST_I2S0_2CH_M>, <&cru SRST_I2S0_2CH_H>;
590 reset-names = "reset-m", "reset-h";
591 pinctrl-names = "default";
592 pinctrl-0 = <&i2s_2ch_0_sclk
600 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s";
603 clocks = <&cru SCLK_I2S1_2CH>, <&cru HCLK_I2S1_2CH>;
604 clock-names = "i2s_clk", "i2s_hclk";
606 dma-names = "rx";
607 resets = <&cru SRST_I2S1_2CH_M>, <&cru SRST_I2S1_2CH_H>;
608 reset-names = "reset-m", "reset-h";
612 spdif_tx: spdif-tx@ff3a0000 {
613 compatible = "rockchip,rk3308-spdif", "rockchip,rk3066-spdif";
616 clocks = <&cru SCLK_SPDIF_TX>, <&cru HCLK_SPDIFTX>;
617 clock-names = "mclk", "hclk";
619 dma-names = "tx";
620 pinctrl-names = "default";
621 pinctrl-0 = <&spdif_out>;
626 compatible = "rockchip,rk3308-usb", "rockchip,rk3066-usb",
630 clocks = <&cru HCLK_OTG>;
631 clock-names = "otg";
633 g-np-tx-fifo-size = <16>;
634 g-rx-fifo-size = <280>;
635 g-tx-fifo-size = <256 128 128 64 32 16>;
637 phy-names = "usb2-phy";
642 compatible = "generic-ehci";
645 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, <&u2phy>;
647 phy-names = "usb";
652 compatible = "generic-ohci";
655 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, <&u2phy>;
657 phy-names = "usb";
662 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
665 bus-width = <4>;
666 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
667 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
668 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
669 fifo-depth = <0x100>;
670 max-frequency = <150000000>;
671 pinctrl-names = "default";
672 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
677 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
680 bus-width = <8>;
681 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
682 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
683 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
684 fifo-depth = <0x100>;
685 max-frequency = <150000000>;
690 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
693 bus-width = <4>;
694 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
695 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
696 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
697 fifo-depth = <0x100>;
698 max-frequency = <150000000>;
699 pinctrl-names = "default";
700 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
704 nfc: nand-controller@ff4b0000 {
705 compatible = "rockchip,rk3308-nfc",
706 "rockchip,rv1108-nfc";
709 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
710 clock-names = "ahb", "nfc";
711 assigned-clocks = <&cru SCLK_NANDC>;
712 assigned-clock-rates = <150000000>;
713 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0
715 pinctrl-names = "default";
720 compatible = "rockchip,rk3308-gmac";
723 interrupt-names = "macirq";
724 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX_TX>,
725 <&cru SCLK_MAC_RX_TX>, <&cru SCLK_MAC_REF>,
726 <&cru SCLK_MAC>, <&cru ACLK_MAC>,
727 <&cru PCLK_MAC>, <&cru SCLK_MAC_RMII>;
728 clock-names = "stmmaceth", "mac_clk_rx",
732 phy-mode = "rmii";
733 pinctrl-names = "default";
734 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
735 resets = <&cru SRST_MAC_A>;
736 reset-names = "stmmaceth";
745 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
746 clock-names = "clk_sfc", "hclk_sfc";
747 pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
748 pinctrl-names = "default";
752 cru: clock-controller@ff500000 {
753 compatible = "rockchip,rk3308-cru";
756 clock-names = "xin24m";
758 #clock-cells = <1>;
759 #reset-cells = <1>;
760 assigned-clocks = <&cru SCLK_RTC32K>;
761 assigned-clock-rates = <32768>;
764 gic: interrupt-controller@ff580000 {
765 compatible = "arm,gic-400";
771 #interrupt-cells = <3>;
772 interrupt-controller;
773 #address-cells = <0>;
777 compatible = "mmio-sram";
780 #address-cells = <1>;
781 #size-cells = <1>;
784 ddr-sram@0 {
789 vad_sram: vad-sram@8000 {
795 compatible = "rockchip,rk3308-pinctrl";
797 #address-cells = <2>;
798 #size-cells = <2>;
802 compatible = "rockchip,gpio-bank";
805 clocks = <&cru PCLK_GPIO0>;
806 gpio-controller;
807 #gpio-cells = <2>;
808 interrupt-controller;
809 #interrupt-cells = <2>;
813 compatible = "rockchip,gpio-bank";
816 clocks = <&cru PCLK_GPIO1>;
817 gpio-controller;
818 #gpio-cells = <2>;
819 interrupt-controller;
820 #interrupt-cells = <2>;
824 compatible = "rockchip,gpio-bank";
827 clocks = <&cru PCLK_GPIO2>;
828 gpio-controller;
829 #gpio-cells = <2>;
830 interrupt-controller;
831 #interrupt-cells = <2>;
835 compatible = "rockchip,gpio-bank";
838 clocks = <&cru PCLK_GPIO3>;
839 gpio-controller;
840 #gpio-cells = <2>;
841 interrupt-controller;
842 #interrupt-cells = <2>;
846 compatible = "rockchip,gpio-bank";
849 clocks = <&cru PCLK_GPIO4>;
850 gpio-controller;
851 #gpio-cells = <2>;
852 interrupt-controller;
853 #interrupt-cells = <2>;
856 pcfg_pull_up: pcfg-pull-up {
857 bias-pull-up;
860 pcfg_pull_down: pcfg-pull-down {
861 bias-pull-down;
864 pcfg_pull_none: pcfg-pull-none {
865 bias-disable;
868 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
869 bias-disable;
870 drive-strength = <2>;
873 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
874 bias-pull-up;
875 drive-strength = <2>;
878 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
879 bias-pull-up;
880 drive-strength = <4>;
883 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
884 bias-disable;
885 drive-strength = <4>;
888 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
889 bias-pull-down;
890 drive-strength = <4>;
893 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
894 bias-disable;
895 drive-strength = <8>;
898 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
899 bias-pull-up;
900 drive-strength = <8>;
903 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
904 bias-disable;
905 drive-strength = <12>;
908 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
909 bias-pull-up;
910 drive-strength = <12>;
913 pcfg_pull_none_smt: pcfg-pull-none-smt {
914 bias-disable;
915 input-schmitt-enable;
918 pcfg_output_high: pcfg-output-high {
919 output-high;
922 pcfg_output_low: pcfg-output-low {
923 output-low;
926 pcfg_input_high: pcfg-input-high {
927 bias-pull-up;
928 input-enable;
931 pcfg_input: pcfg-input {
932 input-enable;
936 emmc_clk: emmc-clk {
941 emmc_cmd: emmc-cmd {
946 emmc_pwren: emmc-pwren {
951 emmc_rstn: emmc-rstn {
956 emmc_bus1: emmc-bus1 {
961 emmc_bus4: emmc-bus4 {
969 emmc_bus8: emmc-bus8 {
983 flash_csn0: flash-csn0 {
988 flash_rdy: flash-rdy {
993 flash_ale: flash-ale {
998 flash_cle: flash-cle {
1003 flash_wrn: flash-wrn {
1008 flash_rdn: flash-rdn {
1013 flash_bus8: flash-bus8 {
1027 sfc_bus4: sfc-bus4 {
1035 sfc_bus2: sfc-bus2 {
1041 sfc_cs0: sfc-cs0 {
1046 sfc_clk: sfc-clk {
1053 rmii_pins: rmii-pins {
1075 mac_refclk_12ma: mac-refclk-12ma {
1080 mac_refclk: mac-refclk {
1086 gmac-m1 {
1087 rmiim1_pins: rmiim1-pins {
1109 macm1_refclk_12ma: macm1-refclk-12ma {
1114 macm1_refclk: macm1-refclk {
1121 i2c0_xfer: i2c0-xfer {
1129 i2c1_xfer: i2c1-xfer {
1137 i2c2_xfer: i2c2-xfer {
1144 i2c3-m0 {
1145 i2c3m0_xfer: i2c3m0-xfer {
1152 i2c3-m1 {
1153 i2c3m1_xfer: i2c3m1-xfer {
1160 i2c3-m2 {
1161 i2c3m2_xfer: i2c3m2-xfer {
1169 i2s_2ch_0_mclk: i2s-2ch-0-mclk {
1174 i2s_2ch_0_sclk: i2s-2ch-0-sclk {
1179 i2s_2ch_0_lrck: i2s-2ch-0-lrck {
1184 i2s_2ch_0_sdo: i2s-2ch-0-sdo {
1189 i2s_2ch_0_sdi: i2s-2ch-0-sdi {
1196 i2s_8ch_0_mclk: i2s-8ch-0-mclk {
1201 i2s_8ch_0_sclktx: i2s-8ch-0-sclktx {
1206 i2s_8ch_0_sclkrx: i2s-8ch-0-sclkrx {
1211 i2s_8ch_0_lrcktx: i2s-8ch-0-lrcktx {
1216 i2s_8ch_0_lrckrx: i2s-8ch-0-lrckrx {
1221 i2s_8ch_0_sdo0: i2s-8ch-0-sdo0 {
1226 i2s_8ch_0_sdo1: i2s-8ch-0-sdo1 {
1231 i2s_8ch_0_sdo2: i2s-8ch-0-sdo2 {
1236 i2s_8ch_0_sdo3: i2s-8ch-0-sdo3 {
1241 i2s_8ch_0_sdi0: i2s-8ch-0-sdi0 {
1246 i2s_8ch_0_sdi1: i2s-8ch-0-sdi1 {
1251 i2s_8ch_0_sdi2: i2s-8ch-0-sdi2 {
1256 i2s_8ch_0_sdi3: i2s-8ch-0-sdi3 {
1263 i2s_8ch_1_m0_mclk: i2s-8ch-1-m0-mclk {
1268 i2s_8ch_1_m0_sclktx: i2s-8ch-1-m0-sclktx {
1273 i2s_8ch_1_m0_sclkrx: i2s-8ch-1-m0-sclkrx {
1278 i2s_8ch_1_m0_lrcktx: i2s-8ch-1-m0-lrcktx {
1283 i2s_8ch_1_m0_lrckrx: i2s-8ch-1-m0-lrckrx {
1288 i2s_8ch_1_m0_sdo0: i2s-8ch-1-m0-sdo0 {
1293 i2s_8ch_1_m0_sdo1_sdi3: i2s-8ch-1-m0-sdo1-sdi3 {
1298 i2s_8ch_1_m0_sdo2_sdi2: i2s-8ch-1-m0-sdo2-sdi2 {
1303 i2s_8ch_1_m0_sdo3_sdi1: i2s-8ch-1-m0-sdo3_sdi1 {
1308 i2s_8ch_1_m0_sdi0: i2s-8ch-1-m0-sdi0 {
1315 i2s_8ch_1_m1_mclk: i2s-8ch-1-m1-mclk {
1320 i2s_8ch_1_m1_sclktx: i2s-8ch-1-m1-sclktx {
1325 i2s_8ch_1_m1_sclkrx: i2s-8ch-1-m1-sclkrx {
1330 i2s_8ch_1_m1_lrcktx: i2s-8ch-1-m1-lrcktx {
1335 i2s_8ch_1_m1_lrckrx: i2s-8ch-1-m1-lrckrx {
1340 i2s_8ch_1_m1_sdo0: i2s-8ch-1-m1-sdo0 {
1345 i2s_8ch_1_m1_sdo1_sdi3: i2s-8ch-1-m1-sdo1-sdi3 {
1350 i2s_8ch_1_m1_sdo2_sdi2: i2s-8ch-1-m1-sdo2-sdi2 {
1355 i2s_8ch_1_m1_sdo3_sdi1: i2s-8ch-1-m1-sdo3_sdi1 {
1360 i2s_8ch_1_m1_sdi0: i2s-8ch-1-m1-sdi0 {
1367 pdm_m0_clk: pdm-m0-clk {
1372 pdm_m0_sdi0: pdm-m0-sdi0 {
1377 pdm_m0_sdi1: pdm-m0-sdi1 {
1382 pdm_m0_sdi2: pdm-m0-sdi2 {
1387 pdm_m0_sdi3: pdm-m0-sdi3 {
1394 pdm_m1_clk: pdm-m1-clk {
1399 pdm_m1_sdi0: pdm-m1-sdi0 {
1404 pdm_m1_sdi1: pdm-m1-sdi1 {
1409 pdm_m1_sdi2: pdm-m1-sdi2 {
1414 pdm_m1_sdi3: pdm-m1-sdi3 {
1421 pdm_m2_clkm: pdm-m2-clkm {
1426 pdm_m2_clk: pdm-m2-clk {
1431 pdm_m2_sdi0: pdm-m2-sdi0 {
1436 pdm_m2_sdi1: pdm-m2-sdi1 {
1441 pdm_m2_sdi2: pdm-m2-sdi2 {
1446 pdm_m2_sdi3: pdm-m2-sdi3 {
1453 pwm0_pin: pwm0-pin {
1458 pwm0_pin_pull_down: pwm0-pin-pull-down {
1465 pwm1_pin: pwm1-pin {
1470 pwm1_pin_pull_down: pwm1-pin-pull-down {
1477 pwm2_pin: pwm2-pin {
1482 pwm2_pin_pull_down: pwm2-pin-pull-down {
1489 pwm3_pin: pwm3-pin {
1494 pwm3_pin_pull_down: pwm3-pin-pull-down {
1501 pwm4_pin: pwm4-pin {
1506 pwm4_pin_pull_down: pwm4-pin-pull-down {
1513 pwm5_pin: pwm5-pin {
1518 pwm5_pin_pull_down: pwm5-pin-pull-down {
1525 pwm6_pin: pwm6-pin {
1530 pwm6_pin_pull_down: pwm6-pin-pull-down {
1537 pwm7_pin: pwm7-pin {
1542 pwm7_pin_pull_down: pwm7-pin-pull-down {
1549 pwm8_pin: pwm8-pin {
1554 pwm8_pin_pull_down: pwm8-pin-pull-down {
1561 pwm9_pin: pwm9-pin {
1566 pwm9_pin_pull_down: pwm9-pin-pull-down {
1573 pwm10_pin: pwm10-pin {
1578 pwm10_pin_pull_down: pwm10-pin-pull-down {
1585 pwm11_pin: pwm11-pin {
1590 pwm11_pin_pull_down: pwm11-pin-pull-down {
1597 rtc_32k: rtc-32k {
1604 sdmmc_clk: sdmmc-clk {
1609 sdmmc_cmd: sdmmc-cmd {
1614 sdmmc_det: sdmmc-det {
1619 sdmmc_pwren: sdmmc-pwren {
1624 sdmmc_bus1: sdmmc-bus1 {
1629 sdmmc_bus4: sdmmc-bus4 {
1639 sdio_clk: sdio-clk {
1644 sdio_cmd: sdio-cmd {
1649 sdio_pwren: sdio-pwren {
1654 sdio_wrpt: sdio-wrpt {
1659 sdio_intn: sdio-intn {
1664 sdio_bus1: sdio-bus1 {
1669 sdio_bus4: sdio-bus4 {
1679 spdif_in: spdif-in {
1686 spdif_out: spdif-out {
1693 spi0_clk: spi0-clk {
1698 spi0_csn0: spi0-csn0 {
1703 spi0_miso: spi0-miso {
1708 spi0_mosi: spi0-mosi {
1715 spi1_clk: spi1-clk {
1720 spi1_csn0: spi1-csn0 {
1725 spi1_miso: spi1-miso {
1730 spi1_mosi: spi1-mosi {
1736 spi1-m1 {
1737 spi1m1_miso: spi1m1-miso {
1742 spi1m1_mosi: spi1m1-mosi {
1747 spi1m1_clk: spi1m1-clk {
1752 spi1m1_csn0: spi1m1-csn0 {
1759 spi2_clk: spi2-clk {
1764 spi2_csn0: spi2-csn0 {
1769 spi2_miso: spi2-miso {
1774 spi2_mosi: spi2-mosi {
1781 tsadc_otp_pin: tsadc-otp-pin {
1786 tsadc_otp_out: tsadc-otp-out {
1793 uart0_xfer: uart0-xfer {
1799 uart0_cts: uart0-cts {
1804 uart0_rts: uart0-rts {
1809 uart0_rts_pin: uart0-rts-pin {
1816 uart1_xfer: uart1-xfer {
1822 uart1_cts: uart1-cts {
1827 uart1_rts: uart1-rts {
1833 uart2-m0 {
1834 uart2m0_xfer: uart2m0-xfer {
1841 uart2-m1 {
1842 uart2m1_xfer: uart2m1-xfer {
1850 uart3_xfer: uart3-xfer {
1857 uart3-m1 {
1858 uart3m1_xfer: uart3m1-xfer {
1866 uart4_xfer: uart4-xfer {
1872 uart4_cts: uart4-cts {
1877 uart4_rts: uart4-rts {
1882 uart4_rts_pin: uart4-rts-pin {