Lines Matching full:cru
6 #include <dt-bindings/clock/px30-cru.h>
46 clocks = <&cru ARMCLK>;
58 clocks = <&cru ARMCLK>;
70 clocks = <&cru ARMCLK>;
82 clocks = <&cru ARMCLK>;
269 clocks = <&cru HCLK_HOST>,
270 <&cru HCLK_OTG>,
271 <&cru SCLK_OTG_ADP>;
277 clocks = <&cru HCLK_SDMMC>,
278 <&cru SCLK_SDMMC>;
284 clocks = <&cru ACLK_GMAC>,
285 <&cru PCLK_GMAC>,
286 <&cru SCLK_MAC_REF>,
287 <&cru SCLK_GMAC_RX_TX>;
293 clocks = <&cru HCLK_NANDC>,
294 <&cru HCLK_EMMC>,
295 <&cru HCLK_SDIO>,
296 <&cru HCLK_SFC>,
297 <&cru SCLK_EMMC>,
298 <&cru SCLK_NANDC>,
299 <&cru SCLK_SDIO>,
300 <&cru SCLK_SFC>;
307 clocks = <&cru ACLK_VPU>,
308 <&cru HCLK_VPU>,
309 <&cru SCLK_CORE_VPU>;
315 clocks = <&cru ACLK_RGA>,
316 <&cru ACLK_VOPB>,
317 <&cru ACLK_VOPL>,
318 <&cru DCLK_VOPB>,
319 <&cru DCLK_VOPL>,
320 <&cru HCLK_RGA>,
321 <&cru HCLK_VOPB>,
322 <&cru HCLK_VOPL>,
323 <&cru PCLK_MIPI_DSI>,
324 <&cru SCLK_RGA_CORE>,
325 <&cru SCLK_VOPB_PWM>;
332 clocks = <&cru ACLK_CIF>,
333 <&cru ACLK_ISP>,
334 <&cru HCLK_CIF>,
335 <&cru HCLK_ISP>,
336 <&cru SCLK_ISP>;
344 clocks = <&cru SCLK_GPU>;
392 clocks = <&cru SCLK_I2S0_TX>, <&cru SCLK_I2S0_RX>, <&cru HCLK_I2S0>;
397 resets = <&cru SRST_I2S0_TX>, <&cru SRST_I2S0_RX>;
414 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>;
429 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>;
503 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
518 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
533 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
548 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
563 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
577 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
590 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
603 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
616 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
630 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
646 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
661 clocks = <&cru PCLK_WDT_NS>;
669 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
680 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
691 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
702 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
713 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
724 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
735 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
746 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
758 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
768 clocks = <&cru ACLK_DMAC>;
777 assigned-clocks = <&cru SCLK_TSADC>;
779 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
781 resets = <&cru SRST_TSADC>;
798 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
800 resets = <&cru SRST_SARADC_P>;
808 clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>,
809 <&cru PCLK_OTP_PHY>;
811 resets = <&cru SRST_OTP_PHY>;
829 cru: clock-controller@ff2b0000 {
830 compatible = "rockchip,px30-cru";
838 assigned-clocks = <&cru PLL_NPLL>,
839 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
840 <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>,
841 <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>;
879 assigned-clocks = <&cru USB480M>;
906 clocks = <&pmucru SCLK_MIPIDSIPHY_REF>, <&cru PCLK_MIPIDSIPHY>;
908 resets = <&cru SRST_MIPIDSIPHY_P>;
918 clocks = <&cru PCLK_MIPICSIPHY>;
922 resets = <&cru SRST_MIPICSIPHY_P>;
933 clocks = <&cru HCLK_OTG>;
949 clocks = <&cru HCLK_HOST>;
960 clocks = <&cru HCLK_HOST>;
972 clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>,
973 <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_MAC_REF>,
974 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
975 <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RMII>;
985 resets = <&cru SRST_GMAC_A>;
994 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
995 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
1010 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
1011 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
1026 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
1027 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
1042 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
1054 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
1056 assigned-clocks = <&cru SCLK_NANDC>;
1093 clocks = <&cru SCLK_GPU>;
1106 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
1116 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
1126 clocks = <&cru PCLK_MIPI_DSI>;
1131 resets = <&cru SRST_MIPIDSI_HOST_P>;
1168 clocks = <&cru ACLK_VOPB>, <&cru DCLK_VOPB>,
1169 <&cru HCLK_VOPB>;
1171 resets = <&cru SRST_VOPB_A>, <&cru SRST_VOPB_H>, <&cru SRST_VOPB>;
1197 clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>;
1208 clocks = <&cru ACLK_VOPL>, <&cru DCLK_VOPL>,
1209 <&cru HCLK_VOPL>;
1211 resets = <&cru SRST_VOPL_A>, <&cru SRST_VOPL_H>, <&cru SRST_VOPL>;
1237 clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>;
1251 clocks = <&cru SCLK_ISP>,
1252 <&cru ACLK_ISP>,
1253 <&cru HCLK_ISP>,
1254 <&cru PCLK_ISP>;
1278 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
1409 clocks = <&cru PCLK_GPIO1>;
1421 clocks = <&cru PCLK_GPIO2>;
1433 clocks = <&cru PCLK_GPIO3>;