Lines Matching +full:miso +full:- +full:pins
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
12 pinctrl-0 = <&sound_clk_pins>;
13 pinctrl-names = "default";
20 /* SW7 should be at position 2->3 so that GPIO8_CAN0_STB line is activated */
21 can0-stb-hog {
22 gpio-hog;
24 output-low;
25 line-name = "can0_stb";
33 /* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */
34 can1-stb-hog {
35 gpio-hog;
37 output-low;
38 line-name = "can1_stb";
42 pins = "RIIC0_SDA", "RIIC0_SCL";
43 input-enable;
47 pins = "RIIC1_SDA", "RIIC1_SCL";
48 input-enable;
57 mtu3-ext-clk-input-pin {
62 mtu3-pwm {
70 mtu3-zphase-clk {
88 sd1-pwr-en-hog {
89 gpio-hog;
91 output-high;
92 line-name = "sd1_pwr_en";
97 pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
98 power-source = <3300>;
102 pins = "SD1_CLK", "SD1_CMD";
103 power-source = <3300>;
113 pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
114 power-source = <1800>;
118 pins = "SD1_CLK", "SD1_CMD";
119 power-source = <1800>;
128 pins = "AUDIO_CLK1", "AUDIO_CLK2";
129 input-enable;
135 <RZG2L_PORT_PINMUX(44, 2, 1)>, /* MISO */