Lines Matching +full:r9a09g011 +full:- +full:xhci
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/r9a09g011-cpg.h>
12 compatible = "renesas,r9a09g011";
13 #address-cells = <2>;
14 #size-cells = <2>;
18 compatible = "fixed-clock";
19 #clock-cells = <0>;
21 clock-frequency = <0>;
25 #address-cells = <1>;
26 #size-cells = <0>;
28 cpu-map {
37 compatible = "arm,cortex-a53";
40 next-level-cache = <&L2_CA53>;
44 L2_CA53: cache-controller-0 {
46 cache-unified;
47 cache-level = <2>;
52 compatible = "simple-bus";
53 interrupt-parent = <&gic>;
54 #address-cells = <2>;
55 #size-cells = <2>;
58 gic: interrupt-controller@82010000 {
59 compatible = "arm,gic-400";
60 #interrupt-cells = <3>;
61 #address-cells = <0>;
62 interrupt-controller;
69 clock-names = "clk";
73 compatible = "renesas,sdhi-r9a09g011",
74 "renesas,rcar-gen3-sdhi";
82 clock-names = "core", "clkh", "cd", "aclk";
84 power-domains = <&cpg>;
89 compatible = "renesas,sdhi-r9a09g011",
90 "renesas,rcar-gen3-sdhi";
98 clock-names = "core", "clkh", "cd", "aclk";
100 power-domains = <&cpg>;
105 compatible = "renesas,sdhi-r9a09g011",
106 "renesas,rcar-gen3-sdhi";
114 clock-names = "core", "clkh", "cd", "aclk";
116 power-domains = <&cpg>;
121 compatible = "renesas,r9a09g011-usb3drd",
122 "renesas,rzv2m-usb3drd";
127 interrupt-names = "drd", "bc", "gpi";
130 clock-names = "axi", "reg";
132 power-domains = <&cpg>;
134 #address-cells = <2>;
135 #size-cells = <2>;
139 compatible = "renesas,r9a09g011-xhci",
140 "renesas,rzv2m-xhci";
145 clock-names = "axi", "reg";
147 power-domains = <&cpg>;
152 compatible = "renesas,r9a09g011-usb3-peri",
153 "renesas,rzv2m-usb3-peri";
158 clock-names = "axi", "reg";
160 power-domains = <&cpg>;
166 compatible = "renesas,etheravb-r9a09g011", "renesas,etheravb-rzv2m";
197 interrupt-names = "ch0", "ch1", "ch2", "ch3",
208 clock-names = "axi", "chi", "gptp";
210 power-domains = <&cpg>;
211 #address-cells = <1>;
212 #size-cells = <0>;
216 cpg: clock-controller@a3500000 {
217 compatible = "renesas,r9a09g011-cpg";
220 clock-names = "extal";
221 #clock-cells = <2>;
222 #reset-cells = <1>;
223 #power-domain-cells = <0>;
227 compatible = "renesas,r9a09g011-pwc", "renesas,rzv2m-pwc";
229 gpio-controller;
230 #gpio-cells = <2>;
234 sys: system-controller@a3f03000 {
235 compatible = "renesas,r9a09g011-sys";
240 compatible = "renesas,rzv2m-csi";
245 clock-names = "csiclk", "pclk";
247 power-domains = <&cpg>;
248 #address-cells = <1>;
249 #size-cells = <0>;
254 compatible = "renesas,rzv2m-csi";
259 clock-names = "csiclk", "pclk";
261 power-domains = <&cpg>;
262 #address-cells = <1>;
263 #size-cells = <0>;
268 #address-cells = <1>;
269 #size-cells = <0>;
270 compatible = "renesas,r9a09g011-i2c", "renesas,rzv2m-i2c";
274 interrupt-names = "tia", "tis";
277 power-domains = <&cpg>;
282 #address-cells = <1>;
283 #size-cells = <0>;
284 compatible = "renesas,r9a09g011-i2c", "renesas,rzv2m-i2c";
288 interrupt-names = "tia", "tis";
291 power-domains = <&cpg>;
296 compatible = "renesas,r9a09g011-uart", "renesas,em-uart";
301 clock-names = "sclk", "pclk";
306 compatible = "renesas,r9a09g011-wdt",
307 "renesas,rzv2m-wdt";
311 clock-names = "pclk", "oscclk";
314 power-domains = <&cpg>;
319 compatible = "renesas,r9a09g011-pinctrl";
321 gpio-controller;
322 #gpio-cells = <2>;
323 gpio-ranges = <&pinctrl 0 0 352>;
364 power-domains = <&cpg>;
370 compatible = "arm,armv8-timer";
371 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,