Lines Matching +full:rzg2l +full:- +full:irqc
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "arm,cortex-a55";
23 #cooling-cells = <2>;
24 next-level-cache = <&L3_CA55>;
25 enable-method = "psci";
27 operating-points-v2 = <&cluster0_opp>;
30 L3_CA55: cache-controller-0 {
32 cache-unified;
33 cache-size = <0x40000>;
34 cache-level = <3>;
39 compatible = "arm,cortex-a55-pmu";
40 interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
44 compatible = "arm,psci-1.0", "arm,psci-0.2";
49 compatible = "arm,armv8-timer";
50 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
58 interrupt-parent = <&irqc>;
62 interrupt-parent = <&gic>;
64 irqc: interrupt-controller@110a0000 { label
65 compatible = "renesas,r9a07g043u-irqc",
66 "renesas,rzg2l-irqc";
68 #interrupt-cells = <2>;
69 #address-cells = <0>;
70 interrupt-controller;
113 interrupt-names = "nmi",
124 "bus-err";
127 clock-names = "clk", "pclk";
128 power-domains = <&cpg>;
132 gic: interrupt-controller@11900000 {
133 compatible = "arm,gic-v3";
134 #interrupt-cells = <3>;
135 #address-cells = <0>;
136 interrupt-controller;
148 interrupt-names = "lpm_int", "ca55stbydone_int",