Lines Matching +full:r8a779f0 +full:- +full:ufs
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Device Tree Source for the R-Car S4-8 (R8A779F0) SoC
8 #include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a779f0-sysc.h>
13 compatible = "renesas,r8a779f0";
14 #address-cells = <2>;
15 #size-cells = <2>;
17 cluster01_opp: opp-table-0 {
18 compatible = "operating-points-v2";
19 opp-shared;
21 opp-500000000 {
22 opp-hz = /bits/ 64 <500000000>;
23 opp-microvolt = <880000>;
24 clock-latency-ns = <500000>;
26 opp-800000000 {
27 opp-hz = /bits/ 64 <800000000>;
28 opp-microvolt = <880000>;
29 clock-latency-ns = <500000>;
31 opp-1000000000 {
32 opp-hz = /bits/ 64 <1000000000>;
33 opp-microvolt = <880000>;
34 clock-latency-ns = <500000>;
36 opp-1200000000 {
37 opp-hz = /bits/ 64 <1200000000>;
38 opp-microvolt = <880000>;
39 clock-latency-ns = <500000>;
40 opp-suspend;
44 cluster23_opp: opp-table-1 {
45 compatible = "operating-points-v2";
46 opp-shared;
48 opp-500000000 {
49 opp-hz = /bits/ 64 <500000000>;
50 opp-microvolt = <880000>;
51 clock-latency-ns = <500000>;
53 opp-800000000 {
54 opp-hz = /bits/ 64 <800000000>;
55 opp-microvolt = <880000>;
56 clock-latency-ns = <500000>;
58 opp-1000000000 {
59 opp-hz = /bits/ 64 <1000000000>;
60 opp-microvolt = <880000>;
61 clock-latency-ns = <500000>;
63 opp-1200000000 {
64 opp-hz = /bits/ 64 <1200000000>;
65 opp-microvolt = <880000>;
66 clock-latency-ns = <500000>;
67 opp-suspend;
72 #address-cells = <1>;
73 #size-cells = <0>;
75 cpu-map {
114 compatible = "arm,cortex-a55";
117 power-domains = <&sysc R8A779F0_PD_A1E0D0C0>;
118 next-level-cache = <&L3_CA55_0>;
119 enable-method = "psci";
120 cpu-idle-states = <&CPU_SLEEP_0>;
122 operating-points-v2 = <&cluster01_opp>;
126 compatible = "arm,cortex-a55";
129 power-domains = <&sysc R8A779F0_PD_A1E0D0C1>;
130 next-level-cache = <&L3_CA55_0>;
131 enable-method = "psci";
132 cpu-idle-states = <&CPU_SLEEP_0>;
134 operating-points-v2 = <&cluster01_opp>;
138 compatible = "arm,cortex-a55";
141 power-domains = <&sysc R8A779F0_PD_A1E0D1C0>;
142 next-level-cache = <&L3_CA55_1>;
143 enable-method = "psci";
144 cpu-idle-states = <&CPU_SLEEP_0>;
146 operating-points-v2 = <&cluster01_opp>;
150 compatible = "arm,cortex-a55";
153 power-domains = <&sysc R8A779F0_PD_A1E0D1C1>;
154 next-level-cache = <&L3_CA55_1>;
155 enable-method = "psci";
156 cpu-idle-states = <&CPU_SLEEP_0>;
158 operating-points-v2 = <&cluster01_opp>;
162 compatible = "arm,cortex-a55";
165 power-domains = <&sysc R8A779F0_PD_A1E1D0C0>;
166 next-level-cache = <&L3_CA55_2>;
167 enable-method = "psci";
168 cpu-idle-states = <&CPU_SLEEP_0>;
170 operating-points-v2 = <&cluster23_opp>;
174 compatible = "arm,cortex-a55";
177 power-domains = <&sysc R8A779F0_PD_A1E1D0C1>;
178 next-level-cache = <&L3_CA55_2>;
179 enable-method = "psci";
180 cpu-idle-states = <&CPU_SLEEP_0>;
182 operating-points-v2 = <&cluster23_opp>;
186 compatible = "arm,cortex-a55";
189 power-domains = <&sysc R8A779F0_PD_A1E1D1C0>;
190 next-level-cache = <&L3_CA55_3>;
191 enable-method = "psci";
192 cpu-idle-states = <&CPU_SLEEP_0>;
194 operating-points-v2 = <&cluster23_opp>;
198 compatible = "arm,cortex-a55";
201 power-domains = <&sysc R8A779F0_PD_A1E1D1C1>;
202 next-level-cache = <&L3_CA55_3>;
203 enable-method = "psci";
204 cpu-idle-states = <&CPU_SLEEP_0>;
206 operating-points-v2 = <&cluster23_opp>;
209 L3_CA55_0: cache-controller-0 {
211 power-domains = <&sysc R8A779F0_PD_A2E0D0>;
212 cache-unified;
213 cache-level = <3>;
216 L3_CA55_1: cache-controller-1 {
218 power-domains = <&sysc R8A779F0_PD_A2E0D1>;
219 cache-unified;
220 cache-level = <3>;
223 L3_CA55_2: cache-controller-2 {
225 power-domains = <&sysc R8A779F0_PD_A2E1D0>;
226 cache-unified;
227 cache-level = <3>;
230 L3_CA55_3: cache-controller-3 {
232 power-domains = <&sysc R8A779F0_PD_A2E1D1>;
233 cache-unified;
234 cache-level = <3>;
237 idle-states {
238 entry-method = "psci";
240 CPU_SLEEP_0: cpu-sleep-0 {
241 compatible = "arm,idle-state";
242 arm,psci-suspend-param = <0x0010000>;
243 local-timer-stop;
244 entry-latency-us = <400>;
245 exit-latency-us = <500>;
246 min-residency-us = <4000>;
252 compatible = "fixed-clock";
253 #clock-cells = <0>;
255 clock-frequency = <0>;
259 compatible = "fixed-clock";
260 #clock-cells = <0>;
262 clock-frequency = <0>;
265 pcie0_clkref: pcie0-clkref {
266 compatible = "fixed-clock";
267 #clock-cells = <0>;
269 clock-frequency = <0>;
272 pcie1_clkref: pcie1-clkref {
273 compatible = "fixed-clock";
274 #clock-cells = <0>;
276 clock-frequency = <0>;
280 compatible = "arm,cortex-a55-pmu";
281 interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
285 compatible = "arm,psci-1.0", "arm,psci-0.2";
289 /* External SCIF clock - to be overridden by boards that provide it */
291 compatible = "fixed-clock";
292 #clock-cells = <0>;
293 clock-frequency = <0>;
297 compatible = "simple-bus";
298 interrupt-parent = <&gic>;
299 #address-cells = <2>;
300 #size-cells = <2>;
304 compatible = "renesas,r8a779f0-wdt",
305 "renesas,rcar-gen4-wdt";
309 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
315 compatible = "renesas,pfc-r8a779f0";
321 compatible = "renesas,gpio-r8a779f0",
322 "renesas,rcar-gen4-gpio";
326 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
328 gpio-controller;
329 #gpio-cells = <2>;
330 gpio-ranges = <&pfc 0 0 21>;
331 interrupt-controller;
332 #interrupt-cells = <2>;
336 compatible = "renesas,gpio-r8a779f0",
337 "renesas,rcar-gen4-gpio";
341 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
343 gpio-controller;
344 #gpio-cells = <2>;
345 gpio-ranges = <&pfc 0 32 25>;
346 interrupt-controller;
347 #interrupt-cells = <2>;
351 compatible = "renesas,gpio-r8a779f0",
352 "renesas,rcar-gen4-gpio";
356 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
358 gpio-controller;
359 #gpio-cells = <2>;
360 gpio-ranges = <&pfc 0 64 17>;
361 interrupt-controller;
362 #interrupt-cells = <2>;
366 compatible = "renesas,gpio-r8a779f0",
367 "renesas,rcar-gen4-gpio";
371 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
373 gpio-controller;
374 #gpio-cells = <2>;
375 gpio-ranges = <&pfc 0 96 19>;
376 interrupt-controller;
377 #interrupt-cells = <2>;
381 compatible = "renesas,r8a779f0-cmt0",
382 "renesas,rcar-gen4-cmt0";
387 clock-names = "fck";
388 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
394 compatible = "renesas,r8a779f0-cmt1",
395 "renesas,rcar-gen4-cmt1";
406 clock-names = "fck";
407 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
413 compatible = "renesas,r8a779f0-cmt1",
414 "renesas,rcar-gen4-cmt1";
425 clock-names = "fck";
426 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
432 compatible = "renesas,r8a779f0-cmt1",
433 "renesas,rcar-gen4-cmt1";
444 clock-names = "fck";
445 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
450 cpg: clock-controller@e6150000 {
451 compatible = "renesas,r8a779f0-cpg-mssr";
454 clock-names = "extal", "extalr";
455 #clock-cells = <2>;
456 #power-domain-cells = <0>;
457 #reset-cells = <1>;
460 rst: reset-controller@e6160000 {
461 compatible = "renesas,r8a779f0-rst";
465 sysc: system-controller@e6180000 {
466 compatible = "renesas,r8a779f0-sysc";
468 #power-domain-cells = <1>;
472 compatible = "renesas,r8a779f0-thermal";
478 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
480 #thermal-sensor-cells = <1>;
483 intc_ex: interrupt-controller@e61c0000 {
484 compatible = "renesas,intc-ex-r8a779f0", "renesas,irqc";
485 #interrupt-cells = <2>;
486 interrupt-controller;
495 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
499 compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
505 clock-names = "fck";
506 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
512 compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
518 clock-names = "fck";
519 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
525 compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
531 clock-names = "fck";
532 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
538 compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
544 clock-names = "fck";
545 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
551 compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
557 clock-names = "fck";
558 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
564 compatible = "renesas,r8a779f0-ether-serdes";
567 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
569 #phy-cells = <1>;
574 compatible = "renesas,i2c-r8a779f0",
575 "renesas,rcar-gen4-i2c";
579 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
583 dma-names = "tx", "rx", "tx", "rx";
584 i2c-scl-internal-delay-ns = <110>;
585 #address-cells = <1>;
586 #size-cells = <0>;
591 compatible = "renesas,i2c-r8a779f0",
592 "renesas,rcar-gen4-i2c";
596 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
600 dma-names = "tx", "rx", "tx", "rx";
601 i2c-scl-internal-delay-ns = <110>;
602 #address-cells = <1>;
603 #size-cells = <0>;
608 compatible = "renesas,i2c-r8a779f0",
609 "renesas,rcar-gen4-i2c";
613 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
617 dma-names = "tx", "rx", "tx", "rx";
618 i2c-scl-internal-delay-ns = <110>;
619 #address-cells = <1>;
620 #size-cells = <0>;
625 compatible = "renesas,i2c-r8a779f0",
626 "renesas,rcar-gen4-i2c";
630 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
634 dma-names = "tx", "rx", "tx", "rx";
635 i2c-scl-internal-delay-ns = <110>;
636 #address-cells = <1>;
637 #size-cells = <0>;
642 compatible = "renesas,i2c-r8a779f0",
643 "renesas,rcar-gen4-i2c";
647 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
651 dma-names = "tx", "rx", "tx", "rx";
652 i2c-scl-internal-delay-ns = <110>;
653 #address-cells = <1>;
654 #size-cells = <0>;
659 compatible = "renesas,i2c-r8a779f0",
660 "renesas,rcar-gen4-i2c";
664 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
668 dma-names = "tx", "rx", "tx", "rx";
669 i2c-scl-internal-delay-ns = <110>;
670 #address-cells = <1>;
671 #size-cells = <0>;
676 compatible = "renesas,hscif-r8a779f0",
677 "renesas,rcar-gen4-hscif", "renesas,hscif";
683 clock-names = "fck", "brg_int", "scif_clk";
686 dma-names = "tx", "rx", "tx", "rx";
687 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
693 compatible = "renesas,hscif-r8a779f0",
694 "renesas,rcar-gen4-hscif", "renesas,hscif";
700 clock-names = "fck", "brg_int", "scif_clk";
703 dma-names = "tx", "rx", "tx", "rx";
704 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
710 compatible = "renesas,hscif-r8a779f0",
711 "renesas,rcar-gen4-hscif", "renesas,hscif";
717 clock-names = "fck", "brg_int", "scif_clk";
720 dma-names = "tx", "rx", "tx", "rx";
721 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
727 compatible = "renesas,hscif-r8a779f0",
728 "renesas,rcar-gen4-hscif", "renesas,hscif";
734 clock-names = "fck", "brg_int", "scif_clk";
737 dma-names = "tx", "rx", "tx", "rx";
738 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
744 compatible = "renesas,r8a779f0-pcie",
745 "renesas,rcar-gen4-pcie";
750 reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "config";
755 interrupt-names = "msi", "dma", "sft_ce", "app";
757 clock-names = "core", "ref";
758 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
760 reset-names = "pwr";
761 max-link-speed = <4>;
762 num-lanes = <2>;
763 #address-cells = <3>;
764 #size-cells = <2>;
765 bus-range = <0x00 0xff>;
769 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
770 #interrupt-cells = <1>;
771 interrupt-map-mask = <0 0 0 7>;
772 interrupt-map = <0 0 0 1 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
776 snps,enable-cdm-check;
781 compatible = "renesas,r8a779f0-pcie",
782 "renesas,rcar-gen4-pcie";
787 reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "config";
792 interrupt-names = "msi", "dma", "sft_ce", "app";
794 clock-names = "core", "ref";
795 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
797 reset-names = "pwr";
798 max-link-speed = <4>;
799 num-lanes = <2>;
800 #address-cells = <3>;
801 #size-cells = <2>;
802 bus-range = <0x00 0xff>;
806 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
807 #interrupt-cells = <1>;
808 interrupt-map-mask = <0 0 0 7>;
809 interrupt-map = <0 0 0 1 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
813 snps,enable-cdm-check;
817 pciec0_ep: pcie-ep@e65d0000 {
818 compatible = "renesas,r8a779f0-pcie-ep",
819 "renesas,rcar-gen4-pcie-ep";
824 reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "addr_space";
828 interrupt-names = "dma", "sft_ce", "app";
830 clock-names = "core", "ref";
831 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
833 reset-names = "pwr";
834 max-link-speed = <4>;
835 num-lanes = <2>;
836 max-functions = /bits/ 8 <2>;
840 pciec1_ep: pcie-ep@e65d8000 {
841 compatible = "renesas,r8a779f0-pcie-ep",
842 "renesas,rcar-gen4-pcie-ep";
847 reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "addr_space";
851 interrupt-names = "dma", "sft_ce", "app";
853 clock-names = "core", "ref";
854 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
856 reset-names = "pwr";
857 max-link-speed = <4>;
858 num-lanes = <2>;
859 max-functions = /bits/ 8 <2>;
863 ufs: ufs@e6860000 {
864 compatible = "renesas,r8a779f0-ufs";
868 clock-names = "fck", "ref_clk";
869 freq-table-hz = <200000000 200000000>, <38400000 38400000>;
870 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
876 compatible = "renesas,r8a779f0-ether-switch";
878 reg-names = "base", "secure_base";
926 interrupt-names = "mfwd_error", "race_error",
952 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
956 ethernet-ports {
957 #address-cells = <1>;
958 #size-cells = <0>;
976 compatible = "renesas,scif-r8a779f0",
977 "renesas,rcar-gen4-scif", "renesas,scif";
983 clock-names = "fck", "brg_int", "scif_clk";
986 dma-names = "tx", "rx", "tx", "rx";
987 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
993 compatible = "renesas,scif-r8a779f0",
994 "renesas,rcar-gen4-scif", "renesas,scif";
1000 clock-names = "fck", "brg_int", "scif_clk";
1003 dma-names = "tx", "rx", "tx", "rx";
1004 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1010 compatible = "renesas,scif-r8a779f0",
1011 "renesas,rcar-gen4-scif", "renesas,scif";
1017 clock-names = "fck", "brg_int", "scif_clk";
1020 dma-names = "tx", "rx", "tx", "rx";
1021 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1027 compatible = "renesas,scif-r8a779f0",
1028 "renesas,rcar-gen4-scif", "renesas,scif";
1034 clock-names = "fck", "brg_int", "scif_clk";
1037 dma-names = "tx", "rx", "tx", "rx";
1038 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1044 compatible = "renesas,msiof-r8a779f0",
1045 "renesas,rcar-gen4-msiof";
1051 dma-names = "tx", "rx", "tx", "rx";
1052 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1054 #address-cells = <1>;
1055 #size-cells = <0>;
1060 compatible = "renesas,msiof-r8a779f0",
1061 "renesas,rcar-gen4-msiof";
1067 dma-names = "tx", "rx", "tx", "rx";
1068 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1070 #address-cells = <1>;
1071 #size-cells = <0>;
1076 compatible = "renesas,msiof-r8a779f0",
1077 "renesas,rcar-gen4-msiof";
1083 dma-names = "tx", "rx", "tx", "rx";
1084 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1086 #address-cells = <1>;
1087 #size-cells = <0>;
1092 compatible = "renesas,msiof-r8a779f0",
1093 "renesas,rcar-gen4-msiof";
1099 dma-names = "tx", "rx", "tx", "rx";
1100 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1102 #address-cells = <1>;
1103 #size-cells = <0>;
1107 dmac0: dma-controller@e7350000 {
1108 compatible = "renesas,dmac-r8a779f0",
1109 "renesas,rcar-gen4-dmac";
1129 interrupt-names = "error",
1135 clock-names = "fck";
1136 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1138 #dma-cells = <1>;
1139 dma-channels = <16>;
1150 dmac1: dma-controller@e7351000 {
1151 compatible = "renesas,dmac-r8a779f0",
1152 "renesas,rcar-gen4-dmac";
1172 interrupt-names = "error",
1178 clock-names = "fck";
1179 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1181 #dma-cells = <1>;
1182 dma-channels = <16>;
1194 compatible = "renesas,sdhi-r8a779f0",
1195 "renesas,rcar-gen4-sdhi";
1199 clock-names = "core", "clkh";
1200 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1202 max-frequency = <200000000>;
1208 compatible = "renesas,ipmmu-r8a779f0",
1209 "renesas,rcar-gen4-ipmmu-vmsa";
1211 renesas,ipmmu-main = <&ipmmu_mm>;
1212 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1213 #iommu-cells = <1>;
1217 compatible = "renesas,ipmmu-r8a779f0",
1218 "renesas,rcar-gen4-ipmmu-vmsa";
1220 renesas,ipmmu-main = <&ipmmu_mm>;
1221 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1222 #iommu-cells = <1>;
1226 compatible = "renesas,ipmmu-r8a779f0",
1227 "renesas,rcar-gen4-ipmmu-vmsa";
1229 renesas,ipmmu-main = <&ipmmu_mm>;
1230 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1231 #iommu-cells = <1>;
1235 compatible = "renesas,ipmmu-r8a779f0",
1236 "renesas,rcar-gen4-ipmmu-vmsa";
1238 renesas,ipmmu-main = <&ipmmu_mm>;
1239 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1240 #iommu-cells = <1>;
1244 compatible = "renesas,ipmmu-r8a779f0",
1245 "renesas,rcar-gen4-ipmmu-vmsa";
1249 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1250 #iommu-cells = <1>;
1253 gic: interrupt-controller@f1000000 {
1254 compatible = "arm,gic-v3";
1255 #interrupt-cells = <3>;
1256 #address-cells = <0>;
1257 interrupt-controller;
1269 thermal-zones {
1270 sensor_thermal_rtcore: sensor1-thermal {
1271 polling-delay-passive = <250>;
1272 polling-delay = <1000>;
1273 thermal-sensors = <&tsc 0>;
1276 sensor1_crit: sensor1-crit {
1284 sensor_thermal_apcore0: sensor2-thermal {
1285 polling-delay-passive = <250>;
1286 polling-delay = <1000>;
1287 thermal-sensors = <&tsc 1>;
1290 sensor2_crit: sensor2-crit {
1298 sensor_thermal_apcore4: sensor3-thermal {
1299 polling-delay-passive = <250>;
1300 polling-delay = <1000>;
1301 thermal-sensors = <&tsc 2>;
1304 sensor3_crit: sensor3-crit {
1314 compatible = "arm,armv8-timer";
1315 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
1321 ufs30_clk: ufs30-clk {
1322 compatible = "fixed-clock";
1323 #clock-cells = <0>;
1325 clock-frequency = <0>;