Lines Matching +full:0 +full:xe6550000
17 cluster01_opp: opp-table-0 {
73 #size-cells = <0>;
113 a55_0: cpu@0 {
115 reg = <0>;
127 reg = <0x100>;
139 reg = <0x10000>;
151 reg = <0x10100>;
163 reg = <0x20000>;
175 reg = <0x20100>;
187 reg = <0x30000>;
199 reg = <0x30100>;
209 L3_CA55_0: cache-controller-0 {
240 CPU_SLEEP_0: cpu-sleep-0 {
242 arm,psci-suspend-param = <0x0010000>;
253 #clock-cells = <0>;
255 clock-frequency = <0>;
260 #clock-cells = <0>;
262 clock-frequency = <0>;
267 #clock-cells = <0>;
269 clock-frequency = <0>;
274 #clock-cells = <0>;
276 clock-frequency = <0>;
292 #clock-cells = <0>;
293 clock-frequency = <0>;
306 reg = <0 0xe6020000 0 0x0c>;
316 reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>,
317 <0 0xe6051000 0 0x16c>, <0 0xe6051800 0 0x16c>;
323 reg = <0 0xe6050180 0 0x54>;
330 gpio-ranges = <&pfc 0 0 21>;
338 reg = <0 0xe6050980 0 0x54>;
345 gpio-ranges = <&pfc 0 32 25>;
353 reg = <0 0xe6051180 0 0x54>;
360 gpio-ranges = <&pfc 0 64 17>;
368 reg = <0 0xe6051980 0 0x54>;
375 gpio-ranges = <&pfc 0 96 19>;
383 reg = <0 0xe60f0000 0 0x1004>;
396 reg = <0 0xe6130000 0 0x1004>;
415 reg = <0 0xe6140000 0 0x1004>;
434 reg = <0 0xe6148000 0 0x1004>;
452 reg = <0 0xe6150000 0 0x4000>;
456 #power-domain-cells = <0>;
462 reg = <0 0xe6160000 0 0x4000>;
467 reg = <0 0xe6180000 0 0x4000>;
474 reg = <0 0xe6198000 0 0x200>,
475 <0 0xe61a0000 0 0x200>,
476 <0 0xe61a8000 0 0x200>;
487 reg = <0 0xe61c0000 0 0x200>;
488 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
500 reg = <0 0xe61e0000 0 0x30>;
513 reg = <0 0xe6fc0000 0 0x30>;
526 reg = <0 0xe6fd0000 0 0x30>;
539 reg = <0 0xe6fe0000 0 0x30>;
552 reg = <0 0xffc00000 0 0x30>;
565 reg = <0 0xe6444000 0 0x2800>;
576 reg = <0 0xe6500000 0 0x40>;
581 dmas = <&dmac0 0x91>, <&dmac0 0x90>,
582 <&dmac1 0x91>, <&dmac1 0x90>;
586 #size-cells = <0>;
593 reg = <0 0xe6508000 0 0x40>;
598 dmas = <&dmac0 0x93>, <&dmac0 0x92>,
599 <&dmac1 0x93>, <&dmac1 0x92>;
603 #size-cells = <0>;
610 reg = <0 0xe6510000 0 0x40>;
611 interrupts = <0 240 IRQ_TYPE_LEVEL_HIGH>;
615 dmas = <&dmac0 0x95>, <&dmac0 0x94>,
616 <&dmac1 0x95>, <&dmac1 0x94>;
620 #size-cells = <0>;
627 reg = <0 0xe66d0000 0 0x40>;
632 dmas = <&dmac0 0x97>, <&dmac0 0x96>,
633 <&dmac1 0x97>, <&dmac1 0x96>;
637 #size-cells = <0>;
644 reg = <0 0xe66d8000 0 0x40>;
649 dmas = <&dmac0 0x99>, <&dmac0 0x98>,
650 <&dmac1 0x99>, <&dmac1 0x98>;
654 #size-cells = <0>;
661 reg = <0 0xe66e0000 0 0x40>;
666 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>,
667 <&dmac1 0x9b>, <&dmac1 0x9a>;
671 #size-cells = <0>;
678 reg = <0 0xe6540000 0 0x60>;
684 dmas = <&dmac0 0x31>, <&dmac0 0x30>,
685 <&dmac1 0x31>, <&dmac1 0x30>;
695 reg = <0 0xe6550000 0 0x60>;
701 dmas = <&dmac0 0x33>, <&dmac0 0x32>,
702 <&dmac1 0x33>, <&dmac1 0x32>;
712 reg = <0 0xe6560000 0 0x60>;
718 dmas = <&dmac0 0x35>, <&dmac0 0x34>,
719 <&dmac1 0x35>, <&dmac1 0x34>;
729 reg = <0 0xe66a0000 0 0x60>;
735 dmas = <&dmac0 0x37>, <&dmac0 0x36>,
736 <&dmac1 0x37>, <&dmac1 0x36>;
746 reg = <0 0xe65d0000 0 0x1000>, <0 0xe65d2000 0 0x0800>,
747 <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>,
748 <0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>,
749 <0 0xfe000000 0 0x400000>;
765 bus-range = <0x00 0xff>;
767 ranges = <0x01000000 0 0x00000000 0 0xfe000000 0 0x00400000>,
768 <0x02000000 0 0x30000000 0 0x30000000 0 0x10000000>;
769 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
771 interrupt-map-mask = <0 0 0 7>;
772 interrupt-map = <0 0 0 1 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
773 <0 0 0 2 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
774 <0 0 0 3 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
775 <0 0 0 4 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>;
783 reg = <0 0xe65d8000 0 0x1000>, <0 0xe65da000 0 0x0800>,
784 <0 0xe65db000 0 0x2000>, <0 0xe65dd000 0 0x1200>,
785 <0 0xe65de200 0 0x0e00>, <0 0xe65df000 0 0x0400>,
786 <0 0xee900000 0 0x400000>;
802 bus-range = <0x00 0xff>;
804 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00400000>,
805 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x10000000>;
806 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
808 interrupt-map-mask = <0 0 0 7>;
809 interrupt-map = <0 0 0 1 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
810 <0 0 0 2 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
811 <0 0 0 3 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
812 <0 0 0 4 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>;
820 reg = <0 0xe65d0000 0 0x2000>, <0 0xe65d2000 0 0x1000>,
821 <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>,
822 <0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>,
823 <0 0xfe000000 0 0x400000>;
843 reg = <0 0xe65d8000 0 0x2000>, <0 0xe65da000 0 0x1000>,
844 <0 0xe65db000 0 0x2000>, <0 0xe65dd000 0 0x1200>,
845 <0 0xe65de200 0 0x0e00>, <0 0xe65df000 0 0x0400>,
846 <0 0xee900000 0 0x400000>;
865 reg = <0 0xe6860000 0 0x100>;
877 reg = <0 0xe6880000 0 0x20000>, <0 0xe68c0000 0 0x20000>;
958 #size-cells = <0>;
960 port@0 {
961 reg = <0>;
962 phys = <ð_serdes 0>;
978 reg = <0 0xe6e60000 0 64>;
984 dmas = <&dmac0 0x51>, <&dmac0 0x50>,
985 <&dmac1 0x51>, <&dmac1 0x50>;
995 reg = <0 0xe6e68000 0 64>;
1001 dmas = <&dmac0 0x53>, <&dmac0 0x52>,
1002 <&dmac1 0x53>, <&dmac1 0x52>;
1012 reg = <0 0xe6c50000 0 64>;
1018 dmas = <&dmac0 0x57>, <&dmac0 0x56>,
1019 <&dmac1 0x57>, <&dmac1 0x56>;
1029 reg = <0 0xe6c40000 0 64>;
1035 dmas = <&dmac0 0x59>, <&dmac0 0x58>,
1036 <&dmac1 0x59>, <&dmac1 0x58>;
1046 reg = <0 0xe6e90000 0 0x0064>;
1049 dmas = <&dmac0 0x41>, <&dmac0 0x40>,
1050 <&dmac1 0x41>, <&dmac1 0x40>;
1055 #size-cells = <0>;
1062 reg = <0 0xe6ea0000 0 0x0064>;
1065 dmas = <&dmac0 0x43>, <&dmac0 0x42>,
1066 <&dmac1 0x43>, <&dmac1 0x42>;
1071 #size-cells = <0>;
1078 reg = <0 0xe6c00000 0 0x0064>;
1081 dmas = <&dmac0 0x45>, <&dmac0 0x44>,
1082 <&dmac1 0x45>, <&dmac1 0x44>;
1087 #size-cells = <0>;
1094 reg = <0 0xe6c10000 0 0x0064>;
1097 dmas = <&dmac0 0x47>, <&dmac0 0x46>,
1098 <&dmac1 0x47>, <&dmac1 0x46>;
1103 #size-cells = <0>;
1110 reg = <0 0xe7350000 0 0x1000>,
1111 <0 0xe7300000 0 0x10000>;
1140 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
1153 reg = <0 0xe7351000 0 0x1000>,
1154 <0 0xe7310000 0 0x10000>;
1196 reg = <0 0xee140000 0 0x2000>;
1210 reg = <0 0xee480000 0 0x20000>;
1219 reg = <0 0xee4c0000 0 0x20000>;
1228 reg = <0 0xeed00000 0 0x20000>;
1237 reg = <0 0xeed40000 0 0x20000>;
1246 reg = <0 0xeefc0000 0 0x20000>;
1256 #address-cells = <0>;
1258 reg = <0x0 0xf1000000 0 0x20000>,
1259 <0x0 0xf1060000 0 0x110000>;
1265 reg = <0 0xfff00044 0 4>;
1273 thermal-sensors = <&tsc 0>;
1323 #clock-cells = <0>;
1325 clock-frequency = <0>;