Lines Matching +full:0 +full:xe6180000
20 #clock-cells = <0>;
21 clock-frequency = <0>;
26 #size-cells = <0>;
28 a76_0: cpu@0 {
30 reg = <0>;
37 L3_CA76_0: cache-controller-0 {
47 #clock-cells = <0>;
49 clock-frequency = <0>;
54 #clock-cells = <0>;
56 clock-frequency = <0>;
67 #clock-cells = <0>;
68 clock-frequency = <0>;
81 reg = <0 0xe6020000 0 0x0c>;
91 reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>,
92 <0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>,
93 <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>,
94 <0 0xe6068000 0 0x16c>, <0 0xe6068800 0 0x16c>,
95 <0 0xe6069000 0 0x16c>, <0 0xe6069800 0 0x16c>;
101 reg = <0 0xe6058180 0 0x54>;
108 gpio-ranges = <&pfc 0 0 28>;
116 reg = <0 0xe6050180 0 0x54>;
123 gpio-ranges = <&pfc 0 32 31>;
131 reg = <0 0xe6050980 0 0x54>;
138 gpio-ranges = <&pfc 0 64 25>;
146 reg = <0 0xe6058980 0 0x54>;
153 gpio-ranges = <&pfc 0 96 17>;
161 reg = <0 0xe6060180 0 0x54>;
168 gpio-ranges = <&pfc 0 128 27>;
176 reg = <0 0xe6060980 0 0x54>;
183 gpio-ranges = <&pfc 0 160 21>;
191 reg = <0 0xe6068180 0 0x54>;
198 gpio-ranges = <&pfc 0 192 21>;
206 reg = <0 0xe6068980 0 0x54>;
213 gpio-ranges = <&pfc 0 224 21>;
221 reg = <0 0xe6069180 0 0x54>;
228 gpio-ranges = <&pfc 0 256 21>;
236 reg = <0 0xe6069980 0 0x54>;
243 gpio-ranges = <&pfc 0 288 21>;
251 reg = <0 0xe60f0000 0 0x1004>;
264 reg = <0 0xe6130000 0 0x1004>;
283 reg = <0 0xe6140000 0 0x1004>;
302 reg = <0 0xe6148000 0 0x1004>;
320 reg = <0 0xe6150000 0 0x4000>;
324 #power-domain-cells = <0>;
330 reg = <0 0xe6160000 0 0x4000>;
335 reg = <0 0xe6180000 0 0x4000>;
341 reg = <0 0xe6190000 0 0x200>,
342 <0 0xe6198000 0 0x200>,
343 <0 0xe61a0000 0 0x200>,
344 <0 0xe61a8000 0 0x200>,
345 <0 0xe61b0000 0 0x200>;
356 reg = <0 0xe61c0000 0 0x200>;
357 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
369 reg = <0 0xe61e0000 0 0x30>;
382 reg = <0 0xe6fc0000 0 0x30>;
395 reg = <0 0xe6fd0000 0 0x30>;
408 reg = <0 0xe6fe0000 0 0x30>;
421 reg = <0 0xffc00000 0 0x30>;
435 reg = <0 0xe6500000 0 0x40>;
440 dmas = <&dmac1 0x91>, <&dmac1 0x90>;
444 #size-cells = <0>;
451 reg = <0 0xe6508000 0 0x40>;
456 dmas = <&dmac1 0x93>, <&dmac1 0x92>;
460 #size-cells = <0>;
467 reg = <0 0xe6510000 0 0x40>;
472 dmas = <&dmac1 0x95>, <&dmac1 0x94>;
476 #size-cells = <0>;
483 reg = <0 0xe66d0000 0 0x40>;
488 dmas = <&dmac1 0x97>, <&dmac1 0x96>;
492 #size-cells = <0>;
499 reg = <0 0xe66d8000 0 0x40>;
504 dmas = <&dmac1 0x99>, <&dmac1 0x98>;
508 #size-cells = <0>;
515 reg = <0 0xe66e0000 0 0x40>;
520 dmas = <&dmac1 0x9b>, <&dmac1 0x9a>;
524 #size-cells = <0>;
531 reg = <0 0xe66e8000 0 0x40>;
536 dmas = <&dmac1 0x9d>, <&dmac1 0x9c>;
540 #size-cells = <0>;
547 reg = <0 0xe6540000 0 0x60>;
553 dmas = <&dmac1 0x31>, <&dmac1 0x30>;
563 reg = <0 0xe6550000 0 0x60>;
569 dmas = <&dmac1 0x33>, <&dmac1 0x32>;
579 reg = <0 0xe6560000 0 0x60>;
585 dmas = <&dmac1 0x35>, <&dmac1 0x34>;
595 reg = <0 0xe66a0000 0 0x60>;
601 dmas = <&dmac1 0x37>, <&dmac1 0x36>;
611 reg = <0 0xe6660000 0 0x8000>;
661 reg = <0 0xe6800000 0 0x800>;
699 rx-internal-delay-ps = <0>;
700 tx-internal-delay-ps = <0>;
702 #size-cells = <0>;
709 reg = <0 0xe6810000 0 0x800>;
747 rx-internal-delay-ps = <0>;
748 tx-internal-delay-ps = <0>;
750 #size-cells = <0>;
757 reg = <0 0xe6820000 0 0x1000>;
795 rx-internal-delay-ps = <0>;
796 tx-internal-delay-ps = <0>;
798 #size-cells = <0>;
805 reg = <0 0xe6830000 0 0x1000>;
843 rx-internal-delay-ps = <0>;
844 tx-internal-delay-ps = <0>;
846 #size-cells = <0>;
853 reg = <0 0xe6840000 0 0x1000>;
891 rx-internal-delay-ps = <0>;
892 tx-internal-delay-ps = <0>;
894 #size-cells = <0>;
901 reg = <0 0xe6850000 0 0x1000>;
939 rx-internal-delay-ps = <0>;
940 tx-internal-delay-ps = <0>;
942 #size-cells = <0>;
948 reg = <0 0xe6e30000 0 0x10>;
958 reg = <0 0xe6e31000 0 0x10>;
968 reg = <0 0xe6e32000 0 0x10>;
978 reg = <0 0xe6e33000 0 0x10>;
988 reg = <0 0xe6e34000 0 0x10>;
999 reg = <0 0xe6e60000 0 64>;
1005 dmas = <&dmac1 0x51>, <&dmac1 0x50>;
1015 reg = <0 0xe6e68000 0 64>;
1021 dmas = <&dmac1 0x53>, <&dmac1 0x52>;
1031 reg = <0 0xe6c50000 0 64>;
1037 dmas = <&dmac1 0x57>, <&dmac1 0x56>;
1047 reg = <0 0xe6c40000 0 64>;
1053 dmas = <&dmac1 0x59>, <&dmac1 0x58>;
1062 reg = <0 0xe6e80000 0 0x148>;
1074 reg = <0 0xe6e90000 0 0x0064>;
1079 dmas = <&dmac1 0x41>, <&dmac1 0x40>;
1082 #size-cells = <0>;
1089 reg = <0 0xe6ea0000 0 0x0064>;
1094 dmas = <&dmac1 0x43>, <&dmac1 0x42>;
1097 #size-cells = <0>;
1104 reg = <0 0xe6c00000 0 0x0064>;
1109 dmas = <&dmac1 0x45>, <&dmac1 0x44>;
1112 #size-cells = <0>;
1119 reg = <0 0xe6c10000 0 0x0064>;
1124 dmas = <&dmac1 0x47>, <&dmac1 0x46>;
1127 #size-cells = <0>;
1134 reg = <0 0xe6c20000 0 0x0064>;
1139 dmas = <&dmac1 0x49>, <&dmac1 0x48>;
1142 #size-cells = <0>;
1149 reg = <0 0xe6c28000 0 0x0064>;
1154 dmas = <&dmac1 0x4b>, <&dmac1 0x4a>;
1157 #size-cells = <0>;
1163 reg = <0 0xe6ef0000 0 0x1000>;
1168 renesas,id = <0>;
1173 #size-cells = <0>;
1177 #size-cells = <0>;
1181 vin00isp0: endpoint@0 {
1182 reg = <0>;
1191 reg = <0 0xe6ef1000 0 0x1000>;
1201 #size-cells = <0>;
1205 #size-cells = <0>;
1209 vin01isp0: endpoint@0 {
1210 reg = <0>;
1219 reg = <0 0xe6ef2000 0 0x1000>;
1229 #size-cells = <0>;
1233 #size-cells = <0>;
1237 vin02isp0: endpoint@0 {
1238 reg = <0>;
1247 reg = <0 0xe6ef3000 0 0x1000>;
1257 #size-cells = <0>;
1261 #size-cells = <0>;
1265 vin03isp0: endpoint@0 {
1266 reg = <0>;
1275 reg = <0 0xe6ef4000 0 0x1000>;
1285 #size-cells = <0>;
1289 #size-cells = <0>;
1293 vin04isp0: endpoint@0 {
1294 reg = <0>;
1303 reg = <0 0xe6ef5000 0 0x1000>;
1313 #size-cells = <0>;
1317 #size-cells = <0>;
1321 vin05isp0: endpoint@0 {
1322 reg = <0>;
1331 reg = <0 0xe6ef6000 0 0x1000>;
1341 #size-cells = <0>;
1345 #size-cells = <0>;
1349 vin06isp0: endpoint@0 {
1350 reg = <0>;
1359 reg = <0 0xe6ef7000 0 0x1000>;
1369 #size-cells = <0>;
1373 #size-cells = <0>;
1377 vin07isp0: endpoint@0 {
1378 reg = <0>;
1387 reg = <0 0xe6ef8000 0 0x1000>;
1397 #size-cells = <0>;
1401 #size-cells = <0>;
1415 reg = <0 0xe6ef9000 0 0x1000>;
1425 #size-cells = <0>;
1429 #size-cells = <0>;
1443 reg = <0 0xe6efa000 0 0x1000>;
1453 #size-cells = <0>;
1457 #size-cells = <0>;
1471 reg = <0 0xe6efb000 0 0x1000>;
1481 #size-cells = <0>;
1485 #size-cells = <0>;
1499 reg = <0 0xe6efc000 0 0x1000>;
1509 #size-cells = <0>;
1513 #size-cells = <0>;
1527 reg = <0 0xe6efd000 0 0x1000>;
1537 #size-cells = <0>;
1541 #size-cells = <0>;
1555 reg = <0 0xe6efe000 0 0x1000>;
1565 #size-cells = <0>;
1569 #size-cells = <0>;
1583 reg = <0 0xe6eff000 0 0x1000>;
1593 #size-cells = <0>;
1597 #size-cells = <0>;
1611 reg = <0 0xe6ed0000 0 0x1000>;
1621 #size-cells = <0>;
1625 #size-cells = <0>;
1639 reg = <0 0xe6ed1000 0 0x1000>;
1649 #size-cells = <0>;
1653 #size-cells = <0>;
1667 reg = <0 0xe6ed2000 0 0x1000>;
1677 #size-cells = <0>;
1681 #size-cells = <0>;
1695 reg = <0 0xe6ed3000 0 0x1000>;
1705 #size-cells = <0>;
1709 #size-cells = <0>;
1723 reg = <0 0xe6ed4000 0 0x1000>;
1733 #size-cells = <0>;
1737 #size-cells = <0>;
1751 reg = <0 0xe6ed5000 0 0x1000>;
1761 #size-cells = <0>;
1765 #size-cells = <0>;
1779 reg = <0 0xe6ed6000 0 0x1000>;
1789 #size-cells = <0>;
1793 #size-cells = <0>;
1807 reg = <0 0xe6ed7000 0 0x1000>;
1817 #size-cells = <0>;
1821 #size-cells = <0>;
1835 reg = <0 0xe6ed8000 0 0x1000>;
1845 #size-cells = <0>;
1849 #size-cells = <0>;
1863 reg = <0 0xe6ed9000 0 0x1000>;
1873 #size-cells = <0>;
1877 #size-cells = <0>;
1891 reg = <0 0xe6eda000 0 0x1000>;
1901 #size-cells = <0>;
1905 #size-cells = <0>;
1919 reg = <0 0xe6edb000 0 0x1000>;
1929 #size-cells = <0>;
1933 #size-cells = <0>;
1947 reg = <0 0xe6edc000 0 0x1000>;
1957 #size-cells = <0>;
1961 #size-cells = <0>;
1975 reg = <0 0xe6edd000 0 0x1000>;
1985 #size-cells = <0>;
1989 #size-cells = <0>;
2003 reg = <0 0xe6ede000 0 0x1000>;
2013 #size-cells = <0>;
2017 #size-cells = <0>;
2031 reg = <0 0xe6edf000 0 0x1000>;
2041 #size-cells = <0>;
2045 #size-cells = <0>;
2060 reg = <0 0xe7350000 0 0x1000>,
2061 <0 0xe7300000 0 0x10000>;
2095 reg = <0 0xe7351000 0 0x1000>,
2096 <0 0xe7310000 0 0x10000>;
2120 reg = <0 0xee140000 0 0x2000>;
2134 reg = <0 0xee200000 0 0x200>,
2135 <0 0x08000000 0 0x04000000>,
2136 <0 0xee208000 0 0x100>;
2143 #size-cells = <0>;
2150 reg = <0 0xee480000 0 0x20000>;
2159 reg = <0 0xee4c0000 0 0x20000>;
2168 reg = <0 0xeed00000 0 0x20000>;
2177 reg = <0 0xeed40000 0 0x20000>;
2186 reg = <0 0xeed80000 0 0x20000>;
2195 reg = <0 0xeedc0000 0 0x20000>;
2204 reg = <0 0xeee80000 0 0x20000>;
2213 reg = <0 0xeeec0000 0 0x20000>;
2222 reg = <0 0xeee00000 0 0x20000>;
2231 reg = <0 0xeef00000 0 0x20000>;
2240 reg = <0 0xeef40000 0 0x20000>;
2249 reg = <0 0xeefc0000 0 0x20000>;
2259 #address-cells = <0>;
2261 reg = <0x0 0xf1000000 0 0x20000>,
2262 <0x0 0xf1060000 0 0x110000>;
2268 reg = <0 0xfea10000 0 0x200>;
2276 reg = <0 0xfea11000 0 0x200>;
2284 reg = <0 0xfea20000 0 0x5000>;
2295 reg = <0 0xfea28000 0 0x5000>;
2306 reg = <0 0xfeaa0000 0 0x10000>;
2315 #size-cells = <0>;
2317 port@0 {
2318 reg = <0>;
2332 reg = <0 0xfeab0000 0 0x10000>;
2341 #size-cells = <0>;
2343 port@0 {
2344 reg = <0>;
2358 reg = <0 0xfed60000 0 0x10000>;
2367 #size-cells = <0>;
2369 port@0 {
2370 reg = <0>;
2384 reg = <0 0xfed70000 0 0x10000>;
2393 #size-cells = <0>;
2395 port@0 {
2396 reg = <0>;
2410 reg = <0 0xfeb00000 0 0x40000>;
2414 clock-names = "du.0";
2417 reset-names = "du.0";
2418 renesas,vsps = <&vspd0 0>, <&vspd1 0>;
2424 #size-cells = <0>;
2426 port@0 {
2427 reg = <0>;
2444 reg = <0 0xfed00000 0 0x10000>;
2453 #size-cells = <0>;
2455 port@0 {
2457 #size-cells = <0>;
2459 reg = <0>;
2461 isp0csi40: endpoint@0 {
2462 reg = <0>;
2527 reg = <0 0xfed20000 0 0x10000>;
2536 #size-cells = <0>;
2538 port@0 {
2540 #size-cells = <0>;
2542 reg = <0>;
2610 reg = <0 0xfed30000 0 0x10000>;
2619 #size-cells = <0>;
2621 port@0 {
2623 #size-cells = <0>;
2625 reg = <0>;
2627 isp2csi42: endpoint@0 {
2628 reg = <0>;
2693 reg = <0 0xfed40000 0 0x10000>;
2702 #size-cells = <0>;
2704 port@0 {
2706 #size-cells = <0>;
2708 reg = <0>;
2776 reg = <0 0xfed80000 0 0x10000>;
2787 #size-cells = <0>;
2789 port@0 {
2790 reg = <0>;
2804 reg = <0 0xfed90000 0 0x10000>;
2815 #size-cells = <0>;
2817 port@0 {
2818 reg = <0>;
2832 reg = <0 0xfff00044 0 4>;
2840 thermal-sensors = <&tsc 0>;