Lines Matching +full:0 +full:xec5a0000
18 * The external audio clocks are configured as 0 Hz fixed frequency
24 #clock-cells = <0>;
25 clock-frequency = <0>;
30 #clock-cells = <0>;
31 clock-frequency = <0>;
36 #clock-cells = <0>;
37 clock-frequency = <0>;
43 #clock-cells = <0>;
44 clock-frequency = <0>;
47 cluster0_opp: opp-table-0 {
114 #size-cells = <0>;
142 a57_0: cpu@0 {
144 reg = <0x0>;
159 reg = <0x1>;
173 reg = <0x100>;
188 reg = <0x101>;
201 reg = <0x102>;
214 reg = <0x103>;
225 L2_CA57: cache-controller-0 {
242 CPU_SLEEP_0: cpu-sleep-0 {
244 arm,psci-suspend-param = <0x0010000>;
253 arm,psci-suspend-param = <0x0010000>;
264 #clock-cells = <0>;
266 clock-frequency = <0>;
271 #clock-cells = <0>;
273 clock-frequency = <0>;
279 #clock-cells = <0>;
280 clock-frequency = <0>;
307 #clock-cells = <0>;
308 clock-frequency = <0>;
321 reg = <0 0xe6020000 0 0x0c>;
332 reg = <0 0xe6050000 0 0x50>;
336 gpio-ranges = <&pfc 0 0 16>;
347 reg = <0 0xe6051000 0 0x50>;
351 gpio-ranges = <&pfc 0 32 29>;
362 reg = <0 0xe6052000 0 0x50>;
366 gpio-ranges = <&pfc 0 64 15>;
377 reg = <0 0xe6053000 0 0x50>;
381 gpio-ranges = <&pfc 0 96 16>;
392 reg = <0 0xe6054000 0 0x50>;
396 gpio-ranges = <&pfc 0 128 18>;
407 reg = <0 0xe6055000 0 0x50>;
411 gpio-ranges = <&pfc 0 160 26>;
422 reg = <0 0xe6055400 0 0x50>;
426 gpio-ranges = <&pfc 0 192 32>;
437 reg = <0 0xe6055800 0 0x50>;
441 gpio-ranges = <&pfc 0 224 4>;
451 reg = <0 0xe6060000 0 0x50c>;
457 reg = <0 0xe60f0000 0 0x1004>;
470 reg = <0 0xe6130000 0 0x1004>;
489 reg = <0 0xe6140000 0 0x1004>;
508 reg = <0 0xe6148000 0 0x1004>;
526 reg = <0 0xe6150000 0 0x1000>;
530 #power-domain-cells = <0>;
536 reg = <0 0xe6160000 0 0x0200>;
541 reg = <0 0xe6180000 0 0x0400>;
547 reg = <0 0xe6198000 0 0x100>,
548 <0 0xe61a0000 0 0x100>,
549 <0 0xe61a8000 0 0x100>;
563 reg = <0 0xe61c0000 0 0x200>;
564 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
577 reg = <0 0xe61e0000 0 0x30>;
590 reg = <0 0xe6fc0000 0 0x30>;
603 reg = <0 0xe6fd0000 0 0x30>;
616 reg = <0 0xe6fe0000 0 0x30>;
629 reg = <0 0xffc00000 0 0x30>;
642 #size-cells = <0>;
645 reg = <0 0xe6500000 0 0x40>;
650 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
651 <&dmac2 0x91>, <&dmac2 0x90>;
659 #size-cells = <0>;
662 reg = <0 0xe6508000 0 0x40>;
667 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
668 <&dmac2 0x93>, <&dmac2 0x92>;
676 #size-cells = <0>;
679 reg = <0 0xe6510000 0 0x40>;
684 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
685 <&dmac2 0x95>, <&dmac2 0x94>;
693 #size-cells = <0>;
696 reg = <0 0xe66d0000 0 0x40>;
701 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
709 #size-cells = <0>;
712 reg = <0 0xe66d8000 0 0x40>;
717 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
725 #size-cells = <0>;
728 reg = <0 0xe66e0000 0 0x40>;
733 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
741 #size-cells = <0>;
744 reg = <0 0xe66e8000 0 0x40>;
749 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
757 #size-cells = <0>;
761 reg = <0 0xe60b0000 0 0x425>;
766 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
775 reg = <0 0xe6540000 0 0x60>;
781 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
782 <&dmac2 0x31>, <&dmac2 0x30>;
793 reg = <0 0xe6550000 0 0x60>;
799 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
800 <&dmac2 0x33>, <&dmac2 0x32>;
811 reg = <0 0xe6560000 0 0x60>;
817 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
818 <&dmac2 0x35>, <&dmac2 0x34>;
829 reg = <0 0xe66a0000 0 0x60>;
835 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
846 reg = <0 0xe66b0000 0 0x60>;
852 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
862 reg = <0 0xe6590000 0 0x200>;
865 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
866 <&usb_dmac1 0>, <&usb_dmac1 1>;
879 reg = <0 0xe65a0000 0 0x100>;
893 reg = <0 0xe65b0000 0 0x100>;
907 reg = <0 0xe65ee000 0 0x90>;
913 #phy-cells = <0>;
920 reg = <0x0 0xe6601000 0 0x1000>;
929 reg = <0 0xe6700000 0 0x10000>;
958 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
971 reg = <0 0xe7300000 0 0x10000>;
1000 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
1013 reg = <0 0xe7310000 0 0x10000>;
1054 reg = <0 0xe6740000 0 0x1000>;
1055 renesas,ipmmu-main = <&ipmmu_mm 0>;
1062 reg = <0 0xe7740000 0 0x1000>;
1070 reg = <0 0xe6570000 0 0x1000>;
1078 reg = <0 0xff8b0000 0 0x1000>;
1086 reg = <0 0xe67b0000 0 0x1000>;
1095 reg = <0 0xec670000 0 0x1000>;
1103 reg = <0 0xfd800000 0 0x1000>;
1111 reg = <0 0xfd950000 0 0x1000>;
1119 reg = <0 0xffc80000 0 0x1000>;
1127 reg = <0 0xfe6b0000 0 0x1000>;
1135 reg = <0 0xfebd0000 0 0x1000>;
1144 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
1182 rx-internal-delay-ps = <0>;
1183 tx-internal-delay-ps = <0>;
1186 #size-cells = <0>;
1193 reg = <0 0xe6c30000 0 0x1000>;
1209 reg = <0 0xe6c38000 0 0x1000>;
1225 reg = <0 0xe66c0000 0 0x8000>;
1250 reg = <0 0xe6e30000 0 8>;
1260 reg = <0 0xe6e31000 0 8>;
1270 reg = <0 0xe6e32000 0 8>;
1280 reg = <0 0xe6e33000 0 8>;
1290 reg = <0 0xe6e34000 0 8>;
1300 reg = <0 0xe6e35000 0 8>;
1310 reg = <0 0xe6e36000 0 8>;
1321 reg = <0 0xe6e60000 0 64>;
1327 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1328 <&dmac2 0x51>, <&dmac2 0x50>;
1338 reg = <0 0xe6e68000 0 64>;
1344 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1345 <&dmac2 0x53>, <&dmac2 0x52>;
1355 reg = <0 0xe6e88000 0 64>;
1361 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1362 <&dmac2 0x13>, <&dmac2 0x12>;
1372 reg = <0 0xe6c50000 0 64>;
1378 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1388 reg = <0 0xe6c40000 0 64>;
1394 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1404 reg = <0 0xe6f30000 0 64>;
1410 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
1411 <&dmac2 0x5b>, <&dmac2 0x5a>;
1420 reg = <0 0xe6e80000 0 0x148>;
1432 reg = <0 0xe6e90000 0 0x0064>;
1435 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1436 <&dmac2 0x41>, <&dmac2 0x40>;
1441 #size-cells = <0>;
1448 reg = <0 0xe6ea0000 0 0x0064>;
1451 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
1452 <&dmac2 0x43>, <&dmac2 0x42>;
1457 #size-cells = <0>;
1464 reg = <0 0xe6c00000 0 0x0064>;
1467 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1472 #size-cells = <0>;
1479 reg = <0 0xe6c10000 0 0x0064>;
1482 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1487 #size-cells = <0>;
1493 reg = <0 0xe6ef0000 0 0x1000>;
1498 renesas,id = <0>;
1503 #size-cells = <0>;
1507 #size-cells = <0>;
1511 vin0csi20: endpoint@0 {
1512 reg = <0>;
1525 reg = <0 0xe6ef1000 0 0x1000>;
1535 #size-cells = <0>;
1539 #size-cells = <0>;
1543 vin1csi20: endpoint@0 {
1544 reg = <0>;
1557 reg = <0 0xe6ef2000 0 0x1000>;
1567 #size-cells = <0>;
1571 #size-cells = <0>;
1575 vin2csi20: endpoint@0 {
1576 reg = <0>;
1589 reg = <0 0xe6ef3000 0 0x1000>;
1599 #size-cells = <0>;
1603 #size-cells = <0>;
1607 vin3csi20: endpoint@0 {
1608 reg = <0>;
1621 reg = <0 0xe6ef4000 0 0x1000>;
1631 #size-cells = <0>;
1635 #size-cells = <0>;
1639 vin4csi20: endpoint@0 {
1640 reg = <0>;
1653 reg = <0 0xe6ef5000 0 0x1000>;
1663 #size-cells = <0>;
1667 #size-cells = <0>;
1671 vin5csi20: endpoint@0 {
1672 reg = <0>;
1685 reg = <0 0xe6ef6000 0 0x1000>;
1695 #size-cells = <0>;
1699 #size-cells = <0>;
1703 vin6csi20: endpoint@0 {
1704 reg = <0>;
1717 reg = <0 0xe6ef7000 0 0x1000>;
1727 #size-cells = <0>;
1731 #size-cells = <0>;
1735 vin7csi20: endpoint@0 {
1736 reg = <0>;
1751 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1757 * clkout : #clock-cells = <0>; <&rcar_sound>;
1761 reg = <0 0xec500000 0 0x1000>, /* SCU */
1762 <0 0xec5a0000 0 0x100>, /* ADG */
1763 <0 0xec540000 0 0x1000>, /* SSIU */
1764 <0 0xec541000 0 0x280>, /* SSI */
1765 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1788 "ssi.1", "ssi.0",
1791 "src.1", "src.0",
1792 "mix.1", "mix.0",
1793 "ctu.1", "ctu.0",
1794 "dvc.0", "dvc.1",
1806 "ssi.1", "ssi.0";
1810 ctu00: ctu-0 { };
1821 dvc0: dvc-0 {
1822 dmas = <&audma1 0xbc>;
1826 dmas = <&audma1 0xbe>;
1832 mix0: mix-0 { };
1837 src0: src-0 {
1839 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1844 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1849 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1854 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1859 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1864 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1869 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1874 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1879 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1884 dmas = <&audma0 0x97>, <&audma1 0xba>;
1890 ssi0: ssi-0 {
1892 dmas = <&audma0 0x01>, <&audma1 0x02>;
1897 dmas = <&audma0 0x03>, <&audma1 0x04>;
1902 dmas = <&audma0 0x05>, <&audma1 0x06>;
1907 dmas = <&audma0 0x07>, <&audma1 0x08>;
1912 dmas = <&audma0 0x09>, <&audma1 0x0a>;
1917 dmas = <&audma0 0x0b>, <&audma1 0x0c>;
1922 dmas = <&audma0 0x0d>, <&audma1 0x0e>;
1927 dmas = <&audma0 0x0f>, <&audma1 0x10>;
1932 dmas = <&audma0 0x11>, <&audma1 0x12>;
1937 dmas = <&audma0 0x13>, <&audma1 0x14>;
1943 ssiu00: ssiu-0 {
1944 dmas = <&audma0 0x15>, <&audma1 0x16>;
1948 dmas = <&audma0 0x35>, <&audma1 0x36>;
1952 dmas = <&audma0 0x37>, <&audma1 0x38>;
1956 dmas = <&audma0 0x47>, <&audma1 0x48>;
1960 dmas = <&audma0 0x3F>, <&audma1 0x40>;
1964 dmas = <&audma0 0x43>, <&audma1 0x44>;
1968 dmas = <&audma0 0x4F>, <&audma1 0x50>;
1972 dmas = <&audma0 0x53>, <&audma1 0x54>;
1976 dmas = <&audma0 0x49>, <&audma1 0x4a>;
1980 dmas = <&audma0 0x4B>, <&audma1 0x4C>;
1984 dmas = <&audma0 0x57>, <&audma1 0x58>;
1988 dmas = <&audma0 0x59>, <&audma1 0x5A>;
1992 dmas = <&audma0 0x5F>, <&audma1 0x60>;
1996 dmas = <&audma0 0xC3>, <&audma1 0xC4>;
2000 dmas = <&audma0 0xC7>, <&audma1 0xC8>;
2004 dmas = <&audma0 0xCB>, <&audma1 0xCC>;
2008 dmas = <&audma0 0x63>, <&audma1 0x64>;
2012 dmas = <&audma0 0x67>, <&audma1 0x68>;
2016 dmas = <&audma0 0x6B>, <&audma1 0x6C>;
2020 dmas = <&audma0 0x6D>, <&audma1 0x6E>;
2024 dmas = <&audma0 0xCF>, <&audma1 0xCE>;
2028 dmas = <&audma0 0xEB>, <&audma1 0xEC>;
2032 dmas = <&audma0 0xED>, <&audma1 0xEE>;
2036 dmas = <&audma0 0xEF>, <&audma1 0xF0>;
2040 dmas = <&audma0 0x6f>, <&audma1 0x70>;
2044 dmas = <&audma0 0x21>, <&audma1 0x22>;
2048 dmas = <&audma0 0x23>, <&audma1 0x24>;
2052 dmas = <&audma0 0x25>, <&audma1 0x26>;
2056 dmas = <&audma0 0x27>, <&audma1 0x28>;
2060 dmas = <&audma0 0x29>, <&audma1 0x2A>;
2064 dmas = <&audma0 0x2B>, <&audma1 0x2C>;
2068 dmas = <&audma0 0x2D>, <&audma1 0x2E>;
2072 dmas = <&audma0 0x71>, <&audma1 0x72>;
2076 dmas = <&audma0 0x17>, <&audma1 0x18>;
2080 dmas = <&audma0 0x19>, <&audma1 0x1A>;
2084 dmas = <&audma0 0x1B>, <&audma1 0x1C>;
2088 dmas = <&audma0 0x1D>, <&audma1 0x1E>;
2092 dmas = <&audma0 0x1F>, <&audma1 0x20>;
2096 dmas = <&audma0 0x31>, <&audma1 0x32>;
2100 dmas = <&audma0 0x33>, <&audma1 0x34>;
2104 dmas = <&audma0 0x73>, <&audma1 0x74>;
2108 dmas = <&audma0 0x75>, <&audma1 0x76>;
2112 dmas = <&audma0 0x79>, <&audma1 0x7a>;
2116 dmas = <&audma0 0x7b>, <&audma1 0x7c>;
2120 dmas = <&audma0 0x7d>, <&audma1 0x7e>;
2124 dmas = <&audma0 0x7F>, <&audma1 0x80>;
2128 dmas = <&audma0 0x81>, <&audma1 0x82>;
2132 dmas = <&audma0 0x83>, <&audma1 0x84>;
2136 dmas = <&audma0 0xA3>, <&audma1 0xA4>;
2140 dmas = <&audma0 0xA5>, <&audma1 0xA6>;
2144 dmas = <&audma0 0xA7>, <&audma1 0xA8>;
2148 dmas = <&audma0 0xA9>, <&audma1 0xAA>;
2157 reg = <0 0xec520000 0 0x800>;
2169 reg = <0 0xec700000 0 0x10000>;
2198 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
2211 reg = <0 0xec720000 0 0x10000>;
2253 reg = <0 0xee000000 0 0xc00>;
2264 reg = <0 0xee020000 0 0x400>;
2274 reg = <0 0xee080000 0 0x100>;
2286 reg = <0 0xee0a0000 0 0x100>;
2298 reg = <0 0xee080100 0 0x100>;
2311 reg = <0 0xee0a0100 0 0x100>;
2325 reg = <0 0xee080200 0 0x700>;
2337 reg = <0 0xee0a0200 0 0x700>;
2348 reg = <0 0xee100000 0 0x2000>;
2362 reg = <0 0xee120000 0 0x2000>;
2376 reg = <0 0xee140000 0 0x2000>;
2390 reg = <0 0xee160000 0 0x2000>;
2404 reg = <0 0xee200000 0 0x200>,
2405 <0 0x08000000 0 0x04000000>,
2406 <0 0xee208000 0 0x100>;
2413 #size-cells = <0>;
2420 #address-cells = <0>;
2422 reg = <0x0 0xf1010000 0 0x1000>,
2423 <0x0 0xf1020000 0 0x20000>,
2424 <0x0 0xf1040000 0 0x20000>,
2425 <0x0 0xf1060000 0 0x20000>;
2437 reg = <0 0xfe000000 0 0x80000>;
2440 bus-range = <0x00 0xff>;
2442 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
2443 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
2444 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
2445 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
2447 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
2452 interrupt-map-mask = <0 0 0 0>;
2453 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
2458 iommu-map = <0 &ipmmu_hc 0 1>;
2459 iommu-map-mask = <0>;
2466 reg = <0 0xee800000 0 0x80000>;
2469 bus-range = <0x00 0xff>;
2471 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
2472 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
2473 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
2474 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
2476 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
2481 interrupt-map-mask = <0 0 0 0>;
2482 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2487 iommu-map = <0 &ipmmu_hc 1 1>;
2488 iommu-map-mask = <0>;
2494 reg = <0 0xfe950000 0 0x200>;
2502 reg = <0 0xfe96f000 0 0x200>;
2510 reg = <0 0xfe9af000 0 0x200>;
2519 reg = <0 0xfea27000 0 0x200>;
2528 reg = <0 0xfea2f000 0 0x200>;
2537 reg = <0 0xfea37000 0 0x200>;
2546 reg = <0 0xfe960000 0 0x8000>;
2557 reg = <0 0xfea20000 0 0x5000>;
2568 reg = <0 0xfea28000 0 0x5000>;
2579 reg = <0 0xfea30000 0 0x5000>;
2590 reg = <0 0xfe9a0000 0 0x8000>;
2601 reg = <0 0xfea80000 0 0x10000>;
2610 #size-cells = <0>;
2612 port@0 {
2613 reg = <0>;
2618 #size-cells = <0>;
2622 csi20vin0: endpoint@0 {
2623 reg = <0>;
2660 reg = <0 0xfeaa0000 0 0x10000>;
2669 #size-cells = <0>;
2671 port@0 {
2672 reg = <0>;
2677 #size-cells = <0>;
2681 csi40vin0: endpoint@0 {
2682 reg = <0>;
2720 reg = <0 0xfead0000 0 0x10000>;
2730 #size-cells = <0>;
2731 port@0 {
2732 reg = <0>;
2749 reg = <0 0xfeb00000 0 0x70000>;
2755 clock-names = "du.0", "du.1", "du.2";
2757 reset-names = "du.0", "du.2";
2759 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>;
2764 #size-cells = <0>;
2766 port@0 {
2767 reg = <0>;
2786 reg = <0 0xfeb90000 0 0x14>;
2794 #size-cells = <0>;
2796 port@0 {
2797 reg = <0>;
2810 reg = <0 0xfff00044 0 4>;
2818 thermal-sensors = <&tsc 0>;
2859 cooling-device = <&a53_0 0 2>;
2890 #clock-cells = <0>;
2891 clock-frequency = <0>;
2896 #clock-cells = <0>;
2897 clock-frequency = <0>;