Lines Matching +full:0 +full:xee0a0200
19 * The external audio clocks are configured as 0 Hz fixed frequency
25 #clock-cells = <0>;
26 clock-frequency = <0>;
31 #clock-cells = <0>;
32 clock-frequency = <0>;
37 #clock-cells = <0>;
38 clock-frequency = <0>;
44 #clock-cells = <0>;
45 clock-frequency = <0>;
48 cluster0_opp: opp-table-0 {
93 #size-cells = <0>;
127 a57_0: cpu@0 {
129 reg = <0x0>;
144 reg = <0x1>;
158 reg = <0x2>;
172 reg = <0x3>;
186 reg = <0x100>;
201 reg = <0x101>;
214 reg = <0x102>;
227 reg = <0x103>;
238 L2_CA57: cache-controller-0 {
255 CPU_SLEEP_0: cpu-sleep-0 {
257 arm,psci-suspend-param = <0x0010000>;
266 arm,psci-suspend-param = <0x0010000>;
277 #clock-cells = <0>;
279 clock-frequency = <0>;
284 #clock-cells = <0>;
286 clock-frequency = <0>;
292 #clock-cells = <0>;
293 clock-frequency = <0>;
322 #clock-cells = <0>;
323 clock-frequency = <0>;
336 reg = <0 0xe6020000 0 0x0c>;
347 reg = <0 0xe6050000 0 0x50>;
351 gpio-ranges = <&pfc 0 0 16>;
362 reg = <0 0xe6051000 0 0x50>;
366 gpio-ranges = <&pfc 0 32 29>;
377 reg = <0 0xe6052000 0 0x50>;
381 gpio-ranges = <&pfc 0 64 15>;
392 reg = <0 0xe6053000 0 0x50>;
396 gpio-ranges = <&pfc 0 96 16>;
407 reg = <0 0xe6054000 0 0x50>;
411 gpio-ranges = <&pfc 0 128 18>;
422 reg = <0 0xe6055000 0 0x50>;
426 gpio-ranges = <&pfc 0 160 26>;
437 reg = <0 0xe6055400 0 0x50>;
441 gpio-ranges = <&pfc 0 192 32>;
452 reg = <0 0xe6055800 0 0x50>;
456 gpio-ranges = <&pfc 0 224 4>;
466 reg = <0 0xe6060000 0 0x50c>;
472 reg = <0 0xe60f0000 0 0x1004>;
485 reg = <0 0xe6130000 0 0x1004>;
504 reg = <0 0xe6140000 0 0x1004>;
523 reg = <0 0xe6148000 0 0x1004>;
541 reg = <0 0xe6150000 0 0x1000>;
545 #power-domain-cells = <0>;
551 reg = <0 0xe6160000 0 0x0200>;
556 reg = <0 0xe6180000 0 0x0400>;
562 reg = <0 0xe6198000 0 0x100>,
563 <0 0xe61a0000 0 0x100>,
564 <0 0xe61a8000 0 0x100>;
578 reg = <0 0xe61c0000 0 0x200>;
579 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
592 reg = <0 0xe61e0000 0 0x30>;
605 reg = <0 0xe6fc0000 0 0x30>;
618 reg = <0 0xe6fd0000 0 0x30>;
631 reg = <0 0xe6fe0000 0 0x30>;
644 reg = <0 0xffc00000 0 0x30>;
657 #size-cells = <0>;
660 reg = <0 0xe6500000 0 0x40>;
665 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
666 <&dmac2 0x91>, <&dmac2 0x90>;
674 #size-cells = <0>;
677 reg = <0 0xe6508000 0 0x40>;
682 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
683 <&dmac2 0x93>, <&dmac2 0x92>;
691 #size-cells = <0>;
694 reg = <0 0xe6510000 0 0x40>;
699 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
700 <&dmac2 0x95>, <&dmac2 0x94>;
708 #size-cells = <0>;
711 reg = <0 0xe66d0000 0 0x40>;
716 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
724 #size-cells = <0>;
727 reg = <0 0xe66d8000 0 0x40>;
732 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
740 #size-cells = <0>;
743 reg = <0 0xe66e0000 0 0x40>;
748 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
756 #size-cells = <0>;
759 reg = <0 0xe66e8000 0 0x40>;
764 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
772 #size-cells = <0>;
776 reg = <0 0xe60b0000 0 0x425>;
781 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
790 reg = <0 0xe6540000 0 0x60>;
796 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
797 <&dmac2 0x31>, <&dmac2 0x30>;
808 reg = <0 0xe6550000 0 0x60>;
814 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
815 <&dmac2 0x33>, <&dmac2 0x32>;
826 reg = <0 0xe6560000 0 0x60>;
832 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
833 <&dmac2 0x35>, <&dmac2 0x34>;
844 reg = <0 0xe66a0000 0 0x60>;
850 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
861 reg = <0 0xe66b0000 0 0x60>;
867 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
877 reg = <0 0xe6590000 0 0x200>;
880 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
881 <&usb_dmac1 0>, <&usb_dmac1 1>;
894 reg = <0 0xe6590630 0 0x02>;
899 #clock-cells = <0>;
909 reg = <0 0xe65a0000 0 0x100>;
923 reg = <0 0xe65b0000 0 0x100>;
937 reg = <0 0xe65ee000 0 0x90>;
943 #phy-cells = <0>;
950 reg = <0 0xe6700000 0 0x10000>;
979 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
992 reg = <0 0xe7300000 0 0x10000>;
1021 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
1034 reg = <0 0xe7310000 0 0x10000>;
1075 reg = <0 0xe6740000 0 0x1000>;
1076 renesas,ipmmu-main = <&ipmmu_mm 0>;
1083 reg = <0 0xe7740000 0 0x1000>;
1091 reg = <0 0xe6570000 0 0x1000>;
1099 reg = <0 0xe67b0000 0 0x1000>;
1108 reg = <0 0xec670000 0 0x1000>;
1116 reg = <0 0xfd800000 0 0x1000>;
1124 reg = <0 0xfd950000 0 0x1000>;
1132 reg = <0 0xfd960000 0 0x1000>;
1140 reg = <0 0xfd970000 0 0x1000>;
1148 reg = <0 0xfe6b0000 0 0x1000>;
1156 reg = <0 0xfe6f0000 0 0x1000>;
1164 reg = <0 0xfebd0000 0 0x1000>;
1172 reg = <0 0xfebe0000 0 0x1000>;
1180 reg = <0 0xfe990000 0 0x1000>;
1188 reg = <0 0xfe980000 0 0x1000>;
1197 reg = <0 0xe6800000 0 0x800>;
1235 rx-internal-delay-ps = <0>;
1236 tx-internal-delay-ps = <0>;
1239 #size-cells = <0>;
1246 reg = <0 0xe6c30000 0 0x1000>;
1262 reg = <0 0xe6c38000 0 0x1000>;
1278 reg = <0 0xe66c0000 0 0x8000>;
1303 reg = <0 0xe6e30000 0 0x8>;
1313 reg = <0 0xe6e31000 0 0x8>;
1323 reg = <0 0xe6e32000 0 0x8>;
1333 reg = <0 0xe6e33000 0 0x8>;
1343 reg = <0 0xe6e34000 0 0x8>;
1353 reg = <0 0xe6e35000 0 0x8>;
1363 reg = <0 0xe6e36000 0 0x8>;
1374 reg = <0 0xe6e60000 0 0x40>;
1380 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1381 <&dmac2 0x51>, <&dmac2 0x50>;
1391 reg = <0 0xe6e68000 0 0x40>;
1397 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1398 <&dmac2 0x53>, <&dmac2 0x52>;
1408 reg = <0 0xe6e88000 0 0x40>;
1414 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1415 <&dmac2 0x13>, <&dmac2 0x12>;
1425 reg = <0 0xe6c50000 0 0x40>;
1431 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1441 reg = <0 0xe6c40000 0 0x40>;
1447 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1457 reg = <0 0xe6f30000 0 0x40>;
1463 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
1464 <&dmac2 0x5b>, <&dmac2 0x5a>;
1474 reg = <0 0xe6e90000 0 0x0064>;
1477 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1478 <&dmac2 0x41>, <&dmac2 0x40>;
1483 #size-cells = <0>;
1490 reg = <0 0xe6ea0000 0 0x0064>;
1493 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
1494 <&dmac2 0x43>, <&dmac2 0x42>;
1499 #size-cells = <0>;
1506 reg = <0 0xe6c00000 0 0x0064>;
1509 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1514 #size-cells = <0>;
1521 reg = <0 0xe6c10000 0 0x0064>;
1524 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1529 #size-cells = <0>;
1535 reg = <0 0xe6ef0000 0 0x1000>;
1540 renesas,id = <0>;
1545 #size-cells = <0>;
1549 #size-cells = <0>;
1553 vin0csi20: endpoint@0 {
1554 reg = <0>;
1567 reg = <0 0xe6ef1000 0 0x1000>;
1577 #size-cells = <0>;
1581 #size-cells = <0>;
1585 vin1csi20: endpoint@0 {
1586 reg = <0>;
1599 reg = <0 0xe6ef2000 0 0x1000>;
1609 #size-cells = <0>;
1613 #size-cells = <0>;
1617 vin2csi20: endpoint@0 {
1618 reg = <0>;
1631 reg = <0 0xe6ef3000 0 0x1000>;
1641 #size-cells = <0>;
1645 #size-cells = <0>;
1649 vin3csi20: endpoint@0 {
1650 reg = <0>;
1663 reg = <0 0xe6ef4000 0 0x1000>;
1673 #size-cells = <0>;
1677 #size-cells = <0>;
1681 vin4csi20: endpoint@0 {
1682 reg = <0>;
1691 reg = <0 0xe6ef5000 0 0x1000>;
1701 #size-cells = <0>;
1705 #size-cells = <0>;
1709 vin5csi20: endpoint@0 {
1710 reg = <0>;
1719 reg = <0 0xe6ef6000 0 0x1000>;
1729 #size-cells = <0>;
1733 #size-cells = <0>;
1737 vin6csi20: endpoint@0 {
1738 reg = <0>;
1747 reg = <0 0xe6ef7000 0 0x1000>;
1757 #size-cells = <0>;
1761 #size-cells = <0>;
1765 vin7csi20: endpoint@0 {
1766 reg = <0>;
1777 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1783 * clkout : #clock-cells = <0>; <&rcar_sound>;
1787 reg = <0 0xec500000 0 0x1000>, /* SCU */
1788 <0 0xec5a0000 0 0x100>, /* ADG */
1789 <0 0xec540000 0 0x1000>, /* SSIU */
1790 <0 0xec541000 0 0x280>, /* SSI */
1791 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1814 "ssi.1", "ssi.0",
1817 "src.1", "src.0",
1818 "mix.1", "mix.0",
1819 "ctu.1", "ctu.0",
1820 "dvc.0", "dvc.1",
1832 "ssi.1", "ssi.0";
1836 dvc0: dvc-0 {
1837 dmas = <&audma1 0xbc>;
1841 dmas = <&audma1 0xbe>;
1847 mix0: mix-0 { };
1852 ctu00: ctu-0 { };
1863 src0: src-0 {
1865 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1870 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1875 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1880 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1885 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1890 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1895 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1900 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1905 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1910 dmas = <&audma0 0x97>, <&audma1 0xba>;
1916 ssiu00: ssiu-0 {
1917 dmas = <&audma0 0x15>, <&audma1 0x16>;
1921 dmas = <&audma0 0x35>, <&audma1 0x36>;
1925 dmas = <&audma0 0x37>, <&audma1 0x38>;
1929 dmas = <&audma0 0x47>, <&audma1 0x48>;
1933 dmas = <&audma0 0x3F>, <&audma1 0x40>;
1937 dmas = <&audma0 0x43>, <&audma1 0x44>;
1941 dmas = <&audma0 0x4F>, <&audma1 0x50>;
1945 dmas = <&audma0 0x53>, <&audma1 0x54>;
1949 dmas = <&audma0 0x49>, <&audma1 0x4a>;
1953 dmas = <&audma0 0x4B>, <&audma1 0x4C>;
1957 dmas = <&audma0 0x57>, <&audma1 0x58>;
1961 dmas = <&audma0 0x59>, <&audma1 0x5A>;
1965 dmas = <&audma0 0x5F>, <&audma1 0x60>;
1969 dmas = <&audma0 0xC3>, <&audma1 0xC4>;
1973 dmas = <&audma0 0xC7>, <&audma1 0xC8>;
1977 dmas = <&audma0 0xCB>, <&audma1 0xCC>;
1981 dmas = <&audma0 0x63>, <&audma1 0x64>;
1985 dmas = <&audma0 0x67>, <&audma1 0x68>;
1989 dmas = <&audma0 0x6B>, <&audma1 0x6C>;
1993 dmas = <&audma0 0x6D>, <&audma1 0x6E>;
1997 dmas = <&audma0 0xCF>, <&audma1 0xCE>;
2001 dmas = <&audma0 0xEB>, <&audma1 0xEC>;
2005 dmas = <&audma0 0xED>, <&audma1 0xEE>;
2009 dmas = <&audma0 0xEF>, <&audma1 0xF0>;
2013 dmas = <&audma0 0x6f>, <&audma1 0x70>;
2017 dmas = <&audma0 0x21>, <&audma1 0x22>;
2021 dmas = <&audma0 0x23>, <&audma1 0x24>;
2025 dmas = <&audma0 0x25>, <&audma1 0x26>;
2029 dmas = <&audma0 0x27>, <&audma1 0x28>;
2033 dmas = <&audma0 0x29>, <&audma1 0x2A>;
2037 dmas = <&audma0 0x2B>, <&audma1 0x2C>;
2041 dmas = <&audma0 0x2D>, <&audma1 0x2E>;
2045 dmas = <&audma0 0x71>, <&audma1 0x72>;
2049 dmas = <&audma0 0x17>, <&audma1 0x18>;
2053 dmas = <&audma0 0x19>, <&audma1 0x1A>;
2057 dmas = <&audma0 0x1B>, <&audma1 0x1C>;
2061 dmas = <&audma0 0x1D>, <&audma1 0x1E>;
2065 dmas = <&audma0 0x1F>, <&audma1 0x20>;
2069 dmas = <&audma0 0x31>, <&audma1 0x32>;
2073 dmas = <&audma0 0x33>, <&audma1 0x34>;
2077 dmas = <&audma0 0x73>, <&audma1 0x74>;
2081 dmas = <&audma0 0x75>, <&audma1 0x76>;
2085 dmas = <&audma0 0x79>, <&audma1 0x7a>;
2089 dmas = <&audma0 0x7b>, <&audma1 0x7c>;
2093 dmas = <&audma0 0x7d>, <&audma1 0x7e>;
2097 dmas = <&audma0 0x7F>, <&audma1 0x80>;
2101 dmas = <&audma0 0x81>, <&audma1 0x82>;
2105 dmas = <&audma0 0x83>, <&audma1 0x84>;
2109 dmas = <&audma0 0xA3>, <&audma1 0xA4>;
2113 dmas = <&audma0 0xA5>, <&audma1 0xA6>;
2117 dmas = <&audma0 0xA7>, <&audma1 0xA8>;
2121 dmas = <&audma0 0xA9>, <&audma1 0xAA>;
2127 ssi0: ssi-0 {
2129 dmas = <&audma0 0x01>, <&audma1 0x02>;
2134 dmas = <&audma0 0x03>, <&audma1 0x04>;
2139 dmas = <&audma0 0x05>, <&audma1 0x06>;
2144 dmas = <&audma0 0x07>, <&audma1 0x08>;
2149 dmas = <&audma0 0x09>, <&audma1 0x0a>;
2154 dmas = <&audma0 0x0b>, <&audma1 0x0c>;
2159 dmas = <&audma0 0x0d>, <&audma1 0x0e>;
2164 dmas = <&audma0 0x0f>, <&audma1 0x10>;
2169 dmas = <&audma0 0x11>, <&audma1 0x12>;
2174 dmas = <&audma0 0x13>, <&audma1 0x14>;
2183 reg = <0 0xec700000 0 0x10000>;
2212 iommus = <&ipmmu_mp0 0>, <&ipmmu_mp0 1>,
2225 reg = <0 0xec720000 0 0x10000>;
2267 reg = <0 0xee000000 0 0xc00>;
2278 reg = <0 0xee020000 0 0x400>;
2288 reg = <0 0xee080000 0 0x100>;
2300 reg = <0 0xee0a0000 0 0x100>;
2312 reg = <0 0xee080100 0 0x100>;
2325 reg = <0 0xee0a0100 0 0x100>;
2339 reg = <0 0xee080200 0 0x700>;
2351 reg = <0 0xee0a0200 0 0x700>;
2362 reg = <0 0xee100000 0 0x2000>;
2376 reg = <0 0xee120000 0 0x2000>;
2390 reg = <0 0xee140000 0 0x2000>;
2404 reg = <0 0xee160000 0 0x2000>;
2418 reg = <0 0xee200000 0 0x200>,
2419 <0 0x08000000 0 0x4000000>,
2420 <0 0xee208000 0 0x100>;
2427 #size-cells = <0>;
2434 reg = <0 0xee300000 0 0x200000>;
2446 #address-cells = <0>;
2448 reg = <0x0 0xf1010000 0 0x1000>,
2449 <0x0 0xf1020000 0 0x20000>,
2450 <0x0 0xf1040000 0 0x20000>,
2451 <0x0 0xf1060000 0 0x20000>;
2463 reg = <0 0xfe000000 0 0x80000>;
2466 bus-range = <0x00 0xff>;
2468 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
2469 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
2470 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
2471 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
2473 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
2478 interrupt-map-mask = <0 0 0 0>;
2479 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
2484 iommu-map = <0 &ipmmu_hc 0 1>;
2485 iommu-map-mask = <0>;
2492 reg = <0 0xee800000 0 0x80000>;
2495 bus-range = <0x00 0xff>;
2497 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
2498 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
2499 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
2500 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
2502 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
2507 interrupt-map-mask = <0 0 0 0>;
2508 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2513 iommu-map = <0 &ipmmu_hc 1 1>;
2514 iommu-map-mask = <0>;
2521 reg = <0x0 0xfe000000 0 0x80000>,
2522 <0x0 0xfe100000 0 0x100000>,
2523 <0x0 0xfe200000 0 0x200000>,
2524 <0x0 0x30000000 0 0x8000000>,
2525 <0x0 0x38000000 0 0x8000000>;
2540 reg = <0x0 0xee800000 0 0x80000>,
2541 <0x0 0xee900000 0 0x100000>,
2542 <0x0 0xeea00000 0 0x200000>,
2543 <0x0 0xc0000000 0 0x8000000>,
2544 <0x0 0xc8000000 0 0x8000000>;
2558 reg = <0 0xfe920000 0 0x8000>;
2569 reg = <0 0xfe960000 0 0x8000>;
2580 reg = <0 0xfea20000 0 0x5000>;
2591 reg = <0 0xfea28000 0 0x5000>;
2602 reg = <0 0xfe9a0000 0 0x8000>;
2613 reg = <0 0xfe9b0000 0 0x8000>;
2624 reg = <0 0xfe940000 0 0x2400>;
2634 reg = <0 0xfe944000 0 0x2400>;
2644 reg = <0 0xfe950000 0 0x200>;
2652 reg = <0 0xfe951000 0 0x200>;
2660 reg = <0 0xfe96f000 0 0x200>;
2668 reg = <0 0xfe92f000 0 0x200>;
2676 reg = <0 0xfe9af000 0 0x200>;
2684 reg = <0 0xfe9bf000 0 0x200>;
2692 reg = <0 0xfea27000 0 0x200>;
2700 reg = <0 0xfea2f000 0 0x200>;
2708 reg = <0 0xfea80000 0 0x10000>;
2717 #size-cells = <0>;
2719 port@0 {
2720 reg = <0>;
2725 #size-cells = <0>;
2729 csi20vin0: endpoint@0 {
2730 reg = <0>;
2767 reg = <0 0xfeaa0000 0 0x10000>;
2776 #size-cells = <0>;
2778 port@0 {
2779 reg = <0>;
2784 #size-cells = <0>;
2788 csi40vin0: endpoint@0 {
2789 reg = <0>;
2811 reg = <0 0xfead0000 0 0x10000>;
2822 #size-cells = <0>;
2824 port@0 {
2825 reg = <0>;
2842 reg = <0 0xfeb00000 0 0x80000>;
2849 clock-names = "du.0", "du.1", "du.3";
2851 reset-names = "du.0", "du.3";
2854 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>;
2858 #size-cells = <0>;
2860 port@0 {
2861 reg = <0>;
2880 reg = <0 0xfeb90000 0 0x14>;
2888 #size-cells = <0>;
2890 port@0 {
2891 reg = <0>;
2904 reg = <0 0xfff00044 0 4>;
2912 thermal-sensors = <&tsc 0>;
2962 cooling-device = <&a57_0 0 2>;
2968 cooling-device = <&a53_0 0 2>;
2986 #clock-cells = <0>;
2987 clock-frequency = <0>;
2992 #clock-cells = <0>;
2993 clock-frequency = <0>;