Lines Matching +full:0 +full:xec500000
19 * The external audio clocks are configured as 0 Hz fixed frequency
25 #clock-cells = <0>;
26 clock-frequency = <0>;
31 #clock-cells = <0>;
32 clock-frequency = <0>;
37 #clock-cells = <0>;
38 clock-frequency = <0>;
44 #clock-cells = <0>;
45 clock-frequency = <0>;
48 cluster0_opp: opp-table-0 {
72 #size-cells = <0>;
74 a57_0: cpu@0 {
76 reg = <0x0>;
89 reg = <0x1>;
98 L2_CA57: cache-controller-0 {
108 #clock-cells = <0>;
110 clock-frequency = <0>;
115 #clock-cells = <0>;
117 clock-frequency = <0>;
123 #clock-cells = <0>;
124 clock-frequency = <0>;
142 #clock-cells = <0>;
143 clock-frequency = <0>;
156 reg = <0 0xe6020000 0 0x0c>;
167 reg = <0 0xe6050000 0 0x50>;
171 gpio-ranges = <&pfc 0 0 16>;
182 reg = <0 0xe6051000 0 0x50>;
186 gpio-ranges = <&pfc 0 32 29>;
197 reg = <0 0xe6052000 0 0x50>;
201 gpio-ranges = <&pfc 0 64 15>;
212 reg = <0 0xe6053000 0 0x50>;
216 gpio-ranges = <&pfc 0 96 16>;
227 reg = <0 0xe6054000 0 0x50>;
231 gpio-ranges = <&pfc 0 128 18>;
242 reg = <0 0xe6055000 0 0x50>;
246 gpio-ranges = <&pfc 0 160 26>;
257 reg = <0 0xe6055400 0 0x50>;
261 gpio-ranges = <&pfc 0 192 32>;
272 reg = <0 0xe6055800 0 0x50>;
276 gpio-ranges = <&pfc 0 224 4>;
286 reg = <0 0xe6060000 0 0x50c>;
292 reg = <0 0xe60f0000 0 0x1004>;
305 reg = <0 0xe6130000 0 0x1004>;
324 reg = <0 0xe6140000 0 0x1004>;
343 reg = <0 0xe6148000 0 0x1004>;
361 reg = <0 0xe6150000 0 0x1000>;
365 #power-domain-cells = <0>;
371 reg = <0 0xe6160000 0 0x0200>;
376 reg = <0 0xe6180000 0 0x0400>;
382 reg = <0 0xe6198000 0 0x100>,
383 <0 0xe61a0000 0 0x100>,
384 <0 0xe61a8000 0 0x100>;
398 reg = <0 0xe61c0000 0 0x200>;
399 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
412 reg = <0 0xe61e0000 0 0x30>;
425 reg = <0 0xe6fc0000 0 0x30>;
438 reg = <0 0xe6fd0000 0 0x30>;
451 reg = <0 0xe6fe0000 0 0x30>;
464 reg = <0 0xffc00000 0 0x30>;
477 #size-cells = <0>;
480 reg = <0 0xe6500000 0 0x40>;
485 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
486 <&dmac2 0x91>, <&dmac2 0x90>;
494 #size-cells = <0>;
497 reg = <0 0xe6508000 0 0x40>;
502 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
503 <&dmac2 0x93>, <&dmac2 0x92>;
511 #size-cells = <0>;
514 reg = <0 0xe6510000 0 0x40>;
519 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
520 <&dmac2 0x95>, <&dmac2 0x94>;
528 #size-cells = <0>;
531 reg = <0 0xe66d0000 0 0x40>;
536 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
544 #size-cells = <0>;
547 reg = <0 0xe66d8000 0 0x40>;
552 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
560 #size-cells = <0>;
563 reg = <0 0xe66e0000 0 0x40>;
568 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
576 #size-cells = <0>;
579 reg = <0 0xe66e8000 0 0x40>;
584 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
592 #size-cells = <0>;
596 reg = <0 0xe60b0000 0 0x425>;
601 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
610 reg = <0 0xe6540000 0 0x60>;
616 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
617 <&dmac2 0x31>, <&dmac2 0x30>;
628 reg = <0 0xe6550000 0 0x60>;
634 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
635 <&dmac2 0x33>, <&dmac2 0x32>;
646 reg = <0 0xe6560000 0 0x60>;
652 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
653 <&dmac2 0x35>, <&dmac2 0x34>;
664 reg = <0 0xe66a0000 0 0x60>;
670 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
681 reg = <0 0xe66b0000 0 0x60>;
687 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
697 reg = <0 0xe6590000 0 0x200>;
700 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
701 <&usb_dmac1 0>, <&usb_dmac1 1>;
714 reg = <0 0xe6590630 0 0x02>;
719 #clock-cells = <0>;
729 reg = <0 0xe65a0000 0 0x100>;
743 reg = <0 0xe65b0000 0 0x100>;
757 reg = <0 0xe65ee000 0 0x90>;
763 #phy-cells = <0>;
770 reg = <0 0xe6700000 0 0x10000>;
799 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
812 reg = <0 0xe7300000 0 0x10000>;
841 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
854 reg = <0 0xe7310000 0 0x10000>;
895 reg = <0 0xe6740000 0 0x1000>;
896 renesas,ipmmu-main = <&ipmmu_mm 0>;
903 reg = <0 0xe7740000 0 0x1000>;
911 reg = <0 0xe6570000 0 0x1000>;
919 reg = <0 0xe67b0000 0 0x1000>;
928 reg = <0 0xec670000 0 0x1000>;
936 reg = <0 0xfd800000 0 0x1000>;
944 reg = <0 0xfe6b0000 0 0x1000>;
952 reg = <0 0xfebd0000 0 0x1000>;
960 reg = <0 0xfe990000 0 0x1000>;
969 reg = <0 0xe6800000 0 0x800>;
1007 rx-internal-delay-ps = <0>;
1008 tx-internal-delay-ps = <0>;
1011 #size-cells = <0>;
1018 reg = <0 0xe6c30000 0 0x1000>;
1034 reg = <0 0xe6c38000 0 0x1000>;
1050 reg = <0 0xe66c0000 0 0x8000>;
1075 reg = <0 0xe6e30000 0 0x8>;
1085 reg = <0 0xe6e31000 0 0x8>;
1095 reg = <0 0xe6e32000 0 0x8>;
1105 reg = <0 0xe6e33000 0 0x8>;
1115 reg = <0 0xe6e34000 0 0x8>;
1125 reg = <0 0xe6e35000 0 0x8>;
1135 reg = <0 0xe6e36000 0 0x8>;
1146 reg = <0 0xe6e60000 0 0x40>;
1152 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1153 <&dmac2 0x51>, <&dmac2 0x50>;
1163 reg = <0 0xe6e68000 0 0x40>;
1169 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1170 <&dmac2 0x53>, <&dmac2 0x52>;
1180 reg = <0 0xe6e88000 0 0x40>;
1186 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1187 <&dmac2 0x13>, <&dmac2 0x12>;
1197 reg = <0 0xe6c50000 0 0x40>;
1203 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1213 reg = <0 0xe6c40000 0 0x40>;
1219 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1229 reg = <0 0xe6f30000 0 0x40>;
1235 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
1236 <&dmac2 0x5b>, <&dmac2 0x5a>;
1246 reg = <0 0xe6e90000 0 0x0064>;
1249 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1250 <&dmac2 0x41>, <&dmac2 0x40>;
1255 #size-cells = <0>;
1262 reg = <0 0xe6ea0000 0 0x0064>;
1265 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
1266 <&dmac2 0x43>, <&dmac2 0x42>;
1271 #size-cells = <0>;
1278 reg = <0 0xe6c00000 0 0x0064>;
1281 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1286 #size-cells = <0>;
1293 reg = <0 0xe6c10000 0 0x0064>;
1296 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1301 #size-cells = <0>;
1307 reg = <0 0xe6ef0000 0 0x1000>;
1312 renesas,id = <0>;
1317 #size-cells = <0>;
1321 #size-cells = <0>;
1325 vin0csi20: endpoint@0 {
1326 reg = <0>;
1339 reg = <0 0xe6ef1000 0 0x1000>;
1349 #size-cells = <0>;
1353 #size-cells = <0>;
1357 vin1csi20: endpoint@0 {
1358 reg = <0>;
1371 reg = <0 0xe6ef2000 0 0x1000>;
1381 #size-cells = <0>;
1385 #size-cells = <0>;
1389 vin2csi20: endpoint@0 {
1390 reg = <0>;
1403 reg = <0 0xe6ef3000 0 0x1000>;
1413 #size-cells = <0>;
1417 #size-cells = <0>;
1421 vin3csi20: endpoint@0 {
1422 reg = <0>;
1435 reg = <0 0xe6ef4000 0 0x1000>;
1445 #size-cells = <0>;
1449 #size-cells = <0>;
1453 vin4csi20: endpoint@0 {
1454 reg = <0>;
1467 reg = <0 0xe6ef5000 0 0x1000>;
1477 #size-cells = <0>;
1481 #size-cells = <0>;
1485 vin5csi20: endpoint@0 {
1486 reg = <0>;
1499 reg = <0 0xe6ef6000 0 0x1000>;
1509 #size-cells = <0>;
1513 #size-cells = <0>;
1517 vin6csi20: endpoint@0 {
1518 reg = <0>;
1531 reg = <0 0xe6ef7000 0 0x1000>;
1541 #size-cells = <0>;
1545 #size-cells = <0>;
1549 vin7csi20: endpoint@0 {
1550 reg = <0>;
1565 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1571 * clkout : #clock-cells = <0>; <&rcar_sound>;
1575 reg = <0 0xec500000 0 0x1000>, /* SCU */
1576 <0 0xec5a0000 0 0x100>, /* ADG */
1577 <0 0xec540000 0 0x1000>, /* SSIU */
1578 <0 0xec541000 0 0x280>, /* SSI */
1579 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1602 "ssi.1", "ssi.0",
1605 "src.1", "src.0",
1606 "mix.1", "mix.0",
1607 "ctu.1", "ctu.0",
1608 "dvc.0", "dvc.1",
1620 "ssi.1", "ssi.0";
1624 ctu00: ctu-0 { };
1635 dvc0: dvc-0 {
1636 dmas = <&audma1 0xbc>;
1640 dmas = <&audma1 0xbe>;
1646 mix0: mix-0 { };
1651 src0: src-0 {
1653 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1658 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1663 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1668 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1673 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1678 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1683 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1688 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1693 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1698 dmas = <&audma0 0x97>, <&audma1 0xba>;
1704 ssi0: ssi-0 {
1706 dmas = <&audma0 0x01>, <&audma1 0x02>;
1711 dmas = <&audma0 0x03>, <&audma1 0x04>;
1716 dmas = <&audma0 0x05>, <&audma1 0x06>;
1721 dmas = <&audma0 0x07>, <&audma1 0x08>;
1726 dmas = <&audma0 0x09>, <&audma1 0x0a>;
1731 dmas = <&audma0 0x0b>, <&audma1 0x0c>;
1736 dmas = <&audma0 0x0d>, <&audma1 0x0e>;
1741 dmas = <&audma0 0x0f>, <&audma1 0x10>;
1746 dmas = <&audma0 0x11>, <&audma1 0x12>;
1751 dmas = <&audma0 0x13>, <&audma1 0x14>;
1757 ssiu00: ssiu-0 {
1758 dmas = <&audma0 0x15>, <&audma1 0x16>;
1762 dmas = <&audma0 0x35>, <&audma1 0x36>;
1766 dmas = <&audma0 0x37>, <&audma1 0x38>;
1770 dmas = <&audma0 0x47>, <&audma1 0x48>;
1774 dmas = <&audma0 0x3F>, <&audma1 0x40>;
1778 dmas = <&audma0 0x43>, <&audma1 0x44>;
1782 dmas = <&audma0 0x4F>, <&audma1 0x50>;
1786 dmas = <&audma0 0x53>, <&audma1 0x54>;
1790 dmas = <&audma0 0x49>, <&audma1 0x4a>;
1794 dmas = <&audma0 0x4B>, <&audma1 0x4C>;
1798 dmas = <&audma0 0x57>, <&audma1 0x58>;
1802 dmas = <&audma0 0x59>, <&audma1 0x5A>;
1806 dmas = <&audma0 0x5F>, <&audma1 0x60>;
1810 dmas = <&audma0 0xC3>, <&audma1 0xC4>;
1814 dmas = <&audma0 0xC7>, <&audma1 0xC8>;
1818 dmas = <&audma0 0xCB>, <&audma1 0xCC>;
1822 dmas = <&audma0 0x63>, <&audma1 0x64>;
1826 dmas = <&audma0 0x67>, <&audma1 0x68>;
1830 dmas = <&audma0 0x6B>, <&audma1 0x6C>;
1834 dmas = <&audma0 0x6D>, <&audma1 0x6E>;
1838 dmas = <&audma0 0xCF>, <&audma1 0xCE>;
1842 dmas = <&audma0 0xEB>, <&audma1 0xEC>;
1846 dmas = <&audma0 0xED>, <&audma1 0xEE>;
1850 dmas = <&audma0 0xEF>, <&audma1 0xF0>;
1854 dmas = <&audma0 0x6f>, <&audma1 0x70>;
1858 dmas = <&audma0 0x21>, <&audma1 0x22>;
1862 dmas = <&audma0 0x23>, <&audma1 0x24>;
1866 dmas = <&audma0 0x25>, <&audma1 0x26>;
1870 dmas = <&audma0 0x27>, <&audma1 0x28>;
1874 dmas = <&audma0 0x29>, <&audma1 0x2A>;
1878 dmas = <&audma0 0x2B>, <&audma1 0x2C>;
1882 dmas = <&audma0 0x2D>, <&audma1 0x2E>;
1886 dmas = <&audma0 0x71>, <&audma1 0x72>;
1890 dmas = <&audma0 0x17>, <&audma1 0x18>;
1894 dmas = <&audma0 0x19>, <&audma1 0x1A>;
1898 dmas = <&audma0 0x1B>, <&audma1 0x1C>;
1902 dmas = <&audma0 0x1D>, <&audma1 0x1E>;
1906 dmas = <&audma0 0x1F>, <&audma1 0x20>;
1910 dmas = <&audma0 0x31>, <&audma1 0x32>;
1914 dmas = <&audma0 0x33>, <&audma1 0x34>;
1918 dmas = <&audma0 0x73>, <&audma1 0x74>;
1922 dmas = <&audma0 0x75>, <&audma1 0x76>;
1926 dmas = <&audma0 0x79>, <&audma1 0x7a>;
1930 dmas = <&audma0 0x7b>, <&audma1 0x7c>;
1934 dmas = <&audma0 0x7d>, <&audma1 0x7e>;
1938 dmas = <&audma0 0x7F>, <&audma1 0x80>;
1942 dmas = <&audma0 0x81>, <&audma1 0x82>;
1946 dmas = <&audma0 0x83>, <&audma1 0x84>;
1950 dmas = <&audma0 0xA3>, <&audma1 0xA4>;
1954 dmas = <&audma0 0xA5>, <&audma1 0xA6>;
1958 dmas = <&audma0 0xA7>, <&audma1 0xA8>;
1962 dmas = <&audma0 0xA9>, <&audma1 0xAA>;
1971 reg = <0 0xec700000 0 0x10000>;
2005 reg = <0 0xec720000 0 0x10000>;
2039 reg = <0 0xee000000 0 0xc00>;
2050 reg = <0 0xee020000 0 0x400>;
2060 reg = <0 0xee080000 0 0x100>;
2072 reg = <0 0xee0a0000 0 0x100>;
2084 reg = <0 0xee080100 0 0x100>;
2097 reg = <0 0xee0a0100 0 0x100>;
2111 reg = <0 0xee080200 0 0x700>;
2123 reg = <0 0xee0a0200 0 0x700>;
2134 reg = <0 0xee100000 0 0x2000>;
2147 reg = <0 0xee120000 0 0x2000>;
2160 reg = <0 0xee140000 0 0x2000>;
2173 reg = <0 0xee160000 0 0x2000>;
2186 reg = <0 0xee200000 0 0x200>,
2187 <0 0x08000000 0 0x4000000>,
2188 <0 0xee208000 0 0x100>;
2195 #size-cells = <0>;
2202 reg = <0 0xee300000 0 0x200000>;
2213 #address-cells = <0>;
2215 reg = <0x0 0xf1010000 0 0x1000>,
2216 <0x0 0xf1020000 0 0x20000>,
2217 <0x0 0xf1040000 0 0x20000>,
2218 <0x0 0xf1060000 0 0x20000>;
2230 reg = <0 0xfe000000 0 0x80000>;
2233 bus-range = <0x00 0xff>;
2235 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
2236 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
2237 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
2238 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
2240 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
2245 interrupt-map-mask = <0 0 0 0>;
2246 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
2251 iommu-map = <0 &ipmmu_hc 0 1>;
2252 iommu-map-mask = <0>;
2259 reg = <0 0xee800000 0 0x80000>;
2262 bus-range = <0x00 0xff>;
2264 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
2265 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
2266 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
2267 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
2269 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
2274 interrupt-map-mask = <0 0 0 0>;
2275 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2280 iommu-map = <0 &ipmmu_hc 1 1>;
2281 iommu-map-mask = <0>;
2288 reg = <0x0 0xfe000000 0 0x80000>,
2289 <0x0 0xfe100000 0 0x100000>,
2290 <0x0 0xfe200000 0 0x200000>,
2291 <0x0 0x30000000 0 0x8000000>,
2292 <0x0 0x38000000 0 0x8000000>;
2307 reg = <0x0 0xee800000 0 0x80000>,
2308 <0x0 0xee900000 0 0x100000>,
2309 <0x0 0xeea00000 0 0x200000>,
2310 <0x0 0xc0000000 0 0x8000000>,
2311 <0x0 0xc8000000 0 0x8000000>;
2325 reg = <0 0xfe940000 0 0x2400>;
2335 reg = <0 0xfe950000 0 0x200>;
2343 reg = <0 0xfe960000 0 0x8000>;
2354 reg = <0 0xfe9a0000 0 0x8000>;
2365 reg = <0 0xfea20000 0 0x5000>;
2376 reg = <0 0xfea28000 0 0x5000>;
2387 reg = <0 0xfe96f000 0 0x200>;
2395 reg = <0 0xfea27000 0 0x200>;
2403 reg = <0 0xfea2f000 0 0x200>;
2411 reg = <0 0xfe9af000 0 0x200>;
2419 reg = <0 0xfea80000 0 0x10000>;
2428 #size-cells = <0>;
2430 port@0 {
2431 reg = <0>;
2436 #size-cells = <0>;
2440 csi20vin0: endpoint@0 {
2441 reg = <0>;
2478 reg = <0 0xfeaa0000 0 0x10000>;
2487 #size-cells = <0>;
2489 port@0 {
2490 reg = <0>;
2495 #size-cells = <0>;
2499 csi40vin0: endpoint@0 {
2500 reg = <0>;
2538 reg = <0 0xfead0000 0 0x10000>;
2549 #size-cells = <0>;
2551 port@0 {
2552 reg = <0>;
2569 reg = <0 0xfeb00000 0 0x80000>;
2575 clock-names = "du.0", "du.1", "du.3";
2577 reset-names = "du.0", "du.3";
2580 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>;
2584 #size-cells = <0>;
2586 port@0 {
2587 reg = <0>;
2606 reg = <0 0xfeb90000 0 0x14>;
2614 #size-cells = <0>;
2616 port@0 {
2617 reg = <0>;
2630 reg = <0 0xfff00044 0 4>;
2638 thermal-sensors = <&tsc 0>;
2674 cooling-device = <&a57_0 0 2>;
2705 #clock-cells = <0>;
2706 clock-frequency = <0>;
2711 #clock-cells = <0>;
2712 clock-frequency = <0>;