Lines Matching +full:0 +full:xec540000
19 * The external audio clocks are configured as 0 Hz fixed frequency
25 #clock-cells = <0>;
26 clock-frequency = <0>;
31 #clock-cells = <0>;
32 clock-frequency = <0>;
37 #clock-cells = <0>;
38 clock-frequency = <0>;
44 #clock-cells = <0>;
45 clock-frequency = <0>;
48 cluster0_opp: opp-table-0 {
93 #size-cells = <0>;
121 a57_0: cpu@0 {
123 reg = <0x0>;
137 reg = <0x1>;
150 reg = <0x100>;
164 reg = <0x101>;
176 reg = <0x102>;
188 reg = <0x103>;
198 L2_CA57: cache-controller-0 {
215 #clock-cells = <0>;
217 clock-frequency = <0>;
222 #clock-cells = <0>;
224 clock-frequency = <0>;
230 #clock-cells = <0>;
231 clock-frequency = <0>;
258 #clock-cells = <0>;
259 clock-frequency = <0>;
272 reg = <0 0xe6020000 0 0x0c>;
283 reg = <0 0xe6050000 0 0x50>;
287 gpio-ranges = <&pfc 0 0 16>;
298 reg = <0 0xe6051000 0 0x50>;
302 gpio-ranges = <&pfc 0 32 29>;
313 reg = <0 0xe6052000 0 0x50>;
317 gpio-ranges = <&pfc 0 64 15>;
328 reg = <0 0xe6053000 0 0x50>;
332 gpio-ranges = <&pfc 0 96 16>;
343 reg = <0 0xe6054000 0 0x50>;
347 gpio-ranges = <&pfc 0 128 18>;
358 reg = <0 0xe6055000 0 0x50>;
362 gpio-ranges = <&pfc 0 160 26>;
373 reg = <0 0xe6055400 0 0x50>;
377 gpio-ranges = <&pfc 0 192 32>;
388 reg = <0 0xe6055800 0 0x50>;
392 gpio-ranges = <&pfc 0 224 4>;
402 reg = <0 0xe6060000 0 0x50c>;
408 reg = <0 0xe60f0000 0 0x1004>;
421 reg = <0 0xe6130000 0 0x1004>;
440 reg = <0 0xe6140000 0 0x1004>;
459 reg = <0 0xe6148000 0 0x1004>;
477 reg = <0 0xe6150000 0 0x0bb0>;
481 #power-domain-cells = <0>;
487 reg = <0 0xe6160000 0 0x018c>;
492 reg = <0 0xe6180000 0 0x0400>;
498 reg = <0 0xe6198000 0 0x100>,
499 <0 0xe61a0000 0 0x100>,
500 <0 0xe61a8000 0 0x100>;
514 reg = <0 0xe61c0000 0 0x200>;
515 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
528 reg = <0 0xe61e0000 0 0x30>;
541 reg = <0 0xe6fc0000 0 0x30>;
554 reg = <0 0xe6fd0000 0 0x30>;
567 reg = <0 0xe6fe0000 0 0x30>;
580 reg = <0 0xffc00000 0 0x30>;
593 #size-cells = <0>;
596 reg = <0 0xe6500000 0 0x40>;
601 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
602 <&dmac2 0x91>, <&dmac2 0x90>;
610 #size-cells = <0>;
613 reg = <0 0xe6508000 0 0x40>;
618 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
619 <&dmac2 0x93>, <&dmac2 0x92>;
627 #size-cells = <0>;
630 reg = <0 0xe6510000 0 0x40>;
635 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
636 <&dmac2 0x95>, <&dmac2 0x94>;
644 #size-cells = <0>;
647 reg = <0 0xe66d0000 0 0x40>;
652 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
660 #size-cells = <0>;
663 reg = <0 0xe66d8000 0 0x40>;
668 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
676 #size-cells = <0>;
679 reg = <0 0xe66e0000 0 0x40>;
684 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
692 #size-cells = <0>;
695 reg = <0 0xe66e8000 0 0x40>;
700 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
708 #size-cells = <0>;
712 reg = <0 0xe60b0000 0 0x425>;
717 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
726 reg = <0 0xe6540000 0 0x60>;
732 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
733 <&dmac2 0x31>, <&dmac2 0x30>;
744 reg = <0 0xe6550000 0 0x60>;
750 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
751 <&dmac2 0x33>, <&dmac2 0x32>;
762 reg = <0 0xe6560000 0 0x60>;
768 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
769 <&dmac2 0x35>, <&dmac2 0x34>;
780 reg = <0 0xe66a0000 0 0x60>;
786 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
797 reg = <0 0xe66b0000 0 0x60>;
803 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
813 reg = <0 0xe6590000 0 0x200>;
816 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
817 <&usb_dmac1 0>, <&usb_dmac1 1>;
830 reg = <0 0xe6590630 0 0x02>;
835 #clock-cells = <0>;
845 reg = <0 0xe65a0000 0 0x100>;
859 reg = <0 0xe65b0000 0 0x100>;
873 reg = <0 0xe65ee000 0 0x90>;
879 #phy-cells = <0>;
886 reg = <0 0xe6700000 0 0x10000>;
915 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
928 reg = <0 0xe7300000 0 0x10000>;
957 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
970 reg = <0 0xe7310000 0 0x10000>;
1011 reg = <0 0xe6740000 0 0x1000>;
1012 renesas,ipmmu-main = <&ipmmu_mm 0>;
1019 reg = <0 0xe7740000 0 0x1000>;
1027 reg = <0 0xe6570000 0 0x1000>;
1035 reg = <0 0xe67b0000 0 0x1000>;
1044 reg = <0 0xec670000 0 0x1000>;
1052 reg = <0 0xfd800000 0 0x1000>;
1060 reg = <0 0xfd950000 0 0x1000>;
1068 reg = <0 0xfe6b0000 0 0x1000>;
1076 reg = <0 0xfebd0000 0 0x1000>;
1085 reg = <0 0xe6800000 0 0x800>;
1123 rx-internal-delay-ps = <0>;
1124 tx-internal-delay-ps = <0>;
1127 #size-cells = <0>;
1134 reg = <0 0xe6c30000 0 0x1000>;
1150 reg = <0 0xe6c38000 0 0x1000>;
1166 reg = <0 0xe66c0000 0 0x8000>;
1191 reg = <0 0xe6e30000 0 0x8>;
1201 reg = <0 0xe6e31000 0 0x8>;
1211 reg = <0 0xe6e32000 0 0x8>;
1221 reg = <0 0xe6e33000 0 0x8>;
1231 reg = <0 0xe6e34000 0 0x8>;
1241 reg = <0 0xe6e35000 0 0x8>;
1251 reg = <0 0xe6e36000 0 0x8>;
1262 reg = <0 0xe6e60000 0 0x40>;
1268 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1269 <&dmac2 0x51>, <&dmac2 0x50>;
1279 reg = <0 0xe6e68000 0 0x40>;
1285 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1286 <&dmac2 0x53>, <&dmac2 0x52>;
1296 reg = <0 0xe6e88000 0 0x40>;
1302 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1303 <&dmac2 0x13>, <&dmac2 0x12>;
1313 reg = <0 0xe6c50000 0 0x40>;
1319 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1329 reg = <0 0xe6c40000 0 0x40>;
1335 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1345 reg = <0 0xe6f30000 0 0x40>;
1351 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
1352 <&dmac2 0x5b>, <&dmac2 0x5a>;
1362 reg = <0 0xe6e90000 0 0x0064>;
1365 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1366 <&dmac2 0x41>, <&dmac2 0x40>;
1371 #size-cells = <0>;
1378 reg = <0 0xe6ea0000 0 0x0064>;
1381 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
1382 <&dmac2 0x43>, <&dmac2 0x42>;
1387 #size-cells = <0>;
1394 reg = <0 0xe6c00000 0 0x0064>;
1397 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1402 #size-cells = <0>;
1409 reg = <0 0xe6c10000 0 0x0064>;
1412 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1417 #size-cells = <0>;
1423 reg = <0 0xe6ef0000 0 0x1000>;
1428 renesas,id = <0>;
1433 #size-cells = <0>;
1437 #size-cells = <0>;
1441 vin0csi20: endpoint@0 {
1442 reg = <0>;
1455 reg = <0 0xe6ef1000 0 0x1000>;
1465 #size-cells = <0>;
1469 #size-cells = <0>;
1473 vin1csi20: endpoint@0 {
1474 reg = <0>;
1487 reg = <0 0xe6ef2000 0 0x1000>;
1497 #size-cells = <0>;
1501 #size-cells = <0>;
1505 vin2csi20: endpoint@0 {
1506 reg = <0>;
1519 reg = <0 0xe6ef3000 0 0x1000>;
1529 #size-cells = <0>;
1533 #size-cells = <0>;
1537 vin3csi20: endpoint@0 {
1538 reg = <0>;
1551 reg = <0 0xe6ef4000 0 0x1000>;
1561 #size-cells = <0>;
1565 #size-cells = <0>;
1569 vin4csi20: endpoint@0 {
1570 reg = <0>;
1583 reg = <0 0xe6ef5000 0 0x1000>;
1593 #size-cells = <0>;
1597 #size-cells = <0>;
1601 vin5csi20: endpoint@0 {
1602 reg = <0>;
1615 reg = <0 0xe6ef6000 0 0x1000>;
1625 #size-cells = <0>;
1629 #size-cells = <0>;
1633 vin6csi20: endpoint@0 {
1634 reg = <0>;
1647 reg = <0 0xe6ef7000 0 0x1000>;
1657 #size-cells = <0>;
1661 #size-cells = <0>;
1665 vin7csi20: endpoint@0 {
1666 reg = <0>;
1681 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1687 * clkout : #clock-cells = <0>; <&rcar_sound>;
1691 reg = <0 0xec500000 0 0x1000>, /* SCU */
1692 <0 0xec5a0000 0 0x100>, /* ADG */
1693 <0 0xec540000 0 0x1000>, /* SSIU */
1694 <0 0xec541000 0 0x280>, /* SSI */
1695 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1718 "ssi.1", "ssi.0",
1721 "src.1", "src.0",
1722 "mix.1", "mix.0",
1723 "ctu.1", "ctu.0",
1724 "dvc.0", "dvc.1",
1736 "ssi.1", "ssi.0";
1740 ctu00: ctu-0 { };
1751 dvc0: dvc-0 {
1752 dmas = <&audma1 0xbc>;
1756 dmas = <&audma1 0xbe>;
1762 mix0: mix-0 { };
1767 src0: src-0 {
1769 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1774 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1779 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1784 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1789 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1794 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1799 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1804 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1809 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1814 dmas = <&audma0 0x97>, <&audma1 0xba>;
1820 ssi0: ssi-0 {
1822 dmas = <&audma0 0x01>, <&audma1 0x02>;
1827 dmas = <&audma0 0x03>, <&audma1 0x04>;
1832 dmas = <&audma0 0x05>, <&audma1 0x06>;
1837 dmas = <&audma0 0x07>, <&audma1 0x08>;
1842 dmas = <&audma0 0x09>, <&audma1 0x0a>;
1847 dmas = <&audma0 0x0b>, <&audma1 0x0c>;
1852 dmas = <&audma0 0x0d>, <&audma1 0x0e>;
1857 dmas = <&audma0 0x0f>, <&audma1 0x10>;
1862 dmas = <&audma0 0x11>, <&audma1 0x12>;
1867 dmas = <&audma0 0x13>, <&audma1 0x14>;
1873 ssiu00: ssiu-0 {
1874 dmas = <&audma0 0x15>, <&audma1 0x16>;
1878 dmas = <&audma0 0x35>, <&audma1 0x36>;
1882 dmas = <&audma0 0x37>, <&audma1 0x38>;
1886 dmas = <&audma0 0x47>, <&audma1 0x48>;
1890 dmas = <&audma0 0x3F>, <&audma1 0x40>;
1894 dmas = <&audma0 0x43>, <&audma1 0x44>;
1898 dmas = <&audma0 0x4F>, <&audma1 0x50>;
1902 dmas = <&audma0 0x53>, <&audma1 0x54>;
1906 dmas = <&audma0 0x49>, <&audma1 0x4a>;
1910 dmas = <&audma0 0x4B>, <&audma1 0x4C>;
1914 dmas = <&audma0 0x57>, <&audma1 0x58>;
1918 dmas = <&audma0 0x59>, <&audma1 0x5A>;
1922 dmas = <&audma0 0x5F>, <&audma1 0x60>;
1926 dmas = <&audma0 0xC3>, <&audma1 0xC4>;
1930 dmas = <&audma0 0xC7>, <&audma1 0xC8>;
1934 dmas = <&audma0 0xCB>, <&audma1 0xCC>;
1938 dmas = <&audma0 0x63>, <&audma1 0x64>;
1942 dmas = <&audma0 0x67>, <&audma1 0x68>;
1946 dmas = <&audma0 0x6B>, <&audma1 0x6C>;
1950 dmas = <&audma0 0x6D>, <&audma1 0x6E>;
1954 dmas = <&audma0 0xCF>, <&audma1 0xCE>;
1958 dmas = <&audma0 0xEB>, <&audma1 0xEC>;
1962 dmas = <&audma0 0xED>, <&audma1 0xEE>;
1966 dmas = <&audma0 0xEF>, <&audma1 0xF0>;
1970 dmas = <&audma0 0x6f>, <&audma1 0x70>;
1974 dmas = <&audma0 0x21>, <&audma1 0x22>;
1978 dmas = <&audma0 0x23>, <&audma1 0x24>;
1982 dmas = <&audma0 0x25>, <&audma1 0x26>;
1986 dmas = <&audma0 0x27>, <&audma1 0x28>;
1990 dmas = <&audma0 0x29>, <&audma1 0x2A>;
1994 dmas = <&audma0 0x2B>, <&audma1 0x2C>;
1998 dmas = <&audma0 0x2D>, <&audma1 0x2E>;
2002 dmas = <&audma0 0x71>, <&audma1 0x72>;
2006 dmas = <&audma0 0x17>, <&audma1 0x18>;
2010 dmas = <&audma0 0x19>, <&audma1 0x1A>;
2014 dmas = <&audma0 0x1B>, <&audma1 0x1C>;
2018 dmas = <&audma0 0x1D>, <&audma1 0x1E>;
2022 dmas = <&audma0 0x1F>, <&audma1 0x20>;
2026 dmas = <&audma0 0x31>, <&audma1 0x32>;
2030 dmas = <&audma0 0x33>, <&audma1 0x34>;
2034 dmas = <&audma0 0x73>, <&audma1 0x74>;
2038 dmas = <&audma0 0x75>, <&audma1 0x76>;
2042 dmas = <&audma0 0x79>, <&audma1 0x7a>;
2046 dmas = <&audma0 0x7b>, <&audma1 0x7c>;
2050 dmas = <&audma0 0x7d>, <&audma1 0x7e>;
2054 dmas = <&audma0 0x7F>, <&audma1 0x80>;
2058 dmas = <&audma0 0x81>, <&audma1 0x82>;
2062 dmas = <&audma0 0x83>, <&audma1 0x84>;
2066 dmas = <&audma0 0xA3>, <&audma1 0xA4>;
2070 dmas = <&audma0 0xA5>, <&audma1 0xA6>;
2074 dmas = <&audma0 0xA7>, <&audma1 0xA8>;
2078 dmas = <&audma0 0xA9>, <&audma1 0xAA>;
2087 reg = <0 0xec700000 0 0x10000>;
2116 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
2129 reg = <0 0xec720000 0 0x10000>;
2171 reg = <0 0xee000000 0 0xc00>;
2182 reg = <0 0xee020000 0 0x400>;
2192 reg = <0 0xee080000 0 0x100>;
2204 reg = <0 0xee0a0000 0 0x100>;
2216 reg = <0 0xee080100 0 0x100>;
2229 reg = <0 0xee0a0100 0 0x100>;
2243 reg = <0 0xee080200 0 0x700>;
2255 reg = <0 0xee0a0200 0 0x700>;
2266 reg = <0 0xee100000 0 0x2000>;
2279 reg = <0 0xee120000 0 0x2000>;
2292 reg = <0 0xee140000 0 0x2000>;
2305 reg = <0 0xee160000 0 0x2000>;
2318 reg = <0 0xee200000 0 0x200>,
2319 <0 0x08000000 0 0x4000000>,
2320 <0 0xee208000 0 0x100>;
2327 #size-cells = <0>;
2334 #address-cells = <0>;
2336 reg = <0x0 0xf1010000 0 0x1000>,
2337 <0x0 0xf1020000 0 0x20000>,
2338 <0x0 0xf1040000 0 0x20000>,
2339 <0x0 0xf1060000 0 0x20000>;
2351 reg = <0 0xfe000000 0 0x80000>;
2354 bus-range = <0x00 0xff>;
2356 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
2357 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
2358 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
2359 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
2361 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
2366 interrupt-map-mask = <0 0 0 0>;
2367 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
2372 iommu-map = <0 &ipmmu_hc 0 1>;
2373 iommu-map-mask = <0>;
2380 reg = <0 0xee800000 0 0x80000>;
2383 bus-range = <0x00 0xff>;
2385 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
2386 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
2387 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
2388 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
2390 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
2395 interrupt-map-mask = <0 0 0 0>;
2396 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2401 iommu-map = <0 &ipmmu_hc 1 1>;
2402 iommu-map-mask = <0>;
2409 reg = <0x0 0xfe000000 0 0x80000>,
2410 <0x0 0xfe100000 0 0x100000>,
2411 <0x0 0xfe200000 0 0x200000>,
2412 <0x0 0x30000000 0 0x8000000>,
2413 <0x0 0x38000000 0 0x8000000>;
2428 reg = <0x0 0xee800000 0 0x80000>,
2429 <0x0 0xee900000 0 0x100000>,
2430 <0x0 0xeea00000 0 0x200000>,
2431 <0x0 0xc0000000 0 0x8000000>,
2432 <0x0 0xc8000000 0 0x8000000>;
2446 reg = <0 0xfe940000 0 0x2400>;
2456 reg = <0 0xfe950000 0 0x200>;
2464 reg = <0 0xfe96f000 0 0x200>;
2472 reg = <0 0xfea27000 0 0x200>;
2481 reg = <0 0xfea2f000 0 0x200>;
2490 reg = <0 0xfea37000 0 0x200>;
2499 reg = <0 0xfe9af000 0 0x200>;
2508 reg = <0 0xfe960000 0 0x8000>;
2519 reg = <0 0xfea20000 0 0x5000>;
2530 reg = <0 0xfea28000 0 0x5000>;
2541 reg = <0 0xfea30000 0 0x5000>;
2552 reg = <0 0xfe9a0000 0 0x8000>;
2563 reg = <0 0xfea80000 0 0x10000>;
2572 #size-cells = <0>;
2574 port@0 {
2575 reg = <0>;
2580 #size-cells = <0>;
2584 csi20vin0: endpoint@0 {
2585 reg = <0>;
2622 reg = <0 0xfeaa0000 0 0x10000>;
2631 #size-cells = <0>;
2633 port@0 {
2634 reg = <0>;
2639 #size-cells = <0>;
2643 csi40vin0: endpoint@0 {
2644 reg = <0>;
2683 reg = <0 0xfead0000 0 0x10000>;
2694 #size-cells = <0>;
2695 port@0 {
2696 reg = <0>;
2713 reg = <0 0xfeb00000 0 0x70000>;
2719 clock-names = "du.0", "du.1", "du.2";
2721 reset-names = "du.0", "du.2";
2724 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>;
2728 #size-cells = <0>;
2730 port@0 {
2731 reg = <0>;
2750 reg = <0 0xfeb90000 0 0x14>;
2758 #size-cells = <0>;
2760 port@0 {
2761 reg = <0>;
2774 reg = <0 0xfff00044 0 4>;
2782 thermal-sensors = <&tsc 0>;
2818 cooling-device = <&a57_0 0 2>;
2823 cooling-device = <&a53_0 0 2>;
2854 #clock-cells = <0>;
2855 clock-frequency = <0>;
2860 #clock-cells = <0>;
2861 clock-frequency = <0>;