Lines Matching +full:cpu +full:- +full:syscon
1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <1>;
15 #size-cells = <1>;
17 reserved-memory {
18 #address-cells = <1>;
19 #size-cells = <1>;
32 no-map;
37 #address-cells = <1>;
38 #size-cells = <0>;
40 cpu0: cpu@0 {
41 device_type = "cpu";
42 compatible = "arm,cortex-a55";
44 enable-method = "psci";
45 next-level-cache = <&l2>;
48 cpu1: cpu@100 {
49 device_type = "cpu";
50 compatible = "arm,cortex-a55";
52 enable-method = "psci";
53 next-level-cache = <&l3>;
56 cpu2: cpu@200 {
57 device_type = "cpu";
58 compatible = "arm,cortex-a55";
60 enable-method = "psci";
61 next-level-cache = <&l3>;
64 cpu3: cpu@300 {
65 device_type = "cpu";
66 compatible = "arm,cortex-a55";
68 enable-method = "psci";
69 next-level-cache = <&l3>;
72 cpu4: cpu@400 {
73 device_type = "cpu";
74 compatible = "arm,cortex-a55";
76 enable-method = "psci";
77 next-level-cache = <&l3>;
80 cpu5: cpu@500 {
81 device_type = "cpu";
82 compatible = "arm,cortex-a55";
84 enable-method = "psci";
85 next-level-cache = <&l3>;
88 l2: l2-cache {
90 next-level-cache = <&l3>;
91 cache-level = <2>;
92 cache-unified;
96 l3: l3-cache {
98 cache-level = <3>;
99 cache-unified;
104 compatible = "arm,armv8-timer";
112 compatible = "arm,armv8-pmuv3";
114 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>,
119 compatible = "arm,psci-1.0";
124 compatible = "fixed-clock";
125 clock-frequency = <27000000>;
126 clock-output-names = "osc27M";
127 #clock-cells = <0>;
131 compatible = "simple-bus";
132 #address-cells = <1>;
133 #size-cells = <1>;
138 compatible = "simple-bus";
140 #address-cells = <1>;
141 #size-cells = <1>;
144 crt: syscon@0 {
145 compatible = "syscon", "simple-mfd";
147 reg-io-width = <4>;
148 #address-cells = <1>;
149 #size-cells = <1>;
153 iso: syscon@7000 {
154 compatible = "syscon", "simple-mfd";
156 reg-io-width = <4>;
157 #address-cells = <1>;
158 #size-cells = <1>;
162 sb2: syscon@1a000 {
163 compatible = "syscon", "simple-mfd";
165 reg-io-width = <4>;
166 #address-cells = <1>;
167 #size-cells = <1>;
171 misc: syscon@1b000 {
172 compatible = "syscon", "simple-mfd";
174 reg-io-width = <4>;
175 #address-cells = <1>;
176 #size-cells = <1>;
180 scpu_wrapper: syscon@1d000 {
181 compatible = "syscon", "simple-mfd";
183 reg-io-width = <4>;
184 #address-cells = <1>;
185 #size-cells = <1>;
190 gic: interrupt-controller@ff100000 {
191 compatible = "arm,gic-v3";
195 interrupt-controller;
196 #interrupt-cells = <3>;
203 compatible = "snps,dw-apb-uart";
205 reg-shift = <2>;
206 reg-io-width = <4>;
208 clock-frequency = <27000000>;
215 compatible = "snps,dw-apb-uart";
217 reg-shift = <2>;
218 reg-io-width = <4>;
220 clock-frequency = <432000000>;
225 compatible = "snps,dw-apb-uart";
227 reg-shift = <2>;
228 reg-io-width = <4>;
230 clock-frequency = <432000000>;