Lines Matching +full:sm8350 +full:- +full:rpmhpd
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sm8450-videocc.h>
8 #include <dt-bindings/clock/qcom,sm8550-camcc.h>
9 #include <dt-bindings/clock/qcom,sm8550-gcc.h>
10 #include <dt-bindings/clock/qcom,sm8550-gpucc.h>
11 #include <dt-bindings/clock/qcom,sm8550-tcsr.h>
12 #include <dt-bindings/clock/qcom,sm8550-dispcc.h>
13 #include <dt-bindings/dma/qcom-gpi.h>
14 #include <dt-bindings/firmware/qcom,scm.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
18 #include <dt-bindings/mailbox/qcom-ipcc.h>
19 #include <dt-bindings/power/qcom-rpmpd.h>
20 #include <dt-bindings/power/qcom,rpmhpd.h>
21 #include <dt-bindings/soc/qcom,gpr.h>
22 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
23 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
24 #include <dt-bindings/phy/phy-qcom-qmp.h>
25 #include <dt-bindings/thermal/thermal.h>
28 interrupt-parent = <&intc>;
30 #address-cells = <2>;
31 #size-cells = <2>;
36 xo_board: xo-board {
37 compatible = "fixed-clock";
38 #clock-cells = <0>;
41 sleep_clk: sleep-clk {
42 compatible = "fixed-clock";
43 #clock-cells = <0>;
46 bi_tcxo_div2: bi-tcxo-div2-clk {
47 #clock-cells = <0>;
48 compatible = "fixed-factor-clock";
50 clock-mult = <1>;
51 clock-div = <2>;
54 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
55 #clock-cells = <0>;
56 compatible = "fixed-factor-clock";
58 clock-mult = <1>;
59 clock-div = <2>;
62 pcie_1_phy_aux_clk: pcie-1-phy-aux-clk {
63 compatible = "fixed-clock";
64 #clock-cells = <0>;
69 #address-cells = <2>;
70 #size-cells = <0>;
74 compatible = "arm,cortex-a510";
77 enable-method = "psci";
78 next-level-cache = <&L2_0>;
79 power-domains = <&CPU_PD0>;
80 power-domain-names = "psci";
81 qcom,freq-domain = <&cpufreq_hw 0>;
82 capacity-dmips-mhz = <1024>;
83 dynamic-power-coefficient = <100>;
84 #cooling-cells = <2>;
85 L2_0: l2-cache {
87 cache-level = <2>;
88 cache-unified;
89 next-level-cache = <&L3_0>;
90 L3_0: l3-cache {
92 cache-level = <3>;
93 cache-unified;
100 compatible = "arm,cortex-a510";
103 enable-method = "psci";
104 next-level-cache = <&L2_100>;
105 power-domains = <&CPU_PD1>;
106 power-domain-names = "psci";
107 qcom,freq-domain = <&cpufreq_hw 0>;
108 capacity-dmips-mhz = <1024>;
109 dynamic-power-coefficient = <100>;
110 #cooling-cells = <2>;
111 L2_100: l2-cache {
113 cache-level = <2>;
114 cache-unified;
115 next-level-cache = <&L3_0>;
121 compatible = "arm,cortex-a510";
124 enable-method = "psci";
125 next-level-cache = <&L2_200>;
126 power-domains = <&CPU_PD2>;
127 power-domain-names = "psci";
128 qcom,freq-domain = <&cpufreq_hw 0>;
129 capacity-dmips-mhz = <1024>;
130 dynamic-power-coefficient = <100>;
131 #cooling-cells = <2>;
132 L2_200: l2-cache {
134 cache-level = <2>;
135 cache-unified;
136 next-level-cache = <&L3_0>;
142 compatible = "arm,cortex-a715";
145 enable-method = "psci";
146 next-level-cache = <&L2_300>;
147 power-domains = <&CPU_PD3>;
148 power-domain-names = "psci";
149 qcom,freq-domain = <&cpufreq_hw 1>;
150 capacity-dmips-mhz = <1792>;
151 dynamic-power-coefficient = <270>;
152 #cooling-cells = <2>;
153 L2_300: l2-cache {
155 cache-level = <2>;
156 cache-unified;
157 next-level-cache = <&L3_0>;
163 compatible = "arm,cortex-a715";
166 enable-method = "psci";
167 next-level-cache = <&L2_400>;
168 power-domains = <&CPU_PD4>;
169 power-domain-names = "psci";
170 qcom,freq-domain = <&cpufreq_hw 1>;
171 capacity-dmips-mhz = <1792>;
172 dynamic-power-coefficient = <270>;
173 #cooling-cells = <2>;
174 L2_400: l2-cache {
176 cache-level = <2>;
177 cache-unified;
178 next-level-cache = <&L3_0>;
184 compatible = "arm,cortex-a710";
187 enable-method = "psci";
188 next-level-cache = <&L2_500>;
189 power-domains = <&CPU_PD5>;
190 power-domain-names = "psci";
191 qcom,freq-domain = <&cpufreq_hw 1>;
192 capacity-dmips-mhz = <1792>;
193 dynamic-power-coefficient = <270>;
194 #cooling-cells = <2>;
195 L2_500: l2-cache {
197 cache-level = <2>;
198 cache-unified;
199 next-level-cache = <&L3_0>;
205 compatible = "arm,cortex-a710";
208 enable-method = "psci";
209 next-level-cache = <&L2_600>;
210 power-domains = <&CPU_PD6>;
211 power-domain-names = "psci";
212 qcom,freq-domain = <&cpufreq_hw 1>;
213 capacity-dmips-mhz = <1792>;
214 dynamic-power-coefficient = <270>;
215 #cooling-cells = <2>;
216 L2_600: l2-cache {
218 cache-level = <2>;
219 cache-unified;
220 next-level-cache = <&L3_0>;
226 compatible = "arm,cortex-x3";
229 enable-method = "psci";
230 next-level-cache = <&L2_700>;
231 power-domains = <&CPU_PD7>;
232 power-domain-names = "psci";
233 qcom,freq-domain = <&cpufreq_hw 2>;
234 capacity-dmips-mhz = <1894>;
235 dynamic-power-coefficient = <588>;
236 #cooling-cells = <2>;
237 L2_700: l2-cache {
239 cache-level = <2>;
240 cache-unified;
241 next-level-cache = <&L3_0>;
245 cpu-map {
281 idle-states {
282 entry-method = "psci";
284 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
285 compatible = "arm,idle-state";
286 idle-state-name = "silver-rail-power-collapse";
287 arm,psci-suspend-param = <0x40000004>;
288 entry-latency-us = <550>;
289 exit-latency-us = <750>;
290 min-residency-us = <6700>;
291 local-timer-stop;
294 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
295 compatible = "arm,idle-state";
296 idle-state-name = "gold-rail-power-collapse";
297 arm,psci-suspend-param = <0x40000004>;
298 entry-latency-us = <600>;
299 exit-latency-us = <1300>;
300 min-residency-us = <8136>;
301 local-timer-stop;
304 PRIME_CPU_SLEEP_0: cpu-sleep-2-0 {
305 compatible = "arm,idle-state";
306 idle-state-name = "goldplus-rail-power-collapse";
307 arm,psci-suspend-param = <0x40000004>;
308 entry-latency-us = <500>;
309 exit-latency-us = <1350>;
310 min-residency-us = <7480>;
311 local-timer-stop;
315 domain-idle-states {
316 CLUSTER_SLEEP_0: cluster-sleep-0 {
317 compatible = "domain-idle-state";
318 arm,psci-suspend-param = <0x41000044>;
319 entry-latency-us = <750>;
320 exit-latency-us = <2350>;
321 min-residency-us = <9144>;
324 CLUSTER_SLEEP_1: cluster-sleep-1 {
325 compatible = "domain-idle-state";
326 arm,psci-suspend-param = <0x4100c344>;
327 entry-latency-us = <2800>;
328 exit-latency-us = <4400>;
329 min-residency-us = <10150>;
336 compatible = "qcom,scm-sm8550", "qcom,scm";
337 qcom,dload-mode = <&tcsr 0x19000>;
342 clk_virt: interconnect-0 {
343 compatible = "qcom,sm8550-clk-virt";
344 #interconnect-cells = <2>;
345 qcom,bcm-voters = <&apps_bcm_voter>;
348 mc_virt: interconnect-1 {
349 compatible = "qcom,sm8550-mc-virt";
350 #interconnect-cells = <2>;
351 qcom,bcm-voters = <&apps_bcm_voter>;
361 compatible = "arm,armv8-pmuv3";
366 compatible = "arm,psci-1.0";
369 CPU_PD0: power-domain-cpu0 {
370 #power-domain-cells = <0>;
371 power-domains = <&CLUSTER_PD>;
372 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
375 CPU_PD1: power-domain-cpu1 {
376 #power-domain-cells = <0>;
377 power-domains = <&CLUSTER_PD>;
378 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
381 CPU_PD2: power-domain-cpu2 {
382 #power-domain-cells = <0>;
383 power-domains = <&CLUSTER_PD>;
384 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
387 CPU_PD3: power-domain-cpu3 {
388 #power-domain-cells = <0>;
389 power-domains = <&CLUSTER_PD>;
390 domain-idle-states = <&BIG_CPU_SLEEP_0>;
393 CPU_PD4: power-domain-cpu4 {
394 #power-domain-cells = <0>;
395 power-domains = <&CLUSTER_PD>;
396 domain-idle-states = <&BIG_CPU_SLEEP_0>;
399 CPU_PD5: power-domain-cpu5 {
400 #power-domain-cells = <0>;
401 power-domains = <&CLUSTER_PD>;
402 domain-idle-states = <&BIG_CPU_SLEEP_0>;
405 CPU_PD6: power-domain-cpu6 {
406 #power-domain-cells = <0>;
407 power-domains = <&CLUSTER_PD>;
408 domain-idle-states = <&BIG_CPU_SLEEP_0>;
411 CPU_PD7: power-domain-cpu7 {
412 #power-domain-cells = <0>;
413 power-domains = <&CLUSTER_PD>;
414 domain-idle-states = <&PRIME_CPU_SLEEP_0>;
417 CLUSTER_PD: power-domain-cluster {
418 #power-domain-cells = <0>;
419 domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>;
423 reserved_memory: reserved-memory {
424 #address-cells = <2>;
425 #size-cells = <2>;
428 hyp_mem: hyp-region@80000000 {
430 no-map;
433 cpusys_vm_mem: cpusys-vm-region@80a00000 {
435 no-map;
438 hyp_tags_mem: hyp-tags-region@80e00000 {
440 no-map;
443 xbl_sc_mem: xbl-sc-region@d8100000 {
445 no-map;
448 hyp_tags_reserved_mem: hyp-tags-reserved-region@811d0000 {
450 no-map;
454 xbl_dt_log_merged_mem: xbl-dt-log-merged-region@81a00000 {
456 no-map;
459 aop_cmd_db_mem: aop-cmd-db-region@81c60000 {
460 compatible = "qcom,cmd-db";
462 no-map;
466 aop_config_merged_mem: aop-config-merged-region@81c80000 {
468 no-map;
476 no-map;
479 adsp_mhi_mem: adsp-mhi-region@81f00000 {
481 no-map;
484 global_sync_mem: global-sync-region@82600000 {
486 no-map;
489 tz_stat_mem: tz-stat-region@82700000 {
491 no-map;
494 cdsp_secure_heap_mem: cdsp-secure-heap-region@82800000 {
496 no-map;
499 mpss_mem: mpss-region@8a800000 {
501 no-map;
504 q6_mpss_dtb_mem: q6-mpss-dtb-region@9b000000 {
506 no-map;
509 ipa_fw_mem: ipa-fw-region@9b080000 {
511 no-map;
514 ipa_gsi_mem: ipa-gsi-region@9b090000 {
516 no-map;
519 gpu_micro_code_mem: gpu-micro-code-region@9b09a000 {
521 no-map;
524 spss_region_mem: spss-region@9b100000 {
526 no-map;
530 spu_tz_shared_mem: spu-tz-shared-region@9b280000 {
532 no-map;
536 spu_modem_shared_mem: spu-modem-shared-region@9b2e0000 {
538 no-map;
541 camera_mem: camera-region@9b300000 {
543 no-map;
546 video_mem: video-region@9bb00000 {
548 no-map;
551 cvp_mem: cvp-region@9c200000 {
553 no-map;
556 cdsp_mem: cdsp-region@9c900000 {
558 no-map;
561 q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9e900000 {
563 no-map;
566 q6_adsp_dtb_mem: q6-adsp-dtb-region@9e980000 {
568 no-map;
571 adspslpi_mem: adspslpi-region@9ea00000 {
573 no-map;
580 rmtfs_mem: rmtfs-region@d4a80000 {
581 compatible = "qcom,rmtfs-mem";
583 no-map;
585 qcom,client-id = <1>;
589 mpss_dsm_mem: mpss-dsm-region@d4d00000 {
591 no-map;
594 tz_reserved_mem: tz-reserved-region@d8000000 {
596 no-map;
599 cpucp_fw_mem: cpucp-fw-region@d8140000 {
601 no-map;
604 qtee_mem: qtee-region@d8300000 {
606 no-map;
609 ta_mem: ta-region@d8800000 {
611 no-map;
614 tz_tags_mem: tz-tags-region@e1200000 {
616 no-map;
619 hwfence_shbuf: hwfence-shbuf-region@e6440000 {
621 no-map;
624 trust_ui_vm_mem: trust-ui-vm-region@f3600000 {
626 no-map;
629 trust_ui_vm_dump: trust-ui-vm-dump-region@f80ee000 {
631 no-map;
634 trust_ui_vm_qrtr: trust-ui-vm-qrt-region@f80ef000 {
636 no-map;
639 trust_ui_vm_vblk0_ring: trust-ui-vm-vblk0-ring-region@f80f8000 {
641 no-map;
644 trust_ui_vm_vblk1_ring: trust-ui-vm-vblk1-ring-region@f80fc000 {
646 no-map;
649 trust_ui_vm_swiotlb: trust-ui-vm-swiotlb-region@f8100000 {
651 no-map;
654 oem_vm_mem: oem-vm-region@f8400000 {
656 no-map;
659 oem_vm_vblk0_ring: oem-vm-vblk0-ring-region@fcc00000 {
661 no-map;
664 oem_vm_swiotlb: oem-vm-swiotlb-region@fcc04000 {
666 no-map;
669 hyp_ext_tags_mem: hyp-ext-tags-region@fce00000 {
671 no-map;
674 hyp_ext_reserved_mem: hyp-ext-reserved-region@ff700000 {
676 no-map;
680 smp2p-adsp {
683 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
689 qcom,local-pid = <0>;
690 qcom,remote-pid = <2>;
692 smp2p_adsp_out: master-kernel {
693 qcom,entry-name = "master-kernel";
694 #qcom,smem-state-cells = <1>;
697 smp2p_adsp_in: slave-kernel {
698 qcom,entry-name = "slave-kernel";
699 interrupt-controller;
700 #interrupt-cells = <2>;
704 smp2p-cdsp {
707 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
713 qcom,local-pid = <0>;
714 qcom,remote-pid = <5>;
716 smp2p_cdsp_out: master-kernel {
717 qcom,entry-name = "master-kernel";
718 #qcom,smem-state-cells = <1>;
721 smp2p_cdsp_in: slave-kernel {
722 qcom,entry-name = "slave-kernel";
723 interrupt-controller;
724 #interrupt-cells = <2>;
728 smp2p-modem {
731 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
737 qcom,local-pid = <0>;
738 qcom,remote-pid = <1>;
740 smp2p_modem_out: master-kernel {
741 qcom,entry-name = "master-kernel";
742 #qcom,smem-state-cells = <1>;
745 smp2p_modem_in: slave-kernel {
746 qcom,entry-name = "slave-kernel";
747 interrupt-controller;
748 #interrupt-cells = <2>;
751 ipa_smp2p_out: ipa-ap-to-modem {
752 qcom,entry-name = "ipa";
753 #qcom,smem-state-cells = <1>;
756 ipa_smp2p_in: ipa-modem-to-ap {
757 qcom,entry-name = "ipa";
758 interrupt-controller;
759 #interrupt-cells = <2>;
764 compatible = "simple-bus";
766 dma-ranges = <0 0 0 0 0x10 0>;
768 #address-cells = <2>;
769 #size-cells = <2>;
771 gcc: clock-controller@100000 {
772 compatible = "qcom,sm8550-gcc";
774 #clock-cells = <1>;
775 #reset-cells = <1>;
776 #power-domain-cells = <1>;
788 compatible = "qcom,sm8550-ipcc", "qcom,ipcc";
791 interrupt-controller;
792 #interrupt-cells = <3>;
793 #mbox-cells = <2>;
796 gpi_dma2: dma-controller@800000 {
797 compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma";
798 #dma-cells = <3>;
812 dma-channels = <12>;
813 dma-channel-mask = <0x3e>;
819 compatible = "qcom,geni-se-qup";
822 clock-names = "m-ahb", "s-ahb";
826 #address-cells = <2>;
827 #size-cells = <2>;
831 compatible = "qcom,geni-i2c";
833 clock-names = "se";
835 pinctrl-names = "default";
836 pinctrl-0 = <&qup_i2c8_data_clk>;
838 #address-cells = <1>;
839 #size-cells = <0>;
843 interconnect-names = "qup-core", "qup-config", "qup-memory";
846 dma-names = "tx", "rx";
851 compatible = "qcom,geni-spi";
853 clock-names = "se";
856 pinctrl-names = "default";
857 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
861 interconnect-names = "qup-core", "qup-config", "qup-memory";
864 dma-names = "tx", "rx";
865 #address-cells = <1>;
866 #size-cells = <0>;
871 compatible = "qcom,geni-i2c";
873 clock-names = "se";
875 pinctrl-names = "default";
876 pinctrl-0 = <&qup_i2c9_data_clk>;
878 #address-cells = <1>;
879 #size-cells = <0>;
883 interconnect-names = "qup-core", "qup-config", "qup-memory";
886 dma-names = "tx", "rx";
891 compatible = "qcom,geni-spi";
893 clock-names = "se";
896 pinctrl-names = "default";
897 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
901 interconnect-names = "qup-core", "qup-config", "qup-memory";
904 dma-names = "tx", "rx";
905 #address-cells = <1>;
906 #size-cells = <0>;
911 compatible = "qcom,geni-i2c";
913 clock-names = "se";
915 pinctrl-names = "default";
916 pinctrl-0 = <&qup_i2c10_data_clk>;
918 #address-cells = <1>;
919 #size-cells = <0>;
923 interconnect-names = "qup-core", "qup-config", "qup-memory";
926 dma-names = "tx", "rx";
931 compatible = "qcom,geni-spi";
933 clock-names = "se";
936 pinctrl-names = "default";
937 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
941 interconnect-names = "qup-core", "qup-config", "qup-memory";
944 dma-names = "tx", "rx";
945 #address-cells = <1>;
946 #size-cells = <0>;
951 compatible = "qcom,geni-i2c";
953 clock-names = "se";
955 pinctrl-names = "default";
956 pinctrl-0 = <&qup_i2c11_data_clk>;
958 #address-cells = <1>;
959 #size-cells = <0>;
963 interconnect-names = "qup-core", "qup-config", "qup-memory";
966 dma-names = "tx", "rx";
971 compatible = "qcom,geni-spi";
973 clock-names = "se";
976 pinctrl-names = "default";
977 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
981 interconnect-names = "qup-core", "qup-config", "qup-memory";
984 dma-names = "tx", "rx";
985 #address-cells = <1>;
986 #size-cells = <0>;
991 compatible = "qcom,geni-i2c";
993 clock-names = "se";
995 pinctrl-names = "default";
996 pinctrl-0 = <&qup_i2c12_data_clk>;
998 #address-cells = <1>;
999 #size-cells = <0>;
1003 interconnect-names = "qup-core", "qup-config", "qup-memory";
1006 dma-names = "tx", "rx";
1011 compatible = "qcom,geni-spi";
1013 clock-names = "se";
1016 pinctrl-names = "default";
1017 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1021 interconnect-names = "qup-core", "qup-config", "qup-memory";
1024 dma-names = "tx", "rx";
1025 #address-cells = <1>;
1026 #size-cells = <0>;
1031 compatible = "qcom,geni-i2c";
1033 clock-names = "se";
1035 pinctrl-names = "default";
1036 pinctrl-0 = <&qup_i2c13_data_clk>;
1038 #address-cells = <1>;
1039 #size-cells = <0>;
1043 interconnect-names = "qup-core", "qup-config", "qup-memory";
1046 dma-names = "tx", "rx";
1051 compatible = "qcom,geni-spi";
1053 clock-names = "se";
1056 pinctrl-names = "default";
1057 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1061 interconnect-names = "qup-core", "qup-config", "qup-memory";
1064 dma-names = "tx", "rx";
1065 #address-cells = <1>;
1066 #size-cells = <0>;
1071 compatible = "qcom,geni-uart";
1073 clock-names = "se";
1075 pinctrl-names = "default";
1076 pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>;
1080 interconnect-names = "qup-core", "qup-config";
1085 compatible = "qcom,geni-i2c";
1087 clock-names = "se";
1089 pinctrl-names = "default";
1090 pinctrl-0 = <&qup_i2c15_data_clk>;
1092 #address-cells = <1>;
1093 #size-cells = <0>;
1097 interconnect-names = "qup-core", "qup-config", "qup-memory";
1100 dma-names = "tx", "rx";
1105 compatible = "qcom,geni-spi";
1107 clock-names = "se";
1110 pinctrl-names = "default";
1111 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
1115 interconnect-names = "qup-core", "qup-config", "qup-memory";
1118 dma-names = "tx", "rx";
1119 #address-cells = <1>;
1120 #size-cells = <0>;
1126 compatible = "qcom,geni-se-i2c-master-hub";
1128 clock-names = "s-ahb";
1130 #address-cells = <2>;
1131 #size-cells = <2>;
1136 compatible = "qcom,geni-i2c-master-hub";
1138 clock-names = "se", "core";
1141 pinctrl-names = "default";
1142 pinctrl-0 = <&hub_i2c0_data_clk>;
1144 #address-cells = <1>;
1145 #size-cells = <0>;
1148 interconnect-names = "qup-core", "qup-config";
1153 compatible = "qcom,geni-i2c-master-hub";
1155 clock-names = "se", "core";
1158 pinctrl-names = "default";
1159 pinctrl-0 = <&hub_i2c1_data_clk>;
1161 #address-cells = <1>;
1162 #size-cells = <0>;
1165 interconnect-names = "qup-core", "qup-config";
1170 compatible = "qcom,geni-i2c-master-hub";
1172 clock-names = "se", "core";
1175 pinctrl-names = "default";
1176 pinctrl-0 = <&hub_i2c2_data_clk>;
1178 #address-cells = <1>;
1179 #size-cells = <0>;
1182 interconnect-names = "qup-core", "qup-config";
1187 compatible = "qcom,geni-i2c-master-hub";
1189 clock-names = "se", "core";
1192 pinctrl-names = "default";
1193 pinctrl-0 = <&hub_i2c3_data_clk>;
1195 #address-cells = <1>;
1196 #size-cells = <0>;
1199 interconnect-names = "qup-core", "qup-config";
1204 compatible = "qcom,geni-i2c-master-hub";
1206 clock-names = "se", "core";
1209 pinctrl-names = "default";
1210 pinctrl-0 = <&hub_i2c4_data_clk>;
1212 #address-cells = <1>;
1213 #size-cells = <0>;
1216 interconnect-names = "qup-core", "qup-config";
1221 compatible = "qcom,geni-i2c-master-hub";
1223 clock-names = "se", "core";
1226 pinctrl-names = "default";
1227 pinctrl-0 = <&hub_i2c5_data_clk>;
1229 #address-cells = <1>;
1230 #size-cells = <0>;
1233 interconnect-names = "qup-core", "qup-config";
1238 compatible = "qcom,geni-i2c-master-hub";
1240 clock-names = "se", "core";
1243 pinctrl-names = "default";
1244 pinctrl-0 = <&hub_i2c6_data_clk>;
1246 #address-cells = <1>;
1247 #size-cells = <0>;
1250 interconnect-names = "qup-core", "qup-config";
1255 compatible = "qcom,geni-i2c-master-hub";
1257 clock-names = "se", "core";
1260 pinctrl-names = "default";
1261 pinctrl-0 = <&hub_i2c7_data_clk>;
1263 #address-cells = <1>;
1264 #size-cells = <0>;
1267 interconnect-names = "qup-core", "qup-config";
1272 compatible = "qcom,geni-i2c-master-hub";
1274 clock-names = "se", "core";
1277 pinctrl-names = "default";
1278 pinctrl-0 = <&hub_i2c8_data_clk>;
1280 #address-cells = <1>;
1281 #size-cells = <0>;
1284 interconnect-names = "qup-core", "qup-config";
1289 compatible = "qcom,geni-i2c-master-hub";
1291 clock-names = "se", "core";
1294 pinctrl-names = "default";
1295 pinctrl-0 = <&hub_i2c9_data_clk>;
1297 #address-cells = <1>;
1298 #size-cells = <0>;
1301 interconnect-names = "qup-core", "qup-config";
1306 gpi_dma1: dma-controller@a00000 {
1307 compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma";
1308 #dma-cells = <3>;
1322 dma-channels = <12>;
1323 dma-channel-mask = <0x1e>;
1329 compatible = "qcom,geni-se-qup";
1332 clock-names = "m-ahb", "s-ahb";
1337 interconnect-names = "qup-core";
1338 #address-cells = <2>;
1339 #size-cells = <2>;
1343 compatible = "qcom,geni-i2c";
1345 clock-names = "se";
1347 pinctrl-names = "default";
1348 pinctrl-0 = <&qup_i2c0_data_clk>;
1350 #address-cells = <1>;
1351 #size-cells = <0>;
1355 interconnect-names = "qup-core", "qup-config", "qup-memory";
1358 dma-names = "tx", "rx";
1363 compatible = "qcom,geni-spi";
1365 clock-names = "se";
1368 pinctrl-names = "default";
1369 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1373 interconnect-names = "qup-core", "qup-config", "qup-memory";
1376 dma-names = "tx", "rx";
1377 #address-cells = <1>;
1378 #size-cells = <0>;
1383 compatible = "qcom,geni-i2c";
1385 clock-names = "se";
1387 pinctrl-names = "default";
1388 pinctrl-0 = <&qup_i2c1_data_clk>;
1390 #address-cells = <1>;
1391 #size-cells = <0>;
1395 interconnect-names = "qup-core", "qup-config", "qup-memory";
1398 dma-names = "tx", "rx";
1403 compatible = "qcom,geni-spi";
1405 clock-names = "se";
1408 pinctrl-names = "default";
1409 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1413 interconnect-names = "qup-core", "qup-config", "qup-memory";
1416 dma-names = "tx", "rx";
1417 #address-cells = <1>;
1418 #size-cells = <0>;
1423 compatible = "qcom,geni-i2c";
1425 clock-names = "se";
1427 pinctrl-names = "default";
1428 pinctrl-0 = <&qup_i2c2_data_clk>;
1430 #address-cells = <1>;
1431 #size-cells = <0>;
1435 interconnect-names = "qup-core", "qup-config", "qup-memory";
1438 dma-names = "tx", "rx";
1443 compatible = "qcom,geni-spi";
1445 clock-names = "se";
1448 pinctrl-names = "default";
1449 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1453 interconnect-names = "qup-core", "qup-config", "qup-memory";
1456 dma-names = "tx", "rx";
1457 #address-cells = <1>;
1458 #size-cells = <0>;
1463 compatible = "qcom,geni-i2c";
1465 clock-names = "se";
1467 pinctrl-names = "default";
1468 pinctrl-0 = <&qup_i2c3_data_clk>;
1470 #address-cells = <1>;
1471 #size-cells = <0>;
1475 interconnect-names = "qup-core", "qup-config", "qup-memory";
1478 dma-names = "tx", "rx";
1483 compatible = "qcom,geni-spi";
1485 clock-names = "se";
1488 pinctrl-names = "default";
1489 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1493 interconnect-names = "qup-core", "qup-config", "qup-memory";
1496 dma-names = "tx", "rx";
1497 #address-cells = <1>;
1498 #size-cells = <0>;
1503 compatible = "qcom,geni-i2c";
1505 clock-names = "se";
1507 pinctrl-names = "default";
1508 pinctrl-0 = <&qup_i2c4_data_clk>;
1510 #address-cells = <1>;
1511 #size-cells = <0>;
1515 interconnect-names = "qup-core", "qup-config", "qup-memory";
1518 dma-names = "tx", "rx";
1523 compatible = "qcom,geni-spi";
1525 clock-names = "se";
1528 pinctrl-names = "default";
1529 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1533 interconnect-names = "qup-core", "qup-config", "qup-memory";
1536 dma-names = "tx", "rx";
1537 #address-cells = <1>;
1538 #size-cells = <0>;
1543 compatible = "qcom,geni-i2c";
1545 clock-names = "se";
1547 pinctrl-names = "default";
1548 pinctrl-0 = <&qup_i2c5_data_clk>;
1553 interconnect-names = "qup-core", "qup-config", "qup-memory";
1556 dma-names = "tx", "rx";
1557 #address-cells = <1>;
1558 #size-cells = <0>;
1563 compatible = "qcom,geni-spi";
1565 clock-names = "se";
1568 pinctrl-names = "default";
1569 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1573 interconnect-names = "qup-core", "qup-config", "qup-memory";
1576 dma-names = "tx", "rx";
1577 #address-cells = <1>;
1578 #size-cells = <0>;
1583 compatible = "qcom,geni-i2c";
1585 clock-names = "se";
1587 pinctrl-names = "default";
1588 pinctrl-0 = <&qup_i2c6_data_clk>;
1593 interconnect-names = "qup-core", "qup-config", "qup-memory";
1596 dma-names = "tx", "rx";
1597 #address-cells = <1>;
1598 #size-cells = <0>;
1603 compatible = "qcom,geni-spi";
1605 clock-names = "se";
1608 pinctrl-names = "default";
1609 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1613 interconnect-names = "qup-core", "qup-config", "qup-memory";
1616 dma-names = "tx", "rx";
1617 #address-cells = <1>;
1618 #size-cells = <0>;
1623 compatible = "qcom,geni-debug-uart";
1625 clock-names = "se";
1627 pinctrl-names = "default";
1628 pinctrl-0 = <&qup_uart7_default>;
1630 interconnect-names = "qup-core", "qup-config";
1638 compatible = "qcom,sm8550-cnoc-main";
1640 #interconnect-cells = <2>;
1641 qcom,bcm-voters = <&apps_bcm_voter>;
1645 compatible = "qcom,sm8550-config-noc";
1647 #interconnect-cells = <2>;
1648 qcom,bcm-voters = <&apps_bcm_voter>;
1652 compatible = "qcom,sm8550-system-noc";
1654 #interconnect-cells = <2>;
1655 qcom,bcm-voters = <&apps_bcm_voter>;
1659 compatible = "qcom,sm8550-pcie-anoc";
1661 #interconnect-cells = <2>;
1664 qcom,bcm-voters = <&apps_bcm_voter>;
1668 compatible = "qcom,sm8550-aggre1-noc";
1670 #interconnect-cells = <2>;
1673 qcom,bcm-voters = <&apps_bcm_voter>;
1677 compatible = "qcom,sm8550-aggre2-noc";
1679 #interconnect-cells = <2>;
1681 qcom,bcm-voters = <&apps_bcm_voter>;
1685 compatible = "qcom,sm8550-mmss-noc";
1687 #interconnect-cells = <2>;
1688 qcom,bcm-voters = <&apps_bcm_voter>;
1692 compatible = "qcom,sm8550-trng", "qcom,trng";
1698 compatible = "qcom,pcie-sm8550";
1704 reg-names = "parf", "dbi", "elbi", "atu", "config";
1705 #address-cells = <3>;
1706 #size-cells = <2>;
1709 bus-range = <0x00 0xff>;
1711 dma-coherent;
1713 linux,pci-domain = <0>;
1714 num-lanes = <2>;
1717 interrupt-names = "msi";
1719 #interrupt-cells = <1>;
1720 interrupt-map-mask = <0 0 0 0x7>;
1721 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1733 clock-names = "aux",
1743 interconnect-names = "pcie-mem", "cpu-pcie";
1745 iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
1749 reset-names = "pci";
1751 power-domains = <&gcc PCIE_0_GDSC>;
1754 phy-names = "pciephy";
1760 compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy";
1768 clock-names = "aux", "cfg_ahb", "ref", "rchng",
1772 reset-names = "phy";
1774 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
1775 assigned-clock-rates = <100000000>;
1777 power-domains = <&gcc PCIE_0_PHY_GDSC>;
1779 #clock-cells = <0>;
1780 clock-output-names = "pcie0_pipe_clk";
1782 #phy-cells = <0>;
1789 compatible = "qcom,pcie-sm8550";
1795 reg-names = "parf", "dbi", "elbi", "atu", "config";
1796 #address-cells = <3>;
1797 #size-cells = <2>;
1800 bus-range = <0x00 0xff>;
1802 dma-coherent;
1804 linux,pci-domain = <1>;
1805 num-lanes = <2>;
1808 interrupt-names = "msi";
1810 #interrupt-cells = <1>;
1811 interrupt-map-mask = <0 0 0 0x7>;
1812 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1825 clock-names = "aux",
1834 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
1835 assigned-clock-rates = <19200000>;
1839 interconnect-names = "pcie-mem", "cpu-pcie";
1841 iommu-map = <0x0 &apps_smmu 0x1480 0x1>,
1846 reset-names = "pci", "link_down";
1848 power-domains = <&gcc PCIE_1_GDSC>;
1851 phy-names = "pciephy";
1857 compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy";
1865 clock-names = "aux", "cfg_ahb", "ref", "rchng",
1870 reset-names = "phy", "phy_nocsr";
1872 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
1873 assigned-clock-rates = <100000000>;
1875 power-domains = <&gcc PCIE_1_PHY_GDSC>;
1877 #clock-cells = <0>;
1878 clock-output-names = "pcie1_pipe_clk";
1880 #phy-cells = <0>;
1885 cryptobam: dma-controller@1dc4000 {
1886 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
1889 #dma-cells = <1>;
1891 qcom,controlled-remotely;
1897 compatible = "qcom,sm8550-qce", "qcom,sm8150-qce", "qcom,qce";
1900 dma-names = "rx", "tx";
1904 interconnect-names = "memory";
1908 compatible = "qcom,sm8550-qmp-ufs-phy";
1912 clock-names = "ref", "ref_aux";
1914 power-domains = <&gcc UFS_MEM_PHY_GDSC>;
1917 reset-names = "ufsphy";
1919 #clock-cells = <1>;
1920 #phy-cells = <0>;
1926 compatible = "qcom,sm8550-ufshc", "qcom,ufshc",
1927 "jedec,ufs-2.0";
1931 phy-names = "ufsphy";
1932 lanes-per-direction = <2>;
1933 #reset-cells = <1>;
1935 reset-names = "rst";
1937 power-domains = <&gcc UFS_PHY_GDSC>;
1938 required-opps = <&rpmhpd_opp_nom>;
1941 dma-coherent;
1946 interconnect-names = "ufs-ddr", "cpu-ufs";
1947 clock-names = "core_clk",
1963 freq-table-hz =
1978 compatible = "qcom,sm8550-inline-crypto-engine",
1979 "qcom,inline-crypto-engine";
1985 compatible = "qcom,tcsr-mutex";
1987 #hwlock-cells = <1>;
1990 tcsr: clock-controller@1fc0000 {
1991 compatible = "qcom,sm8550-tcsr", "syscon";
1994 #clock-cells = <1>;
1995 #reset-cells = <1>;
1999 compatible = "qcom,adreno-43050a01", "qcom,adreno";
2003 reg-names = "kgsl_3d0_reg_memory",
2012 operating-points-v2 = <&gpu_opp_table>;
2018 zap-shader {
2019 memory-region = <&gpu_micro_code_mem>;
2023 gpu_opp_table: opp-table {
2024 compatible = "operating-points-v2";
2026 opp-680000000 {
2027 opp-hz = /bits/ 64 <680000000>;
2028 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2031 opp-615000000 {
2032 opp-hz = /bits/ 64 <615000000>;
2033 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
2036 opp-550000000 {
2037 opp-hz = /bits/ 64 <550000000>;
2038 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2041 opp-475000000 {
2042 opp-hz = /bits/ 64 <475000000>;
2043 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
2046 opp-401000000 {
2047 opp-hz = /bits/ 64 <401000000>;
2048 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2051 opp-348000000 {
2052 opp-hz = /bits/ 64 <348000000>;
2053 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
2056 opp-295000000 {
2057 opp-hz = /bits/ 64 <295000000>;
2058 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
2061 opp-220000000 {
2062 opp-hz = /bits/ 64 <220000000>;
2063 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
2069 compatible = "qcom,adreno-gmu-740.1", "qcom,adreno-gmu";
2073 reg-names = "gmu", "rscc", "gmu_pdc";
2077 interrupt-names = "hfi", "gmu";
2086 clock-names = "ahb",
2094 power-domains = <&gpucc GPU_CC_CX_GDSC>,
2096 power-domain-names = "cx",
2103 operating-points-v2 = <&gmu_opp_table>;
2105 gmu_opp_table: opp-table {
2106 compatible = "operating-points-v2";
2108 opp-500000000 {
2109 opp-hz = /bits/ 64 <500000000>;
2110 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2113 opp-200000000 {
2114 opp-hz = /bits/ 64 <200000000>;
2115 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2120 gpucc: clock-controller@3d90000 {
2121 compatible = "qcom,sm8550-gpucc";
2126 #clock-cells = <1>;
2127 #reset-cells = <1>;
2128 #power-domain-cells = <1>;
2132 compatible = "qcom,sm8550-smmu-500", "qcom,adreno-smmu",
2133 "qcom,smmu-500", "arm,mmu-500";
2135 #iommu-cells = <2>;
2136 #global-interrupts = <1>;
2167 clock-names = "hlos",
2171 power-domains = <&gpucc GPU_CC_CX_GDSC>;
2172 dma-coherent;
2176 compatible = "qcom,sm8550-ipa";
2183 reg-names = "ipa-reg",
2184 "ipa-shared",
2187 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>,
2191 interrupt-names = "ipa",
2193 "ipa-clock-query",
2194 "ipa-setup-ready";
2197 clock-names = "core";
2201 interconnect-names = "memory",
2206 qcom,smem-states = <&ipa_smp2p_out 0>,
2208 qcom,smem-state-names = "ipa-clock-enabled-valid",
2209 "ipa-clock-enabled";
2215 compatible = "qcom,sm8550-mpss-pas";
2218 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
2224 interrupt-names = "wdog", "fatal", "ready", "handover",
2225 "stop-ack", "shutdown-ack";
2228 clock-names = "xo";
2230 power-domains = <&rpmhpd RPMHPD_CX>,
2231 <&rpmhpd RPMHPD_MSS>;
2232 power-domain-names = "cx", "mss";
2236 memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, <&mpss_dsm_mem>;
2240 qcom,smem-states = <&smp2p_modem_out 0>;
2241 qcom,smem-state-names = "stop";
2245 glink-edge {
2246 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2252 qcom,remote-pid = <1>;
2257 compatible = "qcom,sm8550-lpass-wsa-macro";
2263 clock-names = "mclk", "macro", "dcodec", "fsgen";
2265 #clock-cells = <0>;
2266 clock-output-names = "wsa2-mclk";
2267 #sound-dai-cells = <1>;
2271 compatible = "qcom,soundwire-v2.0.0";
2275 clock-names = "iface";
2278 pinctrl-0 = <&wsa2_swr_active>;
2279 pinctrl-names = "default";
2281 qcom,din-ports = <4>;
2282 qcom,dout-ports = <9>;
2284 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>;
2285 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
2286 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2287 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2288 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2289 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>;
2290 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>;
2291 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2292 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2294 #address-cells = <2>;
2295 #size-cells = <0>;
2296 #sound-dai-cells = <1>;
2301 compatible = "qcom,sm8550-lpass-rx-macro";
2307 clock-names = "mclk", "macro", "dcodec", "fsgen";
2309 #clock-cells = <0>;
2310 clock-output-names = "mclk";
2311 #sound-dai-cells = <1>;
2315 compatible = "qcom,soundwire-v2.0.0";
2319 clock-names = "iface";
2322 pinctrl-0 = <&rx_swr_active>;
2323 pinctrl-names = "default";
2325 qcom,din-ports = <1>;
2326 qcom,dout-ports = <11>;
2328 qcom,ports-sinterval = /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xff 0xff 0xff 0xff 0xff 0xff>;
2329 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
2330 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
2331 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff>;
2332 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff>;
2333 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff 0xff 0xff 0xff 0xff 0xff>;
2334 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
2335 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
2336 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
2338 #address-cells = <2>;
2339 #size-cells = <0>;
2340 #sound-dai-cells = <1>;
2345 compatible = "qcom,sm8550-lpass-tx-macro";
2351 clock-names = "mclk", "macro", "dcodec", "fsgen";
2353 #clock-cells = <0>;
2354 clock-output-names = "mclk";
2355 #sound-dai-cells = <1>;
2359 compatible = "qcom,sm8550-lpass-wsa-macro";
2365 clock-names = "mclk", "macro", "dcodec", "fsgen";
2367 #clock-cells = <0>;
2368 clock-output-names = "mclk";
2369 #sound-dai-cells = <1>;
2373 compatible = "qcom,soundwire-v2.0.0";
2377 clock-names = "iface";
2380 pinctrl-0 = <&wsa_swr_active>;
2381 pinctrl-names = "default";
2383 qcom,din-ports = <4>;
2384 qcom,dout-ports = <9>;
2386 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>;
2387 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
2388 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2389 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2390 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2391 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>;
2392 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>;
2393 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2394 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2396 #address-cells = <2>;
2397 #size-cells = <0>;
2398 #sound-dai-cells = <1>;
2403 compatible = "qcom,soundwire-v2.0.0";
2407 interrupt-names = "core", "wakeup";
2409 clock-names = "iface";
2412 pinctrl-0 = <&tx_swr_active>;
2413 pinctrl-names = "default";
2415 qcom,din-ports = <4>;
2416 qcom,dout-ports = <0>;
2417 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
2418 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>;
2419 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
2420 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
2421 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
2422 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
2423 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
2424 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
2425 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>;
2427 #address-cells = <2>;
2428 #size-cells = <0>;
2429 #sound-dai-cells = <1>;
2434 compatible = "qcom,sm8550-lpass-va-macro";
2439 clock-names = "mclk", "macro", "dcodec";
2441 #clock-cells = <0>;
2442 clock-output-names = "fsgen";
2443 #sound-dai-cells = <1>;
2447 compatible = "qcom,sm8550-lpass-lpi-pinctrl";
2450 gpio-controller;
2451 #gpio-cells = <2>;
2452 gpio-ranges = <&lpass_tlmm 0 0 23>;
2456 clock-names = "core", "audio";
2458 tx_swr_active: tx-swr-active-state {
2459 clk-pins {
2462 drive-strength = <2>;
2463 slew-rate = <1>;
2464 bias-disable;
2467 data-pins {
2470 drive-strength = <2>;
2471 slew-rate = <1>;
2472 bias-bus-hold;
2476 rx_swr_active: rx-swr-active-state {
2477 clk-pins {
2480 drive-strength = <2>;
2481 slew-rate = <1>;
2482 bias-disable;
2485 data-pins {
2488 drive-strength = <2>;
2489 slew-rate = <1>;
2490 bias-bus-hold;
2494 dmic01_default: dmic01-default-state {
2495 clk-pins {
2498 drive-strength = <8>;
2499 output-high;
2502 data-pins {
2505 drive-strength = <8>;
2506 input-enable;
2510 dmic02_default: dmic02-default-state {
2511 clk-pins {
2514 drive-strength = <8>;
2515 output-high;
2518 data-pins {
2521 drive-strength = <8>;
2522 input-enable;
2526 wsa_swr_active: wsa-swr-active-state {
2527 clk-pins {
2530 drive-strength = <2>;
2531 slew-rate = <1>;
2532 bias-disable;
2535 data-pins {
2538 drive-strength = <2>;
2539 slew-rate = <1>;
2540 bias-bus-hold;
2544 wsa2_swr_active: wsa2-swr-active-state {
2545 clk-pins {
2548 drive-strength = <2>;
2549 slew-rate = <1>;
2550 bias-disable;
2553 data-pins {
2556 drive-strength = <2>;
2557 slew-rate = <1>;
2558 bias-bus-hold;
2564 compatible = "qcom,sm8550-lpass-lpiaon-noc";
2566 #interconnect-cells = <2>;
2567 qcom,bcm-voters = <&apps_bcm_voter>;
2571 compatible = "qcom,sm8550-lpass-lpicx-noc";
2573 #interconnect-cells = <2>;
2574 qcom,bcm-voters = <&apps_bcm_voter>;
2578 compatible = "qcom,sm8550-lpass-ag-noc";
2580 #interconnect-cells = <2>;
2581 qcom,bcm-voters = <&apps_bcm_voter>;
2585 compatible = "qcom,sm8550-sdhci", "qcom,sdhci-msm-v5";
2590 interrupt-names = "hc_irq", "pwr_irq";
2595 clock-names = "iface", "core", "xo";
2597 qcom,dll-config = <0x0007642c>;
2598 qcom,ddr-config = <0x80040868>;
2599 power-domains = <&rpmhpd RPMHPD_CX>;
2600 operating-points-v2 = <&sdhc2_opp_table>;
2604 interconnect-names = "sdhc-ddr", "cpu-sdhc";
2605 bus-width = <4>;
2606 dma-coherent;
2608 /* Forbid SDR104/SDR50 - broken hw! */
2609 sdhci-caps-mask = <0x3 0>;
2613 sdhc2_opp_table: opp-table {
2614 compatible = "operating-points-v2";
2616 opp-19200000 {
2617 opp-hz = /bits/ 64 <19200000>;
2618 required-opps = <&rpmhpd_opp_min_svs>;
2621 opp-50000000 {
2622 opp-hz = /bits/ 64 <50000000>;
2623 required-opps = <&rpmhpd_opp_low_svs>;
2626 opp-100000000 {
2627 opp-hz = /bits/ 64 <100000000>;
2628 required-opps = <&rpmhpd_opp_svs>;
2631 opp-202000000 {
2632 opp-hz = /bits/ 64 <202000000>;
2633 required-opps = <&rpmhpd_opp_svs_l1>;
2638 videocc: clock-controller@aaf0000 {
2639 compatible = "qcom,sm8550-videocc";
2643 power-domains = <&rpmhpd RPMHPD_MMCX>;
2644 required-opps = <&rpmhpd_opp_low_svs>;
2645 #clock-cells = <1>;
2646 #reset-cells = <1>;
2647 #power-domain-cells = <1>;
2650 camcc: clock-controller@ade0000 {
2651 compatible = "qcom,sm8550-camcc";
2657 power-domains = <&rpmhpd SM8550_MMCX>;
2658 required-opps = <&rpmhpd_opp_low_svs>;
2659 #clock-cells = <1>;
2660 #reset-cells = <1>;
2661 #power-domain-cells = <1>;
2664 mdss: display-subsystem@ae00000 {
2665 compatible = "qcom,sm8550-mdss";
2667 reg-names = "mdss";
2670 interrupt-controller;
2671 #interrupt-cells = <1>;
2680 power-domains = <&dispcc MDSS_GDSC>;
2684 interconnect-names = "mdp0-mem", "mdp1-mem";
2688 #address-cells = <2>;
2689 #size-cells = <2>;
2694 mdss_mdp: display-controller@ae01000 {
2695 compatible = "qcom,sm8550-dpu";
2698 reg-names = "mdp", "vbif";
2700 interrupt-parent = <&mdss>;
2709 clock-names = "bus",
2716 power-domains = <&rpmhpd RPMHPD_MMCX>;
2718 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2719 assigned-clock-rates = <19200000>;
2721 operating-points-v2 = <&mdp_opp_table>;
2724 #address-cells = <1>;
2725 #size-cells = <0>;
2730 remote-endpoint = <&mdss_dsi0_in>;
2737 remote-endpoint = <&mdss_dsi1_in>;
2744 remote-endpoint = <&mdss_dp0_in>;
2749 mdp_opp_table: opp-table {
2750 compatible = "operating-points-v2";
2752 opp-200000000 {
2753 opp-hz = /bits/ 64 <200000000>;
2754 required-opps = <&rpmhpd_opp_low_svs>;
2757 opp-325000000 {
2758 opp-hz = /bits/ 64 <325000000>;
2759 required-opps = <&rpmhpd_opp_svs>;
2762 opp-375000000 {
2763 opp-hz = /bits/ 64 <375000000>;
2764 required-opps = <&rpmhpd_opp_svs_l1>;
2767 opp-514000000 {
2768 opp-hz = /bits/ 64 <514000000>;
2769 required-opps = <&rpmhpd_opp_nom>;
2774 mdss_dp0: displayport-controller@ae90000 {
2775 compatible = "qcom,sm8550-dp", "qcom,sm8350-dp";
2781 interrupt-parent = <&mdss>;
2788 clock-names = "core_iface",
2794 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
2796 assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
2800 phy-names = "dp";
2802 #sound-dai-cells = <0>;
2804 operating-points-v2 = <&dp_opp_table>;
2805 power-domains = <&rpmhpd RPMHPD_MMCX>;
2810 #address-cells = <1>;
2811 #size-cells = <0>;
2816 remote-endpoint = <&dpu_intf0_out>;
2827 dp_opp_table: opp-table {
2828 compatible = "operating-points-v2";
2830 opp-162000000 {
2831 opp-hz = /bits/ 64 <162000000>;
2832 required-opps = <&rpmhpd_opp_low_svs_d1>;
2835 opp-270000000 {
2836 opp-hz = /bits/ 64 <270000000>;
2837 required-opps = <&rpmhpd_opp_low_svs>;
2840 opp-540000000 {
2841 opp-hz = /bits/ 64 <540000000>;
2842 required-opps = <&rpmhpd_opp_svs_l1>;
2845 opp-810000000 {
2846 opp-hz = /bits/ 64 <810000000>;
2847 required-opps = <&rpmhpd_opp_nom>;
2853 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2855 reg-names = "dsi_ctrl";
2857 interrupt-parent = <&mdss>;
2866 clock-names = "byte",
2873 power-domains = <&rpmhpd RPMHPD_MMCX>;
2875 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
2877 assigned-clock-parents = <&mdss_dsi0_phy 0>,
2880 operating-points-v2 = <&mdss_dsi_opp_table>;
2883 phy-names = "dsi";
2885 #address-cells = <1>;
2886 #size-cells = <0>;
2891 #address-cells = <1>;
2892 #size-cells = <0>;
2897 remote-endpoint = <&dpu_intf1_out>;
2908 mdss_dsi_opp_table: opp-table {
2909 compatible = "operating-points-v2";
2911 opp-187500000 {
2912 opp-hz = /bits/ 64 <187500000>;
2913 required-opps = <&rpmhpd_opp_low_svs>;
2916 opp-300000000 {
2917 opp-hz = /bits/ 64 <300000000>;
2918 required-opps = <&rpmhpd_opp_svs>;
2921 opp-358000000 {
2922 opp-hz = /bits/ 64 <358000000>;
2923 required-opps = <&rpmhpd_opp_svs_l1>;
2929 compatible = "qcom,sm8550-dsi-phy-4nm";
2933 reg-names = "dsi_phy",
2939 clock-names = "iface", "ref";
2941 #clock-cells = <1>;
2942 #phy-cells = <0>;
2948 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2950 reg-names = "dsi_ctrl";
2952 interrupt-parent = <&mdss>;
2961 clock-names = "byte",
2968 power-domains = <&rpmhpd RPMHPD_MMCX>;
2970 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
2972 assigned-clock-parents = <&mdss_dsi1_phy 0>,
2975 operating-points-v2 = <&mdss_dsi_opp_table>;
2978 phy-names = "dsi";
2980 #address-cells = <1>;
2981 #size-cells = <0>;
2986 #address-cells = <1>;
2987 #size-cells = <0>;
2992 remote-endpoint = <&dpu_intf2_out>;
3005 compatible = "qcom,sm8550-dsi-phy-4nm";
3009 reg-names = "dsi_phy",
3015 clock-names = "iface", "ref";
3017 #clock-cells = <1>;
3018 #phy-cells = <0>;
3024 dispcc: clock-controller@af00000 {
3025 compatible = "qcom,sm8550-dispcc";
3043 power-domains = <&rpmhpd RPMHPD_MMCX>;
3044 required-opps = <&rpmhpd_opp_low_svs>;
3045 #clock-cells = <1>;
3046 #reset-cells = <1>;
3047 #power-domain-cells = <1>;
3051 compatible = "qcom,sm8550-snps-eusb2-phy";
3053 #phy-cells = <0>;
3056 clock-names = "ref";
3064 compatible = "qcom,sm8550-qmp-usb3-dp-phy";
3071 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
3073 power-domains = <&gcc USB3_PHY_GDSC>;
3077 reset-names = "phy", "common";
3079 #clock-cells = <1>;
3080 #phy-cells = <1>;
3085 #address-cells = <1>;
3086 #size-cells = <0>;
3112 compatible = "qcom,sm8550-dwc3", "qcom,dwc3";
3114 #address-cells = <2>;
3115 #size-cells = <2>;
3124 clock-names = "cfg_noc",
3131 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3133 assigned-clock-rates = <19200000>, <200000000>;
3135 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
3139 interrupt-names = "hs_phy_irq",
3144 power-domains = <&gcc USB30_PRIM_GDSC>;
3145 required-opps = <&rpmhpd_opp_nom>;
3151 interconnect-names = "usb-ddr", "apps-usb";
3165 phy-names = "usb2-phy", "usb3-phy";
3168 #address-cells = <1>;
3169 #size-cells = <0>;
3188 pdc: interrupt-controller@b220000 {
3189 compatible = "qcom,sm8550-pdc", "qcom,pdc";
3191 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
3194 #interrupt-cells = <2>;
3195 interrupt-parent = <&intc>;
3196 interrupt-controller;
3199 tsens0: thermal-sensor@c271000 {
3200 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2";
3206 interrupt-names = "uplow", "critical";
3207 #thermal-sensor-cells = <1>;
3210 tsens1: thermal-sensor@c272000 {
3211 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2";
3217 interrupt-names = "uplow", "critical";
3218 #thermal-sensor-cells = <1>;
3221 tsens2: thermal-sensor@c273000 {
3222 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2";
3228 interrupt-names = "uplow", "critical";
3229 #thermal-sensor-cells = <1>;
3232 aoss_qmp: power-management@c300000 {
3233 compatible = "qcom,sm8550-aoss-qmp", "qcom,aoss-qmp";
3235 interrupt-parent = <&ipcc>;
3236 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
3240 #clock-cells = <0>;
3244 compatible = "qcom,rpmh-stats";
3249 compatible = "qcom,spmi-pmic-arb";
3255 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3256 interrupt-names = "periph_irq";
3257 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3260 qcom,bus-id = <0>;
3261 #address-cells = <2>;
3262 #size-cells = <0>;
3263 interrupt-controller;
3264 #interrupt-cells = <4>;
3268 compatible = "qcom,sm8550-tlmm";
3271 gpio-controller;
3272 #gpio-cells = <2>;
3273 interrupt-controller;
3274 #interrupt-cells = <2>;
3275 gpio-ranges = <&tlmm 0 0 211>;
3276 wakeup-parent = <&pdc>;
3278 hub_i2c0_data_clk: hub-i2c0-data-clk-state {
3282 drive-strength = <2>;
3283 bias-pull-up;
3286 hub_i2c1_data_clk: hub-i2c1-data-clk-state {
3290 drive-strength = <2>;
3291 bias-pull-up;
3294 hub_i2c2_data_clk: hub-i2c2-data-clk-state {
3298 drive-strength = <2>;
3299 bias-pull-up;
3302 hub_i2c3_data_clk: hub-i2c3-data-clk-state {
3306 drive-strength = <2>;
3307 bias-pull-up;
3310 hub_i2c4_data_clk: hub-i2c4-data-clk-state {
3314 drive-strength = <2>;
3315 bias-pull-up;
3318 hub_i2c5_data_clk: hub-i2c5-data-clk-state {
3322 drive-strength = <2>;
3323 bias-pull-up;
3326 hub_i2c6_data_clk: hub-i2c6-data-clk-state {
3330 drive-strength = <2>;
3331 bias-pull-up;
3334 hub_i2c7_data_clk: hub-i2c7-data-clk-state {
3338 drive-strength = <2>;
3339 bias-pull-up;
3342 hub_i2c8_data_clk: hub-i2c8-data-clk-state {
3346 drive-strength = <2>;
3347 bias-pull-up;
3350 hub_i2c9_data_clk: hub-i2c9-data-clk-state {
3354 drive-strength = <2>;
3355 bias-pull-up;
3358 pcie0_default_state: pcie0-default-state {
3359 perst-pins {
3362 drive-strength = <2>;
3363 bias-pull-down;
3366 clkreq-pins {
3369 drive-strength = <2>;
3370 bias-pull-up;
3373 wake-pins {
3376 drive-strength = <2>;
3377 bias-pull-up;
3381 pcie1_default_state: pcie1-default-state {
3382 perst-pins {
3385 drive-strength = <2>;
3386 bias-pull-down;
3389 clkreq-pins {
3392 drive-strength = <2>;
3393 bias-pull-up;
3396 wake-pins {
3399 drive-strength = <2>;
3400 bias-pull-up;
3404 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
3408 drive-strength = <2>;
3409 bias-pull-up = <2200>;
3412 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
3416 drive-strength = <2>;
3417 bias-pull-up = <2200>;
3420 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
3424 drive-strength = <2>;
3425 bias-pull-up = <2200>;
3428 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
3432 drive-strength = <2>;
3433 bias-pull-up = <2200>;
3436 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
3440 drive-strength = <2>;
3441 bias-pull-up = <2200>;
3444 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
3448 drive-strength = <2>;
3449 bias-pull-up = <2200>;
3452 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
3456 drive-strength = <2>;
3457 bias-pull-up = <2200>;
3460 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
3461 scl-pins {
3464 drive-strength = <2>;
3465 bias-pull-up = <2200>;
3468 sda-pins {
3471 drive-strength = <2>;
3472 bias-pull-up = <2200>;
3476 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
3480 drive-strength = <2>;
3481 bias-pull-up = <2200>;
3484 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
3488 drive-strength = <2>;
3489 bias-pull-up = <2200>;
3492 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
3496 drive-strength = <2>;
3497 bias-pull-up = <2200>;
3500 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
3504 drive-strength = <2>;
3505 bias-pull-up = <2200>;
3508 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
3512 drive-strength = <2>;
3513 bias-pull-up = <2200>;
3516 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
3520 drive-strength = <2>;
3521 bias-pull-up = <2200>;
3524 qup_spi0_cs: qup-spi0-cs-state {
3527 drive-strength = <6>;
3528 bias-disable;
3531 qup_spi0_data_clk: qup-spi0-data-clk-state {
3535 drive-strength = <6>;
3536 bias-disable;
3539 qup_spi1_cs: qup-spi1-cs-state {
3542 drive-strength = <6>;
3543 bias-disable;
3546 qup_spi1_data_clk: qup-spi1-data-clk-state {
3550 drive-strength = <6>;
3551 bias-disable;
3554 qup_spi2_cs: qup-spi2-cs-state {
3557 drive-strength = <6>;
3558 bias-disable;
3561 qup_spi2_data_clk: qup-spi2-data-clk-state {
3565 drive-strength = <6>;
3566 bias-disable;
3569 qup_spi3_cs: qup-spi3-cs-state {
3572 drive-strength = <6>;
3573 bias-disable;
3576 qup_spi3_data_clk: qup-spi3-data-clk-state {
3580 drive-strength = <6>;
3581 bias-disable;
3584 qup_spi4_cs: qup-spi4-cs-state {
3587 drive-strength = <6>;
3588 bias-disable;
3591 qup_spi4_data_clk: qup-spi4-data-clk-state {
3595 drive-strength = <6>;
3596 bias-disable;
3599 qup_spi5_cs: qup-spi5-cs-state {
3602 drive-strength = <6>;
3603 bias-disable;
3606 qup_spi5_data_clk: qup-spi5-data-clk-state {
3610 drive-strength = <6>;
3611 bias-disable;
3614 qup_spi6_cs: qup-spi6-cs-state {
3617 drive-strength = <6>;
3618 bias-disable;
3621 qup_spi6_data_clk: qup-spi6-data-clk-state {
3625 drive-strength = <6>;
3626 bias-disable;
3629 qup_spi8_cs: qup-spi8-cs-state {
3632 drive-strength = <6>;
3633 bias-disable;
3636 qup_spi8_data_clk: qup-spi8-data-clk-state {
3640 drive-strength = <6>;
3641 bias-disable;
3644 qup_spi9_cs: qup-spi9-cs-state {
3647 drive-strength = <6>;
3648 bias-disable;
3651 qup_spi9_data_clk: qup-spi9-data-clk-state {
3655 drive-strength = <6>;
3656 bias-disable;
3659 qup_spi10_cs: qup-spi10-cs-state {
3662 drive-strength = <6>;
3663 bias-disable;
3666 qup_spi10_data_clk: qup-spi10-data-clk-state {
3670 drive-strength = <6>;
3671 bias-disable;
3674 qup_spi11_cs: qup-spi11-cs-state {
3677 drive-strength = <6>;
3678 bias-disable;
3681 qup_spi11_data_clk: qup-spi11-data-clk-state {
3685 drive-strength = <6>;
3686 bias-disable;
3689 qup_spi12_cs: qup-spi12-cs-state {
3692 drive-strength = <6>;
3693 bias-disable;
3696 qup_spi12_data_clk: qup-spi12-data-clk-state {
3700 drive-strength = <6>;
3701 bias-disable;
3704 qup_spi13_cs: qup-spi13-cs-state {
3707 drive-strength = <6>;
3708 bias-disable;
3711 qup_spi13_data_clk: qup-spi13-data-clk-state {
3715 drive-strength = <6>;
3716 bias-disable;
3719 qup_spi15_cs: qup-spi15-cs-state {
3722 drive-strength = <6>;
3723 bias-disable;
3726 qup_spi15_data_clk: qup-spi15-data-clk-state {
3730 drive-strength = <6>;
3731 bias-disable;
3734 qup_uart7_default: qup-uart7-default-state {
3738 drive-strength = <2>;
3739 bias-disable;
3742 qup_uart14_default: qup-uart14-default-state {
3746 drive-strength = <2>;
3747 bias-pull-up;
3750 qup_uart14_cts_rts: qup-uart14-cts-rts-state {
3754 drive-strength = <2>;
3755 bias-pull-down;
3758 sdc2_sleep: sdc2-sleep-state {
3759 clk-pins {
3761 bias-disable;
3762 drive-strength = <2>;
3765 cmd-pins {
3767 bias-pull-up;
3768 drive-strength = <2>;
3771 data-pins {
3773 bias-pull-up;
3774 drive-strength = <2>;
3778 sdc2_default: sdc2-default-state {
3779 clk-pins {
3781 bias-disable;
3782 drive-strength = <16>;
3785 cmd-pins {
3787 bias-pull-up;
3788 drive-strength = <10>;
3791 data-pins {
3793 bias-pull-up;
3794 drive-strength = <10>;
3800 compatible = "qcom,sm8550-smmu-500", "qcom,smmu-500", "arm,mmu-500";
3802 #iommu-cells = <2>;
3803 #global-interrupts = <1>;
3903 intc: interrupt-controller@17100000 {
3904 compatible = "arm,gic-v3";
3908 #interrupt-cells = <3>;
3909 interrupt-controller;
3910 #redistributor-regions = <1>;
3911 redistributor-stride = <0 0x40000>;
3913 #address-cells = <2>;
3914 #size-cells = <2>;
3916 gic_its: msi-controller@17140000 {
3917 compatible = "arm,gic-v3-its";
3919 msi-controller;
3920 #msi-cells = <1>;
3925 compatible = "arm,armv7-timer-mem";
3928 #address-cells = <1>;
3929 #size-cells = <1>;
3934 frame-number = <0>;
3941 frame-number = <1>;
3948 frame-number = <2>;
3955 frame-number = <3>;
3962 frame-number = <4>;
3969 frame-number = <5>;
3976 frame-number = <6>;
3984 compatible = "qcom,rpmh-rsc";
3989 reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
3993 qcom,tcs-offset = <0xd00>;
3994 qcom,drv-id = <2>;
3995 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
3997 power-domains = <&CLUSTER_PD>;
3999 apps_bcm_voter: bcm-voter {
4000 compatible = "qcom,bcm-voter";
4003 rpmhcc: clock-controller {
4004 compatible = "qcom,sm8550-rpmh-clk";
4005 #clock-cells = <1>;
4006 clock-names = "xo";
4010 rpmhpd: power-controller {
4011 compatible = "qcom,sm8550-rpmhpd";
4012 #power-domain-cells = <1>;
4013 operating-points-v2 = <&rpmhpd_opp_table>;
4015 rpmhpd_opp_table: opp-table {
4016 compatible = "operating-points-v2";
4018 rpmhpd_opp_ret: opp-16 {
4019 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4022 rpmhpd_opp_min_svs: opp-48 {
4023 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4026 rpmhpd_opp_low_svs_d2: opp-52 {
4027 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
4030 rpmhpd_opp_low_svs_d1: opp-56 {
4031 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
4034 rpmhpd_opp_low_svs_d0: opp-60 {
4035 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
4038 rpmhpd_opp_low_svs: opp-64 {
4039 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4042 rpmhpd_opp_low_svs_l1: opp-80 {
4043 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
4046 rpmhpd_opp_svs: opp-128 {
4047 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4050 rpmhpd_opp_svs_l0: opp-144 {
4051 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
4054 rpmhpd_opp_svs_l1: opp-192 {
4055 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4058 rpmhpd_opp_nom: opp-256 {
4059 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4062 rpmhpd_opp_nom_l1: opp-320 {
4063 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4066 rpmhpd_opp_nom_l2: opp-336 {
4067 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4070 rpmhpd_opp_turbo: opp-384 {
4071 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4074 rpmhpd_opp_turbo_l1: opp-416 {
4075 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4082 compatible = "qcom,sm8550-cpufreq-epss", "qcom,cpufreq-epss";
4086 reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
4088 clock-names = "xo", "alternate";
4092 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
4093 #freq-domain-cells = <1>;
4094 #clock-cells = <1>;
4098 compatible = "qcom,sm8550-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
4103 operating-points-v2 = <&llcc_bwmon_opp_table>;
4105 llcc_bwmon_opp_table: opp-table {
4106 compatible = "operating-points-v2";
4108 opp-0 {
4109 opp-peak-kBps = <2086000>;
4112 opp-1 {
4113 opp-peak-kBps = <2929000>;
4116 opp-2 {
4117 opp-peak-kBps = <5931000>;
4120 opp-3 {
4121 opp-peak-kBps = <6515000>;
4124 opp-4 {
4125 opp-peak-kBps = <7980000>;
4128 opp-5 {
4129 opp-peak-kBps = <10437000>;
4132 opp-6 {
4133 opp-peak-kBps = <12157000>;
4136 opp-7 {
4137 opp-peak-kBps = <14060000>;
4140 opp-8 {
4141 opp-peak-kBps = <16113000>;
4147 compatible = "qcom,sm8550-cpu-bwmon", "qcom,sdm845-bwmon";
4152 operating-points-v2 = <&cpu_bwmon_opp_table>;
4154 cpu_bwmon_opp_table: opp-table {
4155 compatible = "operating-points-v2";
4157 opp-0 {
4158 opp-peak-kBps = <4577000>;
4161 opp-1 {
4162 opp-peak-kBps = <7110000>;
4165 opp-2 {
4166 opp-peak-kBps = <9155000>;
4169 opp-3 {
4170 opp-peak-kBps = <12298000>;
4173 opp-4 {
4174 opp-peak-kBps = <14236000>;
4177 opp-5 {
4178 opp-peak-kBps = <16265000>;
4184 compatible = "qcom,sm8550-gem-noc";
4186 #interconnect-cells = <2>;
4187 qcom,bcm-voters = <&apps_bcm_voter>;
4190 system-cache-controller@25000000 {
4191 compatible = "qcom,sm8550-llcc";
4197 reg-names = "llcc0_base",
4206 compatible = "qcom,sm8550-adsp-pas";
4209 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
4214 interrupt-names = "wdog", "fatal", "ready",
4215 "handover", "stop-ack";
4218 clock-names = "xo";
4220 power-domains = <&rpmhpd RPMHPD_LCX>,
4221 <&rpmhpd RPMHPD_LMX>;
4222 power-domain-names = "lcx", "lmx";
4226 memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>;
4230 qcom,smem-states = <&smp2p_adsp_out 0>;
4231 qcom,smem-state-names = "stop";
4235 remoteproc_adsp_glink: glink-edge {
4236 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
4243 qcom,remote-pid = <2>;
4247 qcom,glink-channels = "fastrpcglink-apps-dsp";
4249 #address-cells = <1>;
4250 #size-cells = <0>;
4252 compute-cb@3 {
4253 compatible = "qcom,fastrpc-compute-cb";
4259 compute-cb@4 {
4260 compatible = "qcom,fastrpc-compute-cb";
4266 compute-cb@5 {
4267 compatible = "qcom,fastrpc-compute-cb";
4273 compute-cb@6 {
4274 compatible = "qcom,fastrpc-compute-cb";
4280 compute-cb@7 {
4281 compatible = "qcom,fastrpc-compute-cb";
4290 qcom,glink-channels = "adsp_apps";
4293 #address-cells = <1>;
4294 #size-cells = <0>;
4299 #sound-dai-cells = <0>;
4300 qcom,protection-domain = "avs/audio",
4304 compatible = "qcom,q6apm-dais";
4310 compatible = "qcom,q6apm-lpass-dais";
4311 #sound-dai-cells = <1>;
4318 qcom,protection-domain = "avs/audio",
4321 q6prmcc: clock-controller {
4322 compatible = "qcom,q6prm-lpass-clocks";
4323 #clock-cells = <2>;
4331 compatible = "qcom,sm8550-nsp-noc";
4333 #interconnect-cells = <2>;
4334 qcom,bcm-voters = <&apps_bcm_voter>;
4338 compatible = "qcom,sm8550-cdsp-pas";
4341 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
4346 interrupt-names = "wdog", "fatal", "ready",
4347 "handover", "stop-ack";
4350 clock-names = "xo";
4352 power-domains = <&rpmhpd RPMHPD_CX>,
4353 <&rpmhpd RPMHPD_MXC>,
4354 <&rpmhpd RPMHPD_NSP>;
4355 power-domain-names = "cx", "mxc", "nsp";
4359 memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>;
4363 qcom,smem-states = <&smp2p_cdsp_out 0>;
4364 qcom,smem-state-names = "stop";
4368 glink-edge {
4369 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
4376 qcom,remote-pid = <5>;
4380 qcom,glink-channels = "fastrpcglink-apps-dsp";
4382 #address-cells = <1>;
4383 #size-cells = <0>;
4385 compute-cb@1 {
4386 compatible = "qcom,fastrpc-compute-cb";
4393 compute-cb@2 {
4394 compatible = "qcom,fastrpc-compute-cb";
4401 compute-cb@3 {
4402 compatible = "qcom,fastrpc-compute-cb";
4409 compute-cb@4 {
4410 compatible = "qcom,fastrpc-compute-cb";
4417 compute-cb@5 {
4418 compatible = "qcom,fastrpc-compute-cb";
4425 compute-cb@6 {
4426 compatible = "qcom,fastrpc-compute-cb";
4433 compute-cb@7 {
4434 compatible = "qcom,fastrpc-compute-cb";
4441 compute-cb@8 {
4442 compatible = "qcom,fastrpc-compute-cb";
4455 thermal-zones {
4456 aoss0-thermal {
4457 polling-delay-passive = <0>;
4458 polling-delay = <0>;
4459 thermal-sensors = <&tsens0 0>;
4462 thermal-engine-config {
4468 reset-mon-config {
4476 cpuss0-thermal {
4477 polling-delay-passive = <0>;
4478 polling-delay = <0>;
4479 thermal-sensors = <&tsens0 1>;
4482 thermal-engine-config {
4488 reset-mon-config {
4496 cpuss1-thermal {
4497 polling-delay-passive = <0>;
4498 polling-delay = <0>;
4499 thermal-sensors = <&tsens0 2>;
4502 thermal-engine-config {
4508 reset-mon-config {
4516 cpuss2-thermal {
4517 polling-delay-passive = <0>;
4518 polling-delay = <0>;
4519 thermal-sensors = <&tsens0 3>;
4522 thermal-engine-config {
4528 reset-mon-config {
4536 cpuss3-thermal {
4537 polling-delay-passive = <0>;
4538 polling-delay = <0>;
4539 thermal-sensors = <&tsens0 4>;
4542 thermal-engine-config {
4548 reset-mon-config {
4556 cpu3-top-thermal {
4557 polling-delay-passive = <0>;
4558 polling-delay = <0>;
4559 thermal-sensors = <&tsens0 5>;
4562 cpu3_top_alert0: trip-point0 {
4568 cpu3_top_alert1: trip-point1 {
4574 cpu3_top_crit: cpu-critical {
4582 cpu3-bottom-thermal {
4583 polling-delay-passive = <0>;
4584 polling-delay = <0>;
4585 thermal-sensors = <&tsens0 6>;
4588 cpu3_bottom_alert0: trip-point0 {
4594 cpu3_bottom_alert1: trip-point1 {
4600 cpu3_bottom_crit: cpu-critical {
4608 cpu4-top-thermal {
4609 polling-delay-passive = <0>;
4610 polling-delay = <0>;
4611 thermal-sensors = <&tsens0 7>;
4614 cpu4_top_alert0: trip-point0 {
4620 cpu4_top_alert1: trip-point1 {
4626 cpu4_top_crit: cpu-critical {
4634 cpu4-bottom-thermal {
4635 polling-delay-passive = <0>;
4636 polling-delay = <0>;
4637 thermal-sensors = <&tsens0 8>;
4640 cpu4_bottom_alert0: trip-point0 {
4646 cpu4_bottom_alert1: trip-point1 {
4652 cpu4_bottom_crit: cpu-critical {
4660 cpu5-top-thermal {
4661 polling-delay-passive = <0>;
4662 polling-delay = <0>;
4663 thermal-sensors = <&tsens0 9>;
4666 cpu5_top_alert0: trip-point0 {
4672 cpu5_top_alert1: trip-point1 {
4678 cpu5_top_crit: cpu-critical {
4686 cpu5-bottom-thermal {
4687 polling-delay-passive = <0>;
4688 polling-delay = <0>;
4689 thermal-sensors = <&tsens0 10>;
4692 cpu5_bottom_alert0: trip-point0 {
4698 cpu5_bottom_alert1: trip-point1 {
4704 cpu5_bottom_crit: cpu-critical {
4712 cpu6-top-thermal {
4713 polling-delay-passive = <0>;
4714 polling-delay = <0>;
4715 thermal-sensors = <&tsens0 11>;
4718 cpu6_top_alert0: trip-point0 {
4724 cpu6_top_alert1: trip-point1 {
4730 cpu6_top_crit: cpu-critical {
4738 cpu6-bottom-thermal {
4739 polling-delay-passive = <0>;
4740 polling-delay = <0>;
4741 thermal-sensors = <&tsens0 12>;
4744 cpu6_bottom_alert0: trip-point0 {
4750 cpu6_bottom_alert1: trip-point1 {
4756 cpu6_bottom_crit: cpu-critical {
4764 cpu7-top-thermal {
4765 polling-delay-passive = <0>;
4766 polling-delay = <0>;
4767 thermal-sensors = <&tsens0 13>;
4770 cpu7_top_alert0: trip-point0 {
4776 cpu7_top_alert1: trip-point1 {
4782 cpu7_top_crit: cpu-critical {
4790 cpu7-middle-thermal {
4791 polling-delay-passive = <0>;
4792 polling-delay = <0>;
4793 thermal-sensors = <&tsens0 14>;
4796 cpu7_middle_alert0: trip-point0 {
4802 cpu7_middle_alert1: trip-point1 {
4808 cpu7_middle_crit: cpu-critical {
4816 cpu7-bottom-thermal {
4817 polling-delay-passive = <0>;
4818 polling-delay = <0>;
4819 thermal-sensors = <&tsens0 15>;
4822 cpu7_bottom_alert0: trip-point0 {
4828 cpu7_bottom_alert1: trip-point1 {
4834 cpu7_bottom_crit: cpu-critical {
4842 aoss1-thermal {
4843 polling-delay-passive = <0>;
4844 polling-delay = <0>;
4845 thermal-sensors = <&tsens1 0>;
4848 thermal-engine-config {
4854 reset-mon-config {
4862 cpu0-thermal {
4863 polling-delay-passive = <0>;
4864 polling-delay = <0>;
4865 thermal-sensors = <&tsens1 1>;
4868 cpu0_alert0: trip-point0 {
4874 cpu0_alert1: trip-point1 {
4880 cpu0_crit: cpu-critical {
4888 cpu1-thermal {
4889 polling-delay-passive = <0>;
4890 polling-delay = <0>;
4891 thermal-sensors = <&tsens1 2>;
4894 cpu1_alert0: trip-point0 {
4900 cpu1_alert1: trip-point1 {
4906 cpu1_crit: cpu-critical {
4914 cpu2-thermal {
4915 polling-delay-passive = <0>;
4916 polling-delay = <0>;
4917 thermal-sensors = <&tsens1 3>;
4920 cpu2_alert0: trip-point0 {
4926 cpu2_alert1: trip-point1 {
4932 cpu2_crit: cpu-critical {
4940 cdsp0-thermal {
4941 polling-delay-passive = <10>;
4942 polling-delay = <0>;
4943 thermal-sensors = <&tsens2 4>;
4946 thermal-engine-config {
4952 thermal-hal-config {
4958 reset-mon-config {
4964 cdsp0_junction_config: junction-config {
4972 cdsp1-thermal {
4973 polling-delay-passive = <10>;
4974 polling-delay = <0>;
4975 thermal-sensors = <&tsens2 5>;
4978 thermal-engine-config {
4984 thermal-hal-config {
4990 reset-mon-config {
4996 cdsp1_junction_config: junction-config {
5004 cdsp2-thermal {
5005 polling-delay-passive = <10>;
5006 polling-delay = <0>;
5007 thermal-sensors = <&tsens2 6>;
5010 thermal-engine-config {
5016 thermal-hal-config {
5022 reset-mon-config {
5028 cdsp2_junction_config: junction-config {
5036 cdsp3-thermal {
5037 polling-delay-passive = <10>;
5038 polling-delay = <0>;
5039 thermal-sensors = <&tsens2 7>;
5042 thermal-engine-config {
5048 thermal-hal-config {
5054 reset-mon-config {
5060 cdsp3_junction_config: junction-config {
5068 video-thermal {
5069 polling-delay-passive = <0>;
5070 polling-delay = <0>;
5071 thermal-sensors = <&tsens1 8>;
5074 thermal-engine-config {
5080 reset-mon-config {
5088 mem-thermal {
5089 polling-delay-passive = <10>;
5090 polling-delay = <0>;
5091 thermal-sensors = <&tsens1 9>;
5094 thermal-engine-config {
5100 ddr_config0: ddr0-config {
5106 reset-mon-config {
5114 modem0-thermal {
5115 polling-delay-passive = <0>;
5116 polling-delay = <0>;
5117 thermal-sensors = <&tsens1 10>;
5120 thermal-engine-config {
5126 mdmss0_config0: mdmss0-config0 {
5132 mdmss0_config1: mdmss0-config1 {
5138 reset-mon-config {
5146 modem1-thermal {
5147 polling-delay-passive = <0>;
5148 polling-delay = <0>;
5149 thermal-sensors = <&tsens1 11>;
5152 thermal-engine-config {
5158 mdmss1_config0: mdmss1-config0 {
5164 mdmss1_config1: mdmss1-config1 {
5170 reset-mon-config {
5178 modem2-thermal {
5179 polling-delay-passive = <0>;
5180 polling-delay = <0>;
5181 thermal-sensors = <&tsens1 12>;
5184 thermal-engine-config {
5190 mdmss2_config0: mdmss2-config0 {
5196 mdmss2_config1: mdmss2-config1 {
5202 reset-mon-config {
5210 modem3-thermal {
5211 polling-delay-passive = <0>;
5212 polling-delay = <0>;
5213 thermal-sensors = <&tsens1 13>;
5216 thermal-engine-config {
5222 mdmss3_config0: mdmss3-config0 {
5228 mdmss3_config1: mdmss3-config1 {
5234 reset-mon-config {
5242 camera0-thermal {
5243 polling-delay-passive = <0>;
5244 polling-delay = <0>;
5245 thermal-sensors = <&tsens1 14>;
5248 thermal-engine-config {
5254 reset-mon-config {
5262 camera1-thermal {
5263 polling-delay-passive = <0>;
5264 polling-delay = <0>;
5265 thermal-sensors = <&tsens1 15>;
5268 thermal-engine-config {
5274 reset-mon-config {
5282 aoss2-thermal {
5283 polling-delay-passive = <0>;
5284 polling-delay = <0>;
5285 thermal-sensors = <&tsens2 0>;
5288 thermal-engine-config {
5294 reset-mon-config {
5302 gpuss-0-thermal {
5303 polling-delay-passive = <10>;
5304 polling-delay = <0>;
5305 thermal-sensors = <&tsens2 1>;
5308 thermal-engine-config {
5314 thermal-hal-config {
5320 reset-mon-config {
5326 gpu0_junction_config: junction-config {
5334 gpuss-1-thermal {
5335 polling-delay-passive = <10>;
5336 polling-delay = <0>;
5337 thermal-sensors = <&tsens2 2>;
5340 thermal-engine-config {
5346 thermal-hal-config {
5352 reset-mon-config {
5358 gpu1_junction_config: junction-config {
5366 gpuss-2-thermal {
5367 polling-delay-passive = <10>;
5368 polling-delay = <0>;
5369 thermal-sensors = <&tsens2 3>;
5372 thermal-engine-config {
5378 thermal-hal-config {
5384 reset-mon-config {
5390 gpu2_junction_config: junction-config {
5398 gpuss-3-thermal {
5399 polling-delay-passive = <10>;
5400 polling-delay = <0>;
5401 thermal-sensors = <&tsens2 4>;
5404 thermal-engine-config {
5410 thermal-hal-config {
5416 reset-mon-config {
5422 gpu3_junction_config: junction-config {
5430 gpuss-4-thermal {
5431 polling-delay-passive = <10>;
5432 polling-delay = <0>;
5433 thermal-sensors = <&tsens2 5>;
5436 thermal-engine-config {
5442 thermal-hal-config {
5448 reset-mon-config {
5454 gpu4_junction_config: junction-config {
5462 gpuss-5-thermal {
5463 polling-delay-passive = <10>;
5464 polling-delay = <0>;
5465 thermal-sensors = <&tsens2 6>;
5468 thermal-engine-config {
5474 thermal-hal-config {
5480 reset-mon-config {
5486 gpu5_junction_config: junction-config {
5494 gpuss-6-thermal {
5495 polling-delay-passive = <10>;
5496 polling-delay = <0>;
5497 thermal-sensors = <&tsens2 7>;
5500 thermal-engine-config {
5506 thermal-hal-config {
5512 reset-mon-config {
5518 gpu6_junction_config: junction-config {
5526 gpuss-7-thermal {
5527 polling-delay-passive = <10>;
5528 polling-delay = <0>;
5529 thermal-sensors = <&tsens2 8>;
5532 thermal-engine-config {
5538 thermal-hal-config {
5544 reset-mon-config {
5550 gpu7_junction_config: junction-config {
5560 compatible = "arm,armv8-timer";