Lines Matching +full:0 +full:x0aaf0000
38 #clock-cells = <0>;
43 #clock-cells = <0>;
47 #clock-cells = <0>;
55 #clock-cells = <0>;
64 #clock-cells = <0>;
70 #size-cells = <0>;
72 CPU0: cpu@0 {
75 reg = <0 0>;
76 clocks = <&cpufreq_hw 0>;
81 qcom,freq-domain = <&cpufreq_hw 0>;
101 reg = <0 0x100>;
102 clocks = <&cpufreq_hw 0>;
107 qcom,freq-domain = <&cpufreq_hw 0>;
122 reg = <0 0x200>;
123 clocks = <&cpufreq_hw 0>;
128 qcom,freq-domain = <&cpufreq_hw 0>;
143 reg = <0 0x300>;
164 reg = <0 0x400>;
185 reg = <0 0x500>;
206 reg = <0 0x600>;
227 reg = <0 0x700>;
284 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
287 arm,psci-suspend-param = <0x40000004>;
294 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
297 arm,psci-suspend-param = <0x40000004>;
304 PRIME_CPU_SLEEP_0: cpu-sleep-2-0 {
307 arm,psci-suspend-param = <0x40000004>;
316 CLUSTER_SLEEP_0: cluster-sleep-0 {
318 arm,psci-suspend-param = <0x41000044>;
326 arm,psci-suspend-param = <0x4100c344>;
337 qcom,dload-mode = <&tcsr 0x19000>;
338 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
342 clk_virt: interconnect-0 {
357 reg = <0 0xa0000000 0 0>;
370 #power-domain-cells = <0>;
376 #power-domain-cells = <0>;
382 #power-domain-cells = <0>;
388 #power-domain-cells = <0>;
394 #power-domain-cells = <0>;
400 #power-domain-cells = <0>;
406 #power-domain-cells = <0>;
412 #power-domain-cells = <0>;
418 #power-domain-cells = <0>;
429 reg = <0 0x80000000 0 0xa00000>;
434 reg = <0 0x80a00000 0 0x400000>;
439 reg = <0 0x80e00000 0 0x3d0000>;
444 reg = <0 0xd8100000 0 0x40000>;
449 reg = <0 0x811d0000 0 0x30000>;
455 reg = <0 0x81a00000 0 0x260000>;
461 reg = <0 0x81c60000 0 0x20000>;
467 reg = <0 0x81c80000 0 0x74000>;
474 reg = <0 0x81d00000 0 0x200000>;
480 reg = <0 0x81f00000 0 0x20000>;
485 reg = <0 0x82600000 0 0x100000>;
490 reg = <0 0x82700000 0 0x100000>;
495 reg = <0 0x82800000 0 0x4600000>;
500 reg = <0 0x8a800000 0 0x10800000>;
505 reg = <0 0x9b000000 0 0x80000>;
510 reg = <0 0x9b080000 0 0x10000>;
515 reg = <0 0x9b090000 0 0xa000>;
520 reg = <0 0x9b09a000 0 0x2000>;
525 reg = <0 0x9b100000 0 0x180000>;
531 reg = <0 0x9b280000 0 0x60000>;
537 reg = <0 0x9b2e0000 0 0x20000>;
542 reg = <0 0x9b300000 0 0x800000>;
547 reg = <0 0x9bb00000 0 0x700000>;
552 reg = <0 0x9c200000 0 0x700000>;
557 reg = <0 0x9c900000 0 0x2000000>;
562 reg = <0 0x9e900000 0 0x80000>;
567 reg = <0 0x9e980000 0 0x80000>;
572 reg = <0 0x9ea00000 0 0x4080000>;
578 /* Linux kernel image is loaded at 0xa8000000 */
582 reg = <0x0 0xd4a80000 0x0 0x280000>;
590 reg = <0 0xd4d00000 0 0x3300000>;
595 reg = <0 0xd8000000 0 0x100000>;
600 reg = <0 0xd8140000 0 0x1c0000>;
605 reg = <0 0xd8300000 0 0x500000>;
610 reg = <0 0xd8800000 0 0x8a00000>;
615 reg = <0 0xe1200000 0 0x2740000>;
620 reg = <0 0xe6440000 0 0x279000>;
625 reg = <0 0xf3600000 0 0x4aee000>;
630 reg = <0 0xf80ee000 0 0x1000>;
635 reg = <0 0xf80ef000 0 0x9000>;
640 reg = <0 0xf80f8000 0 0x4000>;
645 reg = <0 0xf80fc000 0 0x4000>;
650 reg = <0 0xf8100000 0 0x100000>;
655 reg = <0 0xf8400000 0 0x4800000>;
660 reg = <0 0xfcc00000 0 0x4000>;
665 reg = <0 0xfcc04000 0 0x100000>;
670 reg = <0 0xfce00000 0 0x2900000>;
675 reg = <0 0xff700000 0 0x100000>;
689 qcom,local-pid = <0>;
713 qcom,local-pid = <0>;
737 qcom,local-pid = <0>;
763 soc: soc@0 {
765 ranges = <0 0 0 0 0x10 0>;
766 dma-ranges = <0 0 0 0 0x10 0>;
773 reg = <0 0x00100000 0 0x1f4200>;
781 <&ufs_mem_phy 0>,
789 reg = <0 0x00408000 0 0x1000>;
799 reg = <0 0x00800000 0 0x60000>;
813 dma-channel-mask = <0x3e>;
814 iommus = <&apps_smmu 0x436 0>;
820 reg = <0 0x008c0000 0 0x2000>;
825 iommus = <&apps_smmu 0x423 0>;
832 reg = <0 0x00880000 0 0x4000>;
836 pinctrl-0 = <&qup_i2c8_data_clk>;
839 #size-cells = <0>;
840 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
841 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
842 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
844 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
845 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
852 reg = <0 0x00880000 0 0x4000>;
857 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
858 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
859 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
860 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
862 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
863 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
866 #size-cells = <0>;
872 reg = <0 0x00884000 0 0x4000>;
876 pinctrl-0 = <&qup_i2c9_data_clk>;
879 #size-cells = <0>;
880 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
881 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
882 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
884 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
892 reg = <0 0x00884000 0 0x4000>;
897 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
898 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
899 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
900 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
902 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
906 #size-cells = <0>;
912 reg = <0 0x00888000 0 0x4000>;
916 pinctrl-0 = <&qup_i2c10_data_clk>;
919 #size-cells = <0>;
920 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
921 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
922 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
924 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
932 reg = <0 0x00888000 0 0x4000>;
937 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
938 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
939 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
940 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
942 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
946 #size-cells = <0>;
952 reg = <0 0x0088c000 0 0x4000>;
956 pinctrl-0 = <&qup_i2c11_data_clk>;
959 #size-cells = <0>;
960 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
961 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
962 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
964 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
972 reg = <0 0x0088c000 0 0x4000>;
977 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
978 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
979 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
980 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
982 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
986 #size-cells = <0>;
992 reg = <0 0x00890000 0 0x4000>;
996 pinctrl-0 = <&qup_i2c12_data_clk>;
999 #size-cells = <0>;
1000 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1001 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1002 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1004 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1012 reg = <0 0x00890000 0 0x4000>;
1017 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1018 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1019 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1020 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1022 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1026 #size-cells = <0>;
1032 reg = <0 0x00894000 0 0x4000>;
1036 pinctrl-0 = <&qup_i2c13_data_clk>;
1039 #size-cells = <0>;
1040 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1041 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1042 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1044 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1052 reg = <0 0x00894000 0 0x4000>;
1057 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1058 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1059 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1060 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1062 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1066 #size-cells = <0>;
1072 reg = <0 0x898000 0 0x4000>;
1076 pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>;
1078 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1079 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>;
1086 reg = <0 0x0089c000 0 0x4000>;
1090 pinctrl-0 = <&qup_i2c15_data_clk>;
1093 #size-cells = <0>;
1094 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1095 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1096 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1098 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>,
1106 reg = <0 0x0089c000 0 0x4000>;
1111 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
1112 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1113 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1114 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1116 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>,
1120 #size-cells = <0>;
1127 reg = <0x0 0x009c0000 0x0 0x2000>;
1137 reg = <0x0 0x00980000 0x0 0x4000>;
1142 pinctrl-0 = <&hub_i2c0_data_clk>;
1145 #size-cells = <0>;
1146 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1147 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1154 reg = <0x0 0x00984000 0x0 0x4000>;
1159 pinctrl-0 = <&hub_i2c1_data_clk>;
1162 #size-cells = <0>;
1163 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1164 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1171 reg = <0x0 0x00988000 0x0 0x4000>;
1176 pinctrl-0 = <&hub_i2c2_data_clk>;
1179 #size-cells = <0>;
1180 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1181 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1188 reg = <0x0 0x0098c000 0x0 0x4000>;
1193 pinctrl-0 = <&hub_i2c3_data_clk>;
1196 #size-cells = <0>;
1197 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1198 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1205 reg = <0x0 0x00990000 0x0 0x4000>;
1210 pinctrl-0 = <&hub_i2c4_data_clk>;
1213 #size-cells = <0>;
1214 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1215 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1222 reg = <0 0x00994000 0 0x4000>;
1227 pinctrl-0 = <&hub_i2c5_data_clk>;
1230 #size-cells = <0>;
1231 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1232 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1239 reg = <0 0x00998000 0 0x4000>;
1244 pinctrl-0 = <&hub_i2c6_data_clk>;
1247 #size-cells = <0>;
1248 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1249 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1256 reg = <0 0x0099c000 0 0x4000>;
1261 pinctrl-0 = <&hub_i2c7_data_clk>;
1264 #size-cells = <0>;
1265 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1266 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1273 reg = <0 0x009a0000 0 0x4000>;
1278 pinctrl-0 = <&hub_i2c8_data_clk>;
1281 #size-cells = <0>;
1282 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1283 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1290 reg = <0 0x009a4000 0 0x4000>;
1295 pinctrl-0 = <&hub_i2c9_data_clk>;
1298 #size-cells = <0>;
1299 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1300 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1309 reg = <0 0x00a00000 0 0x60000>;
1323 dma-channel-mask = <0x1e>;
1324 iommus = <&apps_smmu 0xb6 0>;
1330 reg = <0 0x00ac0000 0 0x2000>;
1335 iommus = <&apps_smmu 0xa3 0>;
1336 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>;
1344 reg = <0 0x00a80000 0 0x4000>;
1348 pinctrl-0 = <&qup_i2c0_data_clk>;
1351 #size-cells = <0>;
1352 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1353 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1354 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1356 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1357 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1364 reg = <0 0x00a80000 0 0x4000>;
1369 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1370 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1371 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1372 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1374 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1375 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1378 #size-cells = <0>;
1384 reg = <0 0x00a84000 0 0x4000>;
1388 pinctrl-0 = <&qup_i2c1_data_clk>;
1391 #size-cells = <0>;
1392 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1393 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1394 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1396 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1404 reg = <0 0x00a84000 0 0x4000>;
1409 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1410 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1411 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1412 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1414 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1418 #size-cells = <0>;
1424 reg = <0 0x00a88000 0 0x4000>;
1428 pinctrl-0 = <&qup_i2c2_data_clk>;
1431 #size-cells = <0>;
1432 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1433 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1434 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1436 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1444 reg = <0 0x00a88000 0 0x4000>;
1449 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1450 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1451 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1452 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1454 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1458 #size-cells = <0>;
1464 reg = <0 0x00a8c000 0 0x4000>;
1468 pinctrl-0 = <&qup_i2c3_data_clk>;
1471 #size-cells = <0>;
1472 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1473 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1474 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1476 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1484 reg = <0 0x00a8c000 0 0x4000>;
1489 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1490 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1491 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1492 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1494 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1498 #size-cells = <0>;
1504 reg = <0 0x00a90000 0 0x4000>;
1508 pinctrl-0 = <&qup_i2c4_data_clk>;
1511 #size-cells = <0>;
1512 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1513 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1514 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1516 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1524 reg = <0 0x00a90000 0 0x4000>;
1529 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1530 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1531 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1532 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1534 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1538 #size-cells = <0>;
1544 reg = <0 0x00a94000 0 0x4000>;
1548 pinctrl-0 = <&qup_i2c5_data_clk>;
1550 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1551 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1552 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1554 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1558 #size-cells = <0>;
1564 reg = <0 0x00a94000 0 0x4000>;
1569 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1570 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1571 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1572 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1574 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1578 #size-cells = <0>;
1584 reg = <0 0x00a98000 0 0x4000>;
1588 pinctrl-0 = <&qup_i2c6_data_clk>;
1590 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1591 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1592 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1594 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1598 #size-cells = <0>;
1604 reg = <0 0x00a98000 0 0x4000>;
1609 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1610 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1611 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1612 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1614 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
1618 #size-cells = <0>;
1624 reg = <0 0x00a9c000 0 0x4000>;
1628 pinctrl-0 = <&qup_uart7_default>;
1631 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1632 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1639 reg = <0 0x01500000 0 0x13080>;
1646 reg = <0 0x01600000 0 0x6200>;
1653 reg = <0 0x01680000 0 0x1d080>;
1660 reg = <0 0x016c0000 0 0x12200>;
1669 reg = <0 0x016e0000 0 0x14400>;
1678 reg = <0 0x01700000 0 0x1e400>;
1686 reg = <0 0x01780000 0 0x5b800>;
1693 reg = <0 0x010c3000 0 0x1000>;
1699 reg = <0 0x01c00000 0 0x3000>,
1700 <0 0x60000000 0 0xf1d>,
1701 <0 0x60000f20 0 0xa8>,
1702 <0 0x60001000 0 0x1000>,
1703 <0 0x60100000 0 0x100000>;
1707 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1708 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1709 bus-range = <0x00 0xff>;
1713 linux,pci-domain = <0>;
1720 interrupt-map-mask = <0 0 0 0x7>;
1721 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1722 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1723 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1724 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1741 interconnects = <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
1742 <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_0 0>;
1745 iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
1746 <0x100 &apps_smmu 0x1401 0x1>;
1761 reg = <0 0x01c06000 0 0x2000>;
1779 #clock-cells = <0>;
1782 #phy-cells = <0>;
1790 reg = <0x0 0x01c08000 0x0 0x3000>,
1791 <0x0 0x40000000 0x0 0xf1d>,
1792 <0x0 0x40000f20 0x0 0xa8>,
1793 <0x0 0x40001000 0x0 0x1000>,
1794 <0x0 0x40100000 0x0 0x100000>;
1798 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1799 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1800 bus-range = <0x00 0xff>;
1811 interrupt-map-mask = <0 0 0 0x7>;
1812 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1813 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1814 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1815 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1837 interconnects = <&pcie_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>,
1838 <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_1 0>;
1841 iommu-map = <0x0 &apps_smmu 0x1480 0x1>,
1842 <0x100 &apps_smmu 0x1481 0x1>;
1858 reg = <0x0 0x01c0e000 0x0 0x2000>;
1877 #clock-cells = <0>;
1880 #phy-cells = <0>;
1887 reg = <0x0 0x01dc4000 0x0 0x28000>;
1890 qcom,ee = <0>;
1892 iommus = <&apps_smmu 0x480 0x0>,
1893 <&apps_smmu 0x481 0x0>;
1898 reg = <0x0 0x01dfa000 0x0 0x6000>;
1901 iommus = <&apps_smmu 0x480 0x0>,
1902 <&apps_smmu 0x481 0x0>;
1903 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
1909 reg = <0x0 0x01d80000 0x0 0x2000>;
1916 resets = <&ufs_mem_hc 0>;
1920 #phy-cells = <0>;
1928 reg = <0x0 0x01d84000 0x0 0x3000>;
1940 iommus = <&apps_smmu 0x60 0x0>;
1943 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,
1944 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
1965 <0 0>,
1966 <0 0>,
1969 <0 0>,
1970 <0 0>,
1971 <0 0>;
1980 reg = <0 0x01d88000 0 0x8000>;
1986 reg = <0 0x01f40000 0 0x20000>;
1992 reg = <0 0x01fc0000 0 0x30000>;
2000 reg = <0x0 0x03d00000 0x0 0x40000>,
2001 <0x0 0x03d9e000 0x0 0x1000>,
2002 <0x0 0x03d61000 0x0 0x800>;
2009 iommus = <&adreno_smmu 0 0x0>,
2010 <&adreno_smmu 1 0x0>;
2070 reg = <0x0 0x03d6a000 0x0 0x35000>,
2071 <0x0 0x03d50000 0x0 0x10000>,
2072 <0x0 0x0b280000 0x0 0x10000>;
2099 iommus = <&adreno_smmu 5 0x0>;
2122 reg = <0 0x03d90000 0 0xa000>;
2134 reg = <0x0 0x03da0000 0x0 0x40000>;
2178 iommus = <&apps_smmu 0x4a0 0x0>,
2179 <&apps_smmu 0x4a2 0x0>;
2180 reg = <0 0x3f40000 0 0x10000>,
2181 <0 0x3f50000 0 0x5000>,
2182 <0 0x3e04000 0 0xfc000>;
2189 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2199 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
2200 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
2206 qcom,smem-states = <&ipa_smp2p_out 0>,
2216 reg = <0x0 0x04080000 0x0 0x4040>;
2219 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
2234 interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
2240 qcom,smem-states = <&smp2p_modem_out 0>;
2258 reg = <0 0x06aa0000 0 0x1000>;
2265 #clock-cells = <0>;
2272 reg = <0 0x06ab0000 0 0x10000>;
2278 pinctrl-0 = <&wsa2_swr_active>;
2284 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>;
2285 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
2286 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2287 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2288 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2289 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>;
2290 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>;
2291 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2292 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2295 #size-cells = <0>;
2302 reg = <0 0x06ac0000 0 0x1000>;
2309 #clock-cells = <0>;
2316 reg = <0 0x06ad0000 0 0x10000>;
2322 pinctrl-0 = <&rx_swr_active>;
2328 qcom,ports-sinterval = /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xff 0xff 0xff 0xff 0xff 0xff>;
2329 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
2330 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
2331 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff>;
2332 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff>;
2333 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff 0xff 0xff 0xff 0xff 0xff>;
2334 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
2335 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
2336 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
2339 #size-cells = <0>;
2346 reg = <0 0x06ae0000 0 0x1000>;
2353 #clock-cells = <0>;
2360 reg = <0 0x06b00000 0 0x1000>;
2367 #clock-cells = <0>;
2374 reg = <0 0x06b10000 0 0x10000>;
2380 pinctrl-0 = <&wsa_swr_active>;
2386 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>;
2387 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
2388 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2389 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2390 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2391 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>;
2392 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>;
2393 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2394 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2397 #size-cells = <0>;
2404 reg = <0 0x06d30000 0 0x10000>;
2412 pinctrl-0 = <&tx_swr_active>;
2416 qcom,dout-ports = <0>;
2417 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
2418 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>;
2419 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
2420 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
2421 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
2422 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
2423 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
2424 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
2425 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>;
2428 #size-cells = <0>;
2435 reg = <0 0x06d44000 0 0x1000>;
2441 #clock-cells = <0>;
2448 reg = <0 0x06e80000 0 0x20000>,
2449 <0 0x07250000 0 0x10000>;
2452 gpio-ranges = <&lpass_tlmm 0 0 23>;
2565 reg = <0 0x07400000 0 0x19080>;
2572 reg = <0 0x07430000 0 0x3a200>;
2579 reg = <0 0x07e40000 0 0xe080>;
2586 reg = <0 0x08804000 0 0x1000>;
2596 iommus = <&apps_smmu 0x540 0>;
2597 qcom,dll-config = <0x0007642c>;
2598 qcom,ddr-config = <0x80040868>;
2602 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
2603 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
2609 sdhci-caps-mask = <0x3 0>;
2640 reg = <0 0x0aaf0000 0 0x10000>;
2652 reg = <0 0x0ade0000 0 0x20000>;
2666 reg = <0 0x0ae00000 0 0x1000>;
2682 interconnects = <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>,
2683 <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
2686 iommus = <&apps_smmu 0x1c00 0x2>;
2696 reg = <0 0x0ae01000 0 0x8f000>,
2697 <0 0x0aeb0000 0 0x2008>;
2701 interrupts = <0>;
2725 #size-cells = <0>;
2727 port@0 {
2728 reg = <0>;
2776 reg = <0 0xae90000 0 0x200>,
2777 <0 0xae90200 0 0x200>,
2778 <0 0xae90400 0 0xc00>,
2779 <0 0xae91000 0 0x400>,
2780 <0 0xae91400 0 0x400>;
2802 #sound-dai-cells = <0>;
2811 #size-cells = <0>;
2813 port@0 {
2814 reg = <0>;
2854 reg = <0 0x0ae94000 0 0x400>;
2877 assigned-clock-parents = <&mdss_dsi0_phy 0>,
2886 #size-cells = <0>;
2892 #size-cells = <0>;
2894 port@0 {
2895 reg = <0>;
2930 reg = <0 0x0ae95000 0 0x200>,
2931 <0 0x0ae95200 0 0x280>,
2932 <0 0x0ae95500 0 0x400>;
2942 #phy-cells = <0>;
2949 reg = <0 0x0ae96000 0 0x400>;
2972 assigned-clock-parents = <&mdss_dsi1_phy 0>,
2981 #size-cells = <0>;
2987 #size-cells = <0>;
2989 port@0 {
2990 reg = <0>;
3006 reg = <0 0x0ae97000 0 0x200>,
3007 <0 0x0ae97200 0 0x280>,
3008 <0 0x0ae97500 0 0x400>;
3018 #phy-cells = <0>;
3026 reg = <0 0x0af00000 0 0x20000>;
3031 <&mdss_dsi0_phy 0>,
3033 <&mdss_dsi1_phy 0>,
3037 <0>, /* dp1 */
3038 <0>,
3039 <0>, /* dp2 */
3040 <0>,
3041 <0>, /* dp3 */
3042 <0>;
3052 reg = <0x0 0x088e3000 0x0 0x154>;
3053 #phy-cells = <0>;
3065 reg = <0x0 0x088e8000 0x0 0x3000>;
3086 #size-cells = <0>;
3088 port@0 {
3089 reg = <0>;
3113 reg = <0x0 0x0a6f8800 0x0 0x400>;
3149 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
3150 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
3157 reg = <0x0 0x0a600000 0x0 0xcd00>;
3159 iommus = <&apps_smmu 0x40 0x0>;
3169 #size-cells = <0>;
3171 port@0 {
3172 reg = <0>;
3190 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
3191 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
3201 reg = <0 0x0c271000 0 0x1000>, /* TM */
3202 <0 0x0c222000 0 0x1000>; /* SROT */
3212 reg = <0 0x0c272000 0 0x1000>, /* TM */
3213 <0 0x0c223000 0 0x1000>; /* SROT */
3223 reg = <0 0x0c273000 0 0x1000>, /* TM */
3224 <0 0x0c224000 0 0x1000>; /* SROT */
3234 reg = <0 0x0c300000 0 0x400>;
3240 #clock-cells = <0>;
3245 reg = <0 0x0c3f0000 0 0x400>;
3250 reg = <0 0x0c400000 0 0x3000>,
3251 <0 0x0c500000 0 0x4000000>,
3252 <0 0x0c440000 0 0x80000>,
3253 <0 0x0c4c0000 0 0x20000>,
3254 <0 0x0c42d000 0 0x4000>;
3258 qcom,ee = <0>;
3259 qcom,channel = <0>;
3260 qcom,bus-id = <0>;
3262 #size-cells = <0>;
3269 reg = <0 0x0f100000 0 0x300000>;
3275 gpio-ranges = <&tlmm 0 0 211>;
3801 reg = <0 0x15000000 0 0x100000>;
3905 reg = <0 0x17100000 0 0x10000>, /* GICD */
3906 <0 0x17180000 0 0x200000>; /* GICR * 8 */
3911 redistributor-stride = <0 0x40000>;
3918 reg = <0 0x17140000 0 0x20000>;
3926 reg = <0 0x17420000 0 0x1000>;
3927 ranges = <0 0 0 0x20000000>;
3932 reg = <0x17421000 0x1000>,
3933 <0x17422000 0x1000>;
3934 frame-number = <0>;
3940 reg = <0x17423000 0x1000>;
3947 reg = <0x17425000 0x1000>;
3954 reg = <0x17427000 0x1000>;
3961 reg = <0x17429000 0x1000>;
3968 reg = <0x1742b000 0x1000>;
3975 reg = <0x1742d000 0x1000>;
3985 reg = <0 0x17a00000 0 0x10000>,
3986 <0 0x17a10000 0 0x10000>,
3987 <0 0x17a20000 0 0x10000>,
3988 <0 0x17a30000 0 0x10000>;
3989 reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
3993 qcom,tcs-offset = <0xd00>;
3996 <WAKE_TCS 2>, <CONTROL_TCS 0>;
4083 reg = <0 0x17d91000 0 0x1000>,
4084 <0 0x17d92000 0 0x1000>,
4085 <0 0x17d93000 0 0x1000>;
4092 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
4099 reg = <0 0x24091000 0 0x1000>;
4108 opp-0 {
4148 reg = <0 0x240b6400 0 0x600>;
4157 opp-0 {
4185 reg = <0 0x24100000 0 0xbb800>;
4192 reg = <0 0x25000000 0 0x200000>,
4193 <0 0x25200000 0 0x200000>,
4194 <0 0x25400000 0 0x200000>,
4195 <0 0x25600000 0 0x200000>,
4196 <0 0x25800000 0 0x200000>;
4207 reg = <0x0 0x30000000 0x0 0x100>;
4210 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
4224 interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>;
4230 qcom,smem-states = <&smp2p_adsp_out 0>;
4250 #size-cells = <0>;
4255 iommus = <&apps_smmu 0x1003 0x80>,
4256 <&apps_smmu 0x1063 0x0>;
4262 iommus = <&apps_smmu 0x1004 0x80>,
4263 <&apps_smmu 0x1064 0x0>;
4269 iommus = <&apps_smmu 0x1005 0x80>,
4270 <&apps_smmu 0x1065 0x0>;
4276 iommus = <&apps_smmu 0x1006 0x80>,
4277 <&apps_smmu 0x1066 0x0>;
4283 iommus = <&apps_smmu 0x1007 0x80>,
4284 <&apps_smmu 0x1067 0x0>;
4294 #size-cells = <0>;
4299 #sound-dai-cells = <0>;
4305 iommus = <&apps_smmu 0x1001 0x80>,
4306 <&apps_smmu 0x1061 0x0>;
4332 reg = <0 0x320c0000 0 0xe080>;
4339 reg = <0x0 0x32300000 0x0 0x1400000>;
4342 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
4357 interconnects = <&nsp_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
4363 qcom,smem-states = <&smp2p_cdsp_out 0>;
4383 #size-cells = <0>;
4388 iommus = <&apps_smmu 0x1961 0x0>,
4389 <&apps_smmu 0x0c01 0x20>,
4390 <&apps_smmu 0x19c1 0x10>;
4396 iommus = <&apps_smmu 0x1962 0x0>,
4397 <&apps_smmu 0x0c02 0x20>,
4398 <&apps_smmu 0x19c2 0x10>;
4404 iommus = <&apps_smmu 0x1963 0x0>,
4405 <&apps_smmu 0x0c03 0x20>,
4406 <&apps_smmu 0x19c3 0x10>;
4412 iommus = <&apps_smmu 0x1964 0x0>,
4413 <&apps_smmu 0x0c04 0x20>,
4414 <&apps_smmu 0x19c4 0x10>;
4420 iommus = <&apps_smmu 0x1965 0x0>,
4421 <&apps_smmu 0x0c05 0x20>,
4422 <&apps_smmu 0x19c5 0x10>;
4428 iommus = <&apps_smmu 0x1966 0x0>,
4429 <&apps_smmu 0x0c06 0x20>,
4430 <&apps_smmu 0x19c6 0x10>;
4436 iommus = <&apps_smmu 0x1967 0x0>,
4437 <&apps_smmu 0x0c07 0x20>,
4438 <&apps_smmu 0x19c7 0x10>;
4444 iommus = <&apps_smmu 0x1968 0x0>,
4445 <&apps_smmu 0x0c08 0x20>,
4446 <&apps_smmu 0x19c8 0x10>;
4457 polling-delay-passive = <0>;
4458 polling-delay = <0>;
4459 thermal-sensors = <&tsens0 0>;
4477 polling-delay-passive = <0>;
4478 polling-delay = <0>;
4497 polling-delay-passive = <0>;
4498 polling-delay = <0>;
4517 polling-delay-passive = <0>;
4518 polling-delay = <0>;
4537 polling-delay-passive = <0>;
4538 polling-delay = <0>;
4557 polling-delay-passive = <0>;
4558 polling-delay = <0>;
4583 polling-delay-passive = <0>;
4584 polling-delay = <0>;
4609 polling-delay-passive = <0>;
4610 polling-delay = <0>;
4635 polling-delay-passive = <0>;
4636 polling-delay = <0>;
4661 polling-delay-passive = <0>;
4662 polling-delay = <0>;
4687 polling-delay-passive = <0>;
4688 polling-delay = <0>;
4713 polling-delay-passive = <0>;
4714 polling-delay = <0>;
4739 polling-delay-passive = <0>;
4740 polling-delay = <0>;
4765 polling-delay-passive = <0>;
4766 polling-delay = <0>;
4791 polling-delay-passive = <0>;
4792 polling-delay = <0>;
4817 polling-delay-passive = <0>;
4818 polling-delay = <0>;
4843 polling-delay-passive = <0>;
4844 polling-delay = <0>;
4845 thermal-sensors = <&tsens1 0>;
4863 polling-delay-passive = <0>;
4864 polling-delay = <0>;
4889 polling-delay-passive = <0>;
4890 polling-delay = <0>;
4915 polling-delay-passive = <0>;
4916 polling-delay = <0>;
4942 polling-delay = <0>;
4974 polling-delay = <0>;
5006 polling-delay = <0>;
5038 polling-delay = <0>;
5069 polling-delay-passive = <0>;
5070 polling-delay = <0>;
5090 polling-delay = <0>;
5115 polling-delay-passive = <0>;
5116 polling-delay = <0>;
5147 polling-delay-passive = <0>;
5148 polling-delay = <0>;
5179 polling-delay-passive = <0>;
5180 polling-delay = <0>;
5211 polling-delay-passive = <0>;
5212 polling-delay = <0>;
5243 polling-delay-passive = <0>;
5244 polling-delay = <0>;
5263 polling-delay-passive = <0>;
5264 polling-delay = <0>;
5283 polling-delay-passive = <0>;
5284 polling-delay = <0>;
5285 thermal-sensors = <&tsens2 0>;
5302 gpuss-0-thermal {
5304 polling-delay = <0>;
5336 polling-delay = <0>;
5368 polling-delay = <0>;
5400 polling-delay = <0>;
5432 polling-delay = <0>;
5464 polling-delay = <0>;
5496 polling-delay = <0>;
5528 polling-delay = <0>;