Lines Matching +full:opp +full:- +full:172000000
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
8 #include <dt-bindings/clock/qcom,rpmh.h>
9 #include <dt-bindings/clock/qcom,sm8450-camcc.h>
10 #include <dt-bindings/clock/qcom,sm8450-dispcc.h>
11 #include <dt-bindings/clock/qcom,sm8450-gpucc.h>
12 #include <dt-bindings/clock/qcom,sm8450-videocc.h>
13 #include <dt-bindings/dma/qcom-gpi.h>
14 #include <dt-bindings/firmware/qcom,scm.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/mailbox/qcom-ipcc.h>
17 #include <dt-bindings/phy/phy-qcom-qmp.h>
18 #include <dt-bindings/power/qcom,rpmhpd.h>
19 #include <dt-bindings/power/qcom-rpmpd.h>
20 #include <dt-bindings/interconnect/qcom,icc.h>
21 #include <dt-bindings/interconnect/qcom,sm8450.h>
22 #include <dt-bindings/reset/qcom,sm8450-gpucc.h>
23 #include <dt-bindings/soc/qcom,gpr.h>
24 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
25 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
26 #include <dt-bindings/thermal/thermal.h>
29 interrupt-parent = <&intc>;
31 #address-cells = <2>;
32 #size-cells = <2>;
37 xo_board: xo-board {
38 compatible = "fixed-clock";
39 #clock-cells = <0>;
40 clock-frequency = <76800000>;
43 sleep_clk: sleep-clk {
44 compatible = "fixed-clock";
45 #clock-cells = <0>;
46 clock-frequency = <32000>;
51 #address-cells = <2>;
52 #size-cells = <0>;
58 enable-method = "psci";
59 next-level-cache = <&L2_0>;
60 power-domains = <&CPU_PD0>;
61 power-domain-names = "psci";
62 qcom,freq-domain = <&cpufreq_hw 0>;
63 #cooling-cells = <2>;
65 L2_0: l2-cache {
67 cache-level = <2>;
68 cache-unified;
69 next-level-cache = <&L3_0>;
70 L3_0: l3-cache {
72 cache-level = <3>;
73 cache-unified;
82 enable-method = "psci";
83 next-level-cache = <&L2_100>;
84 power-domains = <&CPU_PD1>;
85 power-domain-names = "psci";
86 qcom,freq-domain = <&cpufreq_hw 0>;
87 #cooling-cells = <2>;
89 L2_100: l2-cache {
91 cache-level = <2>;
92 cache-unified;
93 next-level-cache = <&L3_0>;
101 enable-method = "psci";
102 next-level-cache = <&L2_200>;
103 power-domains = <&CPU_PD2>;
104 power-domain-names = "psci";
105 qcom,freq-domain = <&cpufreq_hw 0>;
106 #cooling-cells = <2>;
108 L2_200: l2-cache {
110 cache-level = <2>;
111 cache-unified;
112 next-level-cache = <&L3_0>;
120 enable-method = "psci";
121 next-level-cache = <&L2_300>;
122 power-domains = <&CPU_PD3>;
123 power-domain-names = "psci";
124 qcom,freq-domain = <&cpufreq_hw 0>;
125 #cooling-cells = <2>;
127 L2_300: l2-cache {
129 cache-level = <2>;
130 cache-unified;
131 next-level-cache = <&L3_0>;
139 enable-method = "psci";
140 next-level-cache = <&L2_400>;
141 power-domains = <&CPU_PD4>;
142 power-domain-names = "psci";
143 qcom,freq-domain = <&cpufreq_hw 1>;
144 #cooling-cells = <2>;
146 L2_400: l2-cache {
148 cache-level = <2>;
149 cache-unified;
150 next-level-cache = <&L3_0>;
158 enable-method = "psci";
159 next-level-cache = <&L2_500>;
160 power-domains = <&CPU_PD5>;
161 power-domain-names = "psci";
162 qcom,freq-domain = <&cpufreq_hw 1>;
163 #cooling-cells = <2>;
165 L2_500: l2-cache {
167 cache-level = <2>;
168 cache-unified;
169 next-level-cache = <&L3_0>;
177 enable-method = "psci";
178 next-level-cache = <&L2_600>;
179 power-domains = <&CPU_PD6>;
180 power-domain-names = "psci";
181 qcom,freq-domain = <&cpufreq_hw 1>;
182 #cooling-cells = <2>;
184 L2_600: l2-cache {
186 cache-level = <2>;
187 cache-unified;
188 next-level-cache = <&L3_0>;
196 enable-method = "psci";
197 next-level-cache = <&L2_700>;
198 power-domains = <&CPU_PD7>;
199 power-domain-names = "psci";
200 qcom,freq-domain = <&cpufreq_hw 2>;
201 #cooling-cells = <2>;
203 L2_700: l2-cache {
205 cache-level = <2>;
206 cache-unified;
207 next-level-cache = <&L3_0>;
211 cpu-map {
247 idle-states {
248 entry-method = "psci";
250 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
251 compatible = "arm,idle-state";
252 idle-state-name = "silver-rail-power-collapse";
253 arm,psci-suspend-param = <0x40000004>;
254 entry-latency-us = <800>;
255 exit-latency-us = <750>;
256 min-residency-us = <4090>;
257 local-timer-stop;
260 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
261 compatible = "arm,idle-state";
262 idle-state-name = "gold-rail-power-collapse";
263 arm,psci-suspend-param = <0x40000004>;
264 entry-latency-us = <600>;
265 exit-latency-us = <1550>;
266 min-residency-us = <4791>;
267 local-timer-stop;
271 domain-idle-states {
272 CLUSTER_SLEEP_0: cluster-sleep-0 {
273 compatible = "domain-idle-state";
274 arm,psci-suspend-param = <0x41000044>;
275 entry-latency-us = <1050>;
276 exit-latency-us = <2500>;
277 min-residency-us = <5309>;
280 CLUSTER_SLEEP_1: cluster-sleep-1 {
281 compatible = "domain-idle-state";
282 arm,psci-suspend-param = <0x4100c344>;
283 entry-latency-us = <2700>;
284 exit-latency-us = <3500>;
285 min-residency-us = <13959>;
292 compatible = "qcom,scm-sm8450", "qcom,scm";
293 qcom,dload-mode = <&tcsr 0x13000>;
295 #reset-cells = <1>;
299 clk_virt: interconnect-0 {
300 compatible = "qcom,sm8450-clk-virt";
301 #interconnect-cells = <2>;
302 qcom,bcm-voters = <&apps_bcm_voter>;
305 mc_virt: interconnect-1 {
306 compatible = "qcom,sm8450-mc-virt";
307 #interconnect-cells = <2>;
308 qcom,bcm-voters = <&apps_bcm_voter>;
318 compatible = "arm,armv8-pmuv3";
323 compatible = "arm,psci-1.0";
326 CPU_PD0: power-domain-cpu0 {
327 #power-domain-cells = <0>;
328 power-domains = <&CLUSTER_PD>;
329 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
332 CPU_PD1: power-domain-cpu1 {
333 #power-domain-cells = <0>;
334 power-domains = <&CLUSTER_PD>;
335 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
338 CPU_PD2: power-domain-cpu2 {
339 #power-domain-cells = <0>;
340 power-domains = <&CLUSTER_PD>;
341 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
344 CPU_PD3: power-domain-cpu3 {
345 #power-domain-cells = <0>;
346 power-domains = <&CLUSTER_PD>;
347 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
350 CPU_PD4: power-domain-cpu4 {
351 #power-domain-cells = <0>;
352 power-domains = <&CLUSTER_PD>;
353 domain-idle-states = <&BIG_CPU_SLEEP_0>;
356 CPU_PD5: power-domain-cpu5 {
357 #power-domain-cells = <0>;
358 power-domains = <&CLUSTER_PD>;
359 domain-idle-states = <&BIG_CPU_SLEEP_0>;
362 CPU_PD6: power-domain-cpu6 {
363 #power-domain-cells = <0>;
364 power-domains = <&CLUSTER_PD>;
365 domain-idle-states = <&BIG_CPU_SLEEP_0>;
368 CPU_PD7: power-domain-cpu7 {
369 #power-domain-cells = <0>;
370 power-domains = <&CLUSTER_PD>;
371 domain-idle-states = <&BIG_CPU_SLEEP_0>;
374 CLUSTER_PD: power-domain-cpu-cluster0 {
375 #power-domain-cells = <0>;
376 domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>;
380 qup_opp_table_100mhz: opp-table-qup {
381 compatible = "operating-points-v2";
383 opp-50000000 {
384 opp-hz = /bits/ 64 <50000000>;
385 required-opps = <&rpmhpd_opp_min_svs>;
388 opp-75000000 {
389 opp-hz = /bits/ 64 <75000000>;
390 required-opps = <&rpmhpd_opp_low_svs>;
393 opp-100000000 {
394 opp-hz = /bits/ 64 <100000000>;
395 required-opps = <&rpmhpd_opp_svs>;
399 reserved_memory: reserved-memory {
400 #address-cells = <2>;
401 #size-cells = <2>;
406 no-map;
411 no-map;
416 no-map;
421 no-map;
426 no-map;
430 compatible = "qcom,cmd-db";
432 no-map;
437 no-map;
442 no-map;
447 no-map;
452 no-map;
460 no-map;
465 no-map;
470 no-map;
475 no-map;
480 no-map;
485 no-map;
490 no-map;
495 no-map;
500 no-map;
505 no-map;
510 no-map;
516 no-map;
522 no-map;
527 no-map;
532 no-map;
537 no-map;
541 compatible = "qcom,rmtfs-mem";
543 no-map;
545 qcom,client-id = <1>;
551 no-map;
556 no-map;
565 no-map;
570 no-map;
575 no-map;
580 no-map;
585 no-map;
590 no-map;
595 no-map;
600 no-map;
605 no-map;
610 no-map;
615 no-map;
620 no-map;
625 no-map;
630 no-map;
634 smp2p-adsp {
637 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
643 qcom,local-pid = <0>;
644 qcom,remote-pid = <2>;
646 smp2p_adsp_out: master-kernel {
647 qcom,entry-name = "master-kernel";
648 #qcom,smem-state-cells = <1>;
651 smp2p_adsp_in: slave-kernel {
652 qcom,entry-name = "slave-kernel";
653 interrupt-controller;
654 #interrupt-cells = <2>;
658 smp2p-cdsp {
661 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
667 qcom,local-pid = <0>;
668 qcom,remote-pid = <5>;
670 smp2p_cdsp_out: master-kernel {
671 qcom,entry-name = "master-kernel";
672 #qcom,smem-state-cells = <1>;
675 smp2p_cdsp_in: slave-kernel {
676 qcom,entry-name = "slave-kernel";
677 interrupt-controller;
678 #interrupt-cells = <2>;
682 smp2p-modem {
685 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
691 qcom,local-pid = <0>;
692 qcom,remote-pid = <1>;
694 smp2p_modem_out: master-kernel {
695 qcom,entry-name = "master-kernel";
696 #qcom,smem-state-cells = <1>;
699 smp2p_modem_in: slave-kernel {
700 qcom,entry-name = "slave-kernel";
701 interrupt-controller;
702 #interrupt-cells = <2>;
705 ipa_smp2p_out: ipa-ap-to-modem {
706 qcom,entry-name = "ipa";
707 #qcom,smem-state-cells = <1>;
710 ipa_smp2p_in: ipa-modem-to-ap {
711 qcom,entry-name = "ipa";
712 interrupt-controller;
713 #interrupt-cells = <2>;
717 smp2p-slpi {
720 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
726 qcom,local-pid = <0>;
727 qcom,remote-pid = <3>;
729 smp2p_slpi_out: master-kernel {
730 qcom,entry-name = "master-kernel";
731 #qcom,smem-state-cells = <1>;
734 smp2p_slpi_in: slave-kernel {
735 qcom,entry-name = "slave-kernel";
736 interrupt-controller;
737 #interrupt-cells = <2>;
742 #address-cells = <2>;
743 #size-cells = <2>;
745 dma-ranges = <0 0 0 0 0x10 0>;
746 compatible = "simple-bus";
748 gcc: clock-controller@100000 {
749 compatible = "qcom,gcc-sm8450";
751 #clock-cells = <1>;
752 #reset-cells = <1>;
753 #power-domain-cells = <1>;
763 clock-names = "bi_tcxo",
774 gpi_dma2: dma-controller@800000 {
775 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
776 #dma-cells = <3>;
790 dma-channels = <12>;
791 dma-channel-mask = <0x7e>;
797 compatible = "qcom,geni-se-qup";
799 clock-names = "m-ahb", "s-ahb";
803 #address-cells = <2>;
804 #size-cells = <2>;
809 compatible = "qcom,geni-i2c";
811 clock-names = "se";
813 pinctrl-names = "default";
814 pinctrl-0 = <&qup_i2c15_data_clk>;
816 #address-cells = <1>;
817 #size-cells = <0>;
821 interconnect-names = "qup-core", "qup-config", "qup-memory";
824 dma-names = "tx", "rx";
829 compatible = "qcom,geni-spi";
831 clock-names = "se";
834 pinctrl-names = "default";
835 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
838 interconnect-names = "qup-core", "qup-config";
841 dma-names = "tx", "rx";
842 #address-cells = <1>;
843 #size-cells = <0>;
848 compatible = "qcom,geni-i2c";
850 clock-names = "se";
852 pinctrl-names = "default";
853 pinctrl-0 = <&qup_i2c16_data_clk>;
855 #address-cells = <1>;
856 #size-cells = <0>;
860 interconnect-names = "qup-core", "qup-config", "qup-memory";
863 dma-names = "tx", "rx";
868 compatible = "qcom,geni-spi";
870 clock-names = "se";
873 pinctrl-names = "default";
874 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>;
877 interconnect-names = "qup-core", "qup-config";
880 dma-names = "tx", "rx";
881 #address-cells = <1>;
882 #size-cells = <0>;
887 compatible = "qcom,geni-i2c";
889 clock-names = "se";
891 pinctrl-names = "default";
892 pinctrl-0 = <&qup_i2c17_data_clk>;
894 #address-cells = <1>;
895 #size-cells = <0>;
899 interconnect-names = "qup-core", "qup-config", "qup-memory";
902 dma-names = "tx", "rx";
907 compatible = "qcom,geni-spi";
909 clock-names = "se";
912 pinctrl-names = "default";
913 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>;
916 interconnect-names = "qup-core", "qup-config";
919 dma-names = "tx", "rx";
920 #address-cells = <1>;
921 #size-cells = <0>;
926 compatible = "qcom,geni-i2c";
928 clock-names = "se";
930 pinctrl-names = "default";
931 pinctrl-0 = <&qup_i2c18_data_clk>;
933 #address-cells = <1>;
934 #size-cells = <0>;
938 interconnect-names = "qup-core", "qup-config", "qup-memory";
941 dma-names = "tx", "rx";
946 compatible = "qcom,geni-spi";
948 clock-names = "se";
951 pinctrl-names = "default";
952 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>;
955 interconnect-names = "qup-core", "qup-config";
958 dma-names = "tx", "rx";
959 #address-cells = <1>;
960 #size-cells = <0>;
965 compatible = "qcom,geni-i2c";
967 clock-names = "se";
969 pinctrl-names = "default";
970 pinctrl-0 = <&qup_i2c19_data_clk>;
972 #address-cells = <1>;
973 #size-cells = <0>;
977 interconnect-names = "qup-core", "qup-config", "qup-memory";
980 dma-names = "tx", "rx";
985 compatible = "qcom,geni-spi";
987 clock-names = "se";
990 pinctrl-names = "default";
991 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>;
994 interconnect-names = "qup-core", "qup-config";
997 dma-names = "tx", "rx";
998 #address-cells = <1>;
999 #size-cells = <0>;
1004 compatible = "qcom,geni-i2c";
1006 clock-names = "se";
1008 pinctrl-names = "default";
1009 pinctrl-0 = <&qup_i2c20_data_clk>;
1011 #address-cells = <1>;
1012 #size-cells = <0>;
1016 interconnect-names = "qup-core", "qup-config", "qup-memory";
1019 dma-names = "tx", "rx";
1024 compatible = "qcom,geni-uart";
1026 clock-names = "se";
1028 pinctrl-names = "default";
1029 pinctrl-0 = <&qup_uart20_default>;
1035 compatible = "qcom,geni-spi";
1037 clock-names = "se";
1040 pinctrl-names = "default";
1041 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>;
1044 interconnect-names = "qup-core", "qup-config";
1047 dma-names = "tx", "rx";
1048 #address-cells = <1>;
1049 #size-cells = <0>;
1054 compatible = "qcom,geni-i2c";
1056 clock-names = "se";
1058 pinctrl-names = "default";
1059 pinctrl-0 = <&qup_i2c21_data_clk>;
1061 #address-cells = <1>;
1062 #size-cells = <0>;
1066 interconnect-names = "qup-core", "qup-config", "qup-memory";
1069 dma-names = "tx", "rx";
1074 compatible = "qcom,geni-spi";
1076 clock-names = "se";
1079 pinctrl-names = "default";
1080 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>;
1083 interconnect-names = "qup-core", "qup-config";
1086 dma-names = "tx", "rx";
1087 #address-cells = <1>;
1088 #size-cells = <0>;
1093 gpi_dma0: dma-controller@900000 {
1094 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
1095 #dma-cells = <3>;
1109 dma-channels = <12>;
1110 dma-channel-mask = <0x7e>;
1116 compatible = "qcom,geni-se-qup";
1118 clock-names = "m-ahb", "s-ahb";
1123 interconnect-names = "qup-core";
1124 #address-cells = <2>;
1125 #size-cells = <2>;
1130 compatible = "qcom,geni-i2c";
1132 clock-names = "se";
1134 pinctrl-names = "default";
1135 pinctrl-0 = <&qup_i2c0_data_clk>;
1137 #address-cells = <1>;
1138 #size-cells = <0>;
1142 interconnect-names = "qup-core", "qup-config", "qup-memory";
1145 dma-names = "tx", "rx";
1150 compatible = "qcom,geni-spi";
1152 clock-names = "se";
1155 pinctrl-names = "default";
1156 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1157 power-domains = <&rpmhpd RPMHPD_CX>;
1158 operating-points-v2 = <&qup_opp_table_100mhz>;
1162 interconnect-names = "qup-core", "qup-config", "qup-memory";
1165 dma-names = "tx", "rx";
1166 #address-cells = <1>;
1167 #size-cells = <0>;
1172 compatible = "qcom,geni-i2c";
1174 clock-names = "se";
1176 pinctrl-names = "default";
1177 pinctrl-0 = <&qup_i2c1_data_clk>;
1179 #address-cells = <1>;
1180 #size-cells = <0>;
1184 interconnect-names = "qup-core", "qup-config", "qup-memory";
1187 dma-names = "tx", "rx";
1192 compatible = "qcom,geni-spi";
1194 clock-names = "se";
1197 pinctrl-names = "default";
1198 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1202 interconnect-names = "qup-core", "qup-config", "qup-memory";
1205 dma-names = "tx", "rx";
1206 #address-cells = <1>;
1207 #size-cells = <0>;
1212 compatible = "qcom,geni-i2c";
1214 clock-names = "se";
1216 pinctrl-names = "default";
1217 pinctrl-0 = <&qup_i2c2_data_clk>;
1219 #address-cells = <1>;
1220 #size-cells = <0>;
1224 interconnect-names = "qup-core", "qup-config", "qup-memory";
1227 dma-names = "tx", "rx";
1232 compatible = "qcom,geni-spi";
1234 clock-names = "se";
1237 pinctrl-names = "default";
1238 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1242 interconnect-names = "qup-core", "qup-config", "qup-memory";
1245 dma-names = "tx", "rx";
1246 #address-cells = <1>;
1247 #size-cells = <0>;
1253 compatible = "qcom,geni-i2c";
1255 clock-names = "se";
1257 pinctrl-names = "default";
1258 pinctrl-0 = <&qup_i2c3_data_clk>;
1260 #address-cells = <1>;
1261 #size-cells = <0>;
1265 interconnect-names = "qup-core", "qup-config", "qup-memory";
1268 dma-names = "tx", "rx";
1273 compatible = "qcom,geni-spi";
1275 clock-names = "se";
1278 pinctrl-names = "default";
1279 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1283 interconnect-names = "qup-core", "qup-config", "qup-memory";
1286 dma-names = "tx", "rx";
1287 #address-cells = <1>;
1288 #size-cells = <0>;
1293 compatible = "qcom,geni-i2c";
1295 clock-names = "se";
1297 pinctrl-names = "default";
1298 pinctrl-0 = <&qup_i2c4_data_clk>;
1300 #address-cells = <1>;
1301 #size-cells = <0>;
1305 interconnect-names = "qup-core", "qup-config", "qup-memory";
1308 dma-names = "tx", "rx";
1313 compatible = "qcom,geni-spi";
1315 clock-names = "se";
1318 pinctrl-names = "default";
1319 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1320 power-domains = <&rpmhpd RPMHPD_CX>;
1321 operating-points-v2 = <&qup_opp_table_100mhz>;
1325 interconnect-names = "qup-core", "qup-config", "qup-memory";
1328 dma-names = "tx", "rx";
1329 #address-cells = <1>;
1330 #size-cells = <0>;
1335 compatible = "qcom,geni-i2c";
1337 clock-names = "se";
1339 pinctrl-names = "default";
1340 pinctrl-0 = <&qup_i2c5_data_clk>;
1342 #address-cells = <1>;
1343 #size-cells = <0>;
1347 interconnect-names = "qup-core", "qup-config", "qup-memory";
1350 dma-names = "tx", "rx";
1355 compatible = "qcom,geni-spi";
1357 clock-names = "se";
1360 pinctrl-names = "default";
1361 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1365 interconnect-names = "qup-core", "qup-config", "qup-memory";
1368 dma-names = "tx", "rx";
1369 #address-cells = <1>;
1370 #size-cells = <0>;
1376 compatible = "qcom,geni-i2c";
1378 clock-names = "se";
1380 pinctrl-names = "default";
1381 pinctrl-0 = <&qup_i2c6_data_clk>;
1383 #address-cells = <1>;
1384 #size-cells = <0>;
1388 interconnect-names = "qup-core", "qup-config", "qup-memory";
1391 dma-names = "tx", "rx";
1396 compatible = "qcom,geni-spi";
1398 clock-names = "se";
1401 pinctrl-names = "default";
1402 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1406 interconnect-names = "qup-core", "qup-config", "qup-memory";
1409 dma-names = "tx", "rx";
1410 #address-cells = <1>;
1411 #size-cells = <0>;
1416 compatible = "qcom,geni-debug-uart";
1418 clock-names = "se";
1420 pinctrl-names = "default";
1421 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
1427 gpi_dma1: dma-controller@a00000 {
1428 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
1429 #dma-cells = <3>;
1443 dma-channels = <12>;
1444 dma-channel-mask = <0x7e>;
1450 compatible = "qcom,geni-se-qup";
1452 clock-names = "m-ahb", "s-ahb";
1457 interconnect-names = "qup-core";
1458 #address-cells = <2>;
1459 #size-cells = <2>;
1464 compatible = "qcom,geni-i2c";
1466 clock-names = "se";
1468 pinctrl-names = "default";
1469 pinctrl-0 = <&qup_i2c8_data_clk>;
1471 #address-cells = <1>;
1472 #size-cells = <0>;
1476 interconnect-names = "qup-core", "qup-config", "qup-memory";
1479 dma-names = "tx", "rx";
1484 compatible = "qcom,geni-spi";
1486 clock-names = "se";
1489 pinctrl-names = "default";
1490 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1494 interconnect-names = "qup-core", "qup-config", "qup-memory";
1497 dma-names = "tx", "rx";
1498 #address-cells = <1>;
1499 #size-cells = <0>;
1504 compatible = "qcom,geni-i2c";
1506 clock-names = "se";
1508 pinctrl-names = "default";
1509 pinctrl-0 = <&qup_i2c9_data_clk>;
1511 #address-cells = <1>;
1512 #size-cells = <0>;
1516 interconnect-names = "qup-core", "qup-config", "qup-memory";
1519 dma-names = "tx", "rx";
1524 compatible = "qcom,geni-spi";
1526 clock-names = "se";
1529 pinctrl-names = "default";
1530 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1534 interconnect-names = "qup-core", "qup-config", "qup-memory";
1537 dma-names = "tx", "rx";
1538 #address-cells = <1>;
1539 #size-cells = <0>;
1544 compatible = "qcom,geni-i2c";
1546 clock-names = "se";
1548 pinctrl-names = "default";
1549 pinctrl-0 = <&qup_i2c10_data_clk>;
1551 #address-cells = <1>;
1552 #size-cells = <0>;
1556 interconnect-names = "qup-core", "qup-config", "qup-memory";
1559 dma-names = "tx", "rx";
1564 compatible = "qcom,geni-spi";
1566 clock-names = "se";
1569 pinctrl-names = "default";
1570 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1574 interconnect-names = "qup-core", "qup-config", "qup-memory";
1577 dma-names = "tx", "rx";
1578 #address-cells = <1>;
1579 #size-cells = <0>;
1584 compatible = "qcom,geni-i2c";
1586 clock-names = "se";
1588 pinctrl-names = "default";
1589 pinctrl-0 = <&qup_i2c11_data_clk>;
1591 #address-cells = <1>;
1592 #size-cells = <0>;
1596 interconnect-names = "qup-core", "qup-config", "qup-memory";
1599 dma-names = "tx", "rx";
1604 compatible = "qcom,geni-spi";
1606 clock-names = "se";
1609 pinctrl-names = "default";
1610 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1614 interconnect-names = "qup-core", "qup-config", "qup-memory";
1617 dma-names = "tx", "rx";
1618 #address-cells = <1>;
1619 #size-cells = <0>;
1624 compatible = "qcom,geni-i2c";
1626 clock-names = "se";
1628 pinctrl-names = "default";
1629 pinctrl-0 = <&qup_i2c12_data_clk>;
1631 #address-cells = <1>;
1632 #size-cells = <0>;
1636 interconnect-names = "qup-core", "qup-config", "qup-memory";
1639 dma-names = "tx", "rx";
1644 compatible = "qcom,geni-spi";
1646 clock-names = "se";
1649 pinctrl-names = "default";
1650 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1654 interconnect-names = "qup-core", "qup-config", "qup-memory";
1657 dma-names = "tx", "rx";
1658 #address-cells = <1>;
1659 #size-cells = <0>;
1664 compatible = "qcom,geni-i2c";
1666 clock-names = "se";
1668 pinctrl-names = "default";
1669 pinctrl-0 = <&qup_i2c13_data_clk>;
1674 interconnect-names = "qup-core", "qup-config", "qup-memory";
1677 dma-names = "tx", "rx";
1678 #address-cells = <1>;
1679 #size-cells = <0>;
1684 compatible = "qcom,geni-spi";
1686 clock-names = "se";
1689 pinctrl-names = "default";
1690 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1694 interconnect-names = "qup-core", "qup-config", "qup-memory";
1697 dma-names = "tx", "rx";
1698 #address-cells = <1>;
1699 #size-cells = <0>;
1704 compatible = "qcom,geni-i2c";
1706 clock-names = "se";
1708 pinctrl-names = "default";
1709 pinctrl-0 = <&qup_i2c14_data_clk>;
1714 interconnect-names = "qup-core", "qup-config", "qup-memory";
1717 dma-names = "tx", "rx";
1718 #address-cells = <1>;
1719 #size-cells = <0>;
1724 compatible = "qcom,geni-spi";
1726 clock-names = "se";
1729 pinctrl-names = "default";
1730 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
1734 interconnect-names = "qup-core", "qup-config", "qup-memory";
1737 dma-names = "tx", "rx";
1738 #address-cells = <1>;
1739 #size-cells = <0>;
1745 compatible = "qcom,sm8450-trng", "qcom,trng";
1750 compatible = "qcom,pcie-sm8450-pcie0";
1756 reg-names = "parf", "dbi", "elbi", "atu", "config";
1758 linux,pci-domain = <0>;
1759 bus-range = <0x00 0xff>;
1760 num-lanes = <1>;
1762 #address-cells = <3>;
1763 #size-cells = <2>;
1772 msi-map = <0x0 &gic_its 0x5981 0x1>,
1774 msi-map-mask = <0xff00>;
1776 interrupt-names = "msi";
1777 #interrupt-cells = <1>;
1778 interrupt-map-mask = <0 0 0 0x7>;
1779 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1796 clock-names = "pipe",
1809 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
1813 reset-names = "pci";
1815 power-domains = <&gcc PCIE_0_GDSC>;
1818 phy-names = "pciephy";
1820 perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
1821 wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
1823 pinctrl-names = "default";
1824 pinctrl-0 = <&pcie0_default_state>;
1830 compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy";
1838 clock-names = "aux",
1844 clock-output-names = "pcie_0_pipe_clk";
1845 #clock-cells = <0>;
1847 #phy-cells = <0>;
1850 reset-names = "phy";
1852 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
1853 assigned-clock-rates = <100000000>;
1859 compatible = "qcom,pcie-sm8450-pcie1";
1865 reg-names = "parf", "dbi", "elbi", "atu", "config";
1867 linux,pci-domain = <1>;
1868 bus-range = <0x00 0xff>;
1869 num-lanes = <2>;
1871 #address-cells = <3>;
1872 #size-cells = <2>;
1881 msi-map = <0x0 &gic_its 0x5a01 0x1>,
1883 msi-map-mask = <0xff00>;
1885 interrupt-names = "msi";
1886 #interrupt-cells = <1>;
1887 interrupt-map-mask = <0 0 0 0x7>;
1888 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1904 clock-names = "pipe",
1916 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
1920 reset-names = "pci";
1922 power-domains = <&gcc PCIE_1_GDSC>;
1925 phy-names = "pciephy";
1927 perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
1928 wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
1930 pinctrl-names = "default";
1931 pinctrl-0 = <&pcie1_default_state>;
1937 compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy";
1945 clock-names = "aux",
1951 clock-output-names = "pcie_1_pipe_clk";
1952 #clock-cells = <0>;
1954 #phy-cells = <0>;
1957 reset-names = "phy";
1959 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
1960 assigned-clock-rates = <100000000>;
1966 compatible = "qcom,sm8450-config-noc";
1968 #interconnect-cells = <2>;
1969 qcom,bcm-voters = <&apps_bcm_voter>;
1973 compatible = "qcom,sm8450-system-noc";
1975 #interconnect-cells = <2>;
1976 qcom,bcm-voters = <&apps_bcm_voter>;
1980 compatible = "qcom,sm8450-pcie-anoc";
1982 #interconnect-cells = <2>;
1983 qcom,bcm-voters = <&apps_bcm_voter>;
1987 compatible = "qcom,sm8450-aggre1-noc";
1989 #interconnect-cells = <2>;
1992 qcom,bcm-voters = <&apps_bcm_voter>;
1996 compatible = "qcom,sm8450-aggre2-noc";
1998 #interconnect-cells = <2>;
1999 qcom,bcm-voters = <&apps_bcm_voter>;
2007 compatible = "qcom,sm8450-mmss-noc";
2009 #interconnect-cells = <2>;
2010 qcom,bcm-voters = <&apps_bcm_voter>;
2014 compatible = "qcom,tcsr-mutex";
2016 #hwlock-cells = <1>;
2020 compatible = "qcom,sm8450-tcsr", "syscon";
2025 compatible = "qcom,adreno-730.1", "qcom,adreno";
2029 reg-names = "kgsl_3d0_reg_memory",
2038 operating-points-v2 = <&gpu_opp_table>;
2044 zap-shader {
2045 memory-region = <&gpu_micro_code_mem>;
2048 gpu_opp_table: opp-table {
2049 compatible = "operating-points-v2";
2051 opp-818000000 {
2052 opp-hz = /bits/ 64 <818000000>;
2053 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2056 opp-791000000 {
2057 opp-hz = /bits/ 64 <791000000>;
2058 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2061 opp-734000000 {
2062 opp-hz = /bits/ 64 <734000000>;
2063 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2066 opp-640000000 {
2067 opp-hz = /bits/ 64 <640000000>;
2068 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2071 opp-599000000 {
2072 opp-hz = /bits/ 64 <599000000>;
2073 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2076 opp-545000000 {
2077 opp-hz = /bits/ 64 <545000000>;
2078 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
2081 opp-492000000 {
2082 opp-hz = /bits/ 64 <492000000>;
2083 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2086 opp-421000000 {
2087 opp-hz = /bits/ 64 <421000000>;
2088 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
2091 opp-350000000 {
2092 opp-hz = /bits/ 64 <350000000>;
2093 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2096 opp-317000000 {
2097 opp-hz = /bits/ 64 <317000000>;
2098 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2101 opp-285000000 {
2102 opp-hz = /bits/ 64 <285000000>;
2103 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
2106 opp-220000000 {
2107 opp-hz = /bits/ 64 <220000000>;
2108 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
2114 compatible = "qcom,adreno-gmu-730.1", "qcom,adreno-gmu";
2118 reg-names = "gmu", "rscc", "gmu_pdc";
2122 interrupt-names = "hfi", "gmu";
2131 clock-names = "ahb",
2139 power-domains = <&gpucc GPU_CX_GDSC>,
2141 power-domain-names = "cx",
2148 operating-points-v2 = <&gmu_opp_table>;
2150 gmu_opp_table: opp-table {
2151 compatible = "operating-points-v2";
2153 opp-500000000 {
2154 opp-hz = /bits/ 64 <500000000>;
2155 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2158 opp-200000000 {
2159 opp-hz = /bits/ 64 <200000000>;
2160 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2165 gpucc: clock-controller@3d90000 {
2166 compatible = "qcom,sm8450-gpucc";
2171 #clock-cells = <1>;
2172 #reset-cells = <1>;
2173 #power-domain-cells = <1>;
2177 compatible = "qcom,sm8450-smmu-500", "qcom,adreno-smmu",
2178 "qcom,smmu-500", "arm,mmu-500";
2180 #iommu-cells = <2>;
2181 #global-interrupts = <1>;
2214 clock-names = "gmu",
2220 power-domains = <&gpucc GPU_CX_GDSC>;
2221 dma-coherent;
2225 compatible = "qcom,sm8450-usb-hs-phy",
2226 "qcom,usb-snps-hs-7nm-phy";
2229 #phy-cells = <0>;
2232 clock-names = "ref";
2238 compatible = "qcom,sm8450-qmp-usb3-dp-phy";
2245 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
2249 reset-names = "phy", "common";
2251 #clock-cells = <1>;
2252 #phy-cells = <1>;
2257 #address-cells = <1>;
2258 #size-cells = <0>;
2284 compatible = "qcom,sm8450-slpi-pas";
2287 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>,
2292 interrupt-names = "wdog", "fatal", "ready",
2293 "handover", "stop-ack";
2296 clock-names = "xo";
2298 power-domains = <&rpmhpd RPMHPD_LCX>,
2300 power-domain-names = "lcx", "lmx";
2302 memory-region = <&slpi_mem>;
2306 qcom,smem-states = <&smp2p_slpi_out 0>;
2307 qcom,smem-state-names = "stop";
2311 glink-edge {
2312 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
2319 qcom,remote-pid = <3>;
2323 qcom,glink-channels = "fastrpcglink-apps-dsp";
2325 #address-cells = <1>;
2326 #size-cells = <0>;
2328 compute-cb@1 {
2329 compatible = "qcom,fastrpc-compute-cb";
2334 compute-cb@2 {
2335 compatible = "qcom,fastrpc-compute-cb";
2340 compute-cb@3 {
2341 compatible = "qcom,fastrpc-compute-cb";
2344 /* note: shared-cb = <4> in downstream */
2351 compatible = "qcom,sm8450-lpass-wsa-macro";
2358 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2360 #clock-cells = <0>;
2361 clock-output-names = "wsa2-mclk";
2362 #sound-dai-cells = <1>;
2366 compatible = "qcom,soundwire-v1.7.0";
2370 clock-names = "iface";
2373 pinctrl-0 = <&wsa2_swr_active>;
2374 pinctrl-names = "default";
2376 qcom,din-ports = <2>;
2377 qcom,dout-ports = <6>;
2379 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2380 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2381 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2382 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2383 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2384 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2385 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2386 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2387 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2389 #address-cells = <2>;
2390 #size-cells = <0>;
2391 #sound-dai-cells = <1>;
2396 compatible = "qcom,sm8450-lpass-rx-macro";
2403 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2405 #clock-cells = <0>;
2406 clock-output-names = "mclk";
2407 #sound-dai-cells = <1>;
2411 compatible = "qcom,soundwire-v1.7.0";
2415 clock-names = "iface";
2417 qcom,din-ports = <0>;
2418 qcom,dout-ports = <5>;
2420 pinctrl-0 = <&rx_swr_active>;
2421 pinctrl-names = "default";
2423 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2424 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>;
2425 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2426 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2427 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2428 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2429 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2430 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2431 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2433 #address-cells = <2>;
2434 #size-cells = <0>;
2435 #sound-dai-cells = <1>;
2440 compatible = "qcom,sm8450-lpass-tx-macro";
2447 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2449 #clock-cells = <0>;
2450 clock-output-names = "mclk";
2451 #sound-dai-cells = <1>;
2455 compatible = "qcom,sm8450-lpass-wsa-macro";
2462 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2464 #clock-cells = <0>;
2465 clock-output-names = "mclk";
2466 #sound-dai-cells = <1>;
2470 compatible = "qcom,soundwire-v1.7.0";
2474 clock-names = "iface";
2477 pinctrl-0 = <&wsa_swr_active>;
2478 pinctrl-names = "default";
2480 qcom,din-ports = <2>;
2481 qcom,dout-ports = <6>;
2483 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2484 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2485 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2486 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2487 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2488 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2489 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2490 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2491 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2493 #address-cells = <2>;
2494 #size-cells = <0>;
2495 #sound-dai-cells = <1>;
2500 compatible = "qcom,soundwire-v1.7.0";
2504 interrupt-names = "core", "wakeup";
2507 clock-names = "iface";
2510 pinctrl-0 = <&tx_swr_active>;
2511 pinctrl-names = "default";
2513 qcom,din-ports = <4>;
2514 qcom,dout-ports = <0>;
2515 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
2516 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>;
2517 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
2518 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
2519 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
2520 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
2521 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
2522 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
2523 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>;
2525 #address-cells = <2>;
2526 #size-cells = <0>;
2527 #sound-dai-cells = <1>;
2532 compatible = "qcom,sm8450-lpass-va-macro";
2538 clock-names = "mclk", "macro", "dcodec", "npl";
2540 #clock-cells = <0>;
2541 clock-output-names = "fsgen";
2542 #sound-dai-cells = <1>;
2547 compatible = "qcom,sm8450-adsp-pas";
2550 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
2555 interrupt-names = "wdog", "fatal", "ready",
2556 "handover", "stop-ack";
2559 clock-names = "xo";
2561 power-domains = <&rpmhpd RPMHPD_LCX>,
2563 power-domain-names = "lcx", "lmx";
2565 memory-region = <&adsp_mem>;
2569 qcom,smem-states = <&smp2p_adsp_out 0>;
2570 qcom,smem-state-names = "stop";
2574 remoteproc_adsp_glink: glink-edge {
2575 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2582 qcom,remote-pid = <2>;
2586 qcom,glink-channels = "adsp_apps";
2589 #address-cells = <1>;
2590 #size-cells = <0>;
2595 #sound-dai-cells = <0>;
2596 qcom,protection-domain = "avs/audio",
2600 compatible = "qcom,q6apm-dais";
2605 compatible = "qcom,q6apm-lpass-dais";
2606 #sound-dai-cells = <1>;
2613 qcom,protection-domain = "avs/audio",
2616 q6prmcc: clock-controller {
2617 compatible = "qcom,q6prm-lpass-clocks";
2618 #clock-cells = <2>;
2625 qcom,glink-channels = "fastrpcglink-apps-dsp";
2627 #address-cells = <1>;
2628 #size-cells = <0>;
2630 compute-cb@3 {
2631 compatible = "qcom,fastrpc-compute-cb";
2636 compute-cb@4 {
2637 compatible = "qcom,fastrpc-compute-cb";
2642 compute-cb@5 {
2643 compatible = "qcom,fastrpc-compute-cb";
2652 compatible = "qcom,sm8450-cdsp-pas";
2655 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
2660 interrupt-names = "wdog", "fatal", "ready",
2661 "handover", "stop-ack";
2664 clock-names = "xo";
2666 power-domains = <&rpmhpd RPMHPD_CX>,
2668 power-domain-names = "cx", "mxc";
2670 memory-region = <&cdsp_mem>;
2674 qcom,smem-states = <&smp2p_cdsp_out 0>;
2675 qcom,smem-state-names = "stop";
2679 glink-edge {
2680 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
2687 qcom,remote-pid = <5>;
2691 qcom,glink-channels = "fastrpcglink-apps-dsp";
2693 #address-cells = <1>;
2694 #size-cells = <0>;
2696 compute-cb@1 {
2697 compatible = "qcom,fastrpc-compute-cb";
2703 compute-cb@2 {
2704 compatible = "qcom,fastrpc-compute-cb";
2710 compute-cb@3 {
2711 compatible = "qcom,fastrpc-compute-cb";
2717 compute-cb@4 {
2718 compatible = "qcom,fastrpc-compute-cb";
2724 compute-cb@5 {
2725 compatible = "qcom,fastrpc-compute-cb";
2731 compute-cb@6 {
2732 compatible = "qcom,fastrpc-compute-cb";
2738 compute-cb@7 {
2739 compatible = "qcom,fastrpc-compute-cb";
2745 compute-cb@8 {
2746 compatible = "qcom,fastrpc-compute-cb";
2758 compatible = "qcom,sm8450-mpss-pas";
2761 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
2767 interrupt-names = "wdog", "fatal", "ready", "handover",
2768 "stop-ack", "shutdown-ack";
2771 clock-names = "xo";
2773 power-domains = <&rpmhpd RPMHPD_CX>,
2775 power-domain-names = "cx", "mss";
2777 memory-region = <&mpss_mem>;
2781 qcom,smem-states = <&smp2p_modem_out 0>;
2782 qcom,smem-state-names = "stop";
2786 glink-edge {
2787 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2793 qcom,remote-pid = <1>;
2797 videocc: clock-controller@aaf0000 {
2798 compatible = "qcom,sm8450-videocc";
2802 power-domains = <&rpmhpd RPMHPD_MMCX>;
2803 required-opps = <&rpmhpd_opp_low_svs>;
2804 #clock-cells = <1>;
2805 #reset-cells = <1>;
2806 #power-domain-cells = <1>;
2810 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci";
2813 power-domains = <&camcc TITAN_TOP_GDSC>;
2820 clock-names = "camnoc_axi",
2825 pinctrl-0 = <&cci0_default &cci1_default>;
2826 pinctrl-1 = <&cci0_sleep &cci1_sleep>;
2827 pinctrl-names = "default", "sleep";
2830 #address-cells = <1>;
2831 #size-cells = <0>;
2833 cci0_i2c0: i2c-bus@0 {
2835 clock-frequency = <1000000>;
2836 #address-cells = <1>;
2837 #size-cells = <0>;
2840 cci0_i2c1: i2c-bus@1 {
2842 clock-frequency = <1000000>;
2843 #address-cells = <1>;
2844 #size-cells = <0>;
2849 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci";
2852 power-domains = <&camcc TITAN_TOP_GDSC>;
2859 clock-names = "camnoc_axi",
2864 pinctrl-0 = <&cci2_default &cci3_default>;
2865 pinctrl-1 = <&cci2_sleep &cci3_sleep>;
2866 pinctrl-names = "default", "sleep";
2869 #address-cells = <1>;
2870 #size-cells = <0>;
2872 cci1_i2c0: i2c-bus@0 {
2874 clock-frequency = <1000000>;
2875 #address-cells = <1>;
2876 #size-cells = <0>;
2879 cci1_i2c1: i2c-bus@1 {
2881 clock-frequency = <1000000>;
2882 #address-cells = <1>;
2883 #size-cells = <0>;
2887 camcc: clock-controller@ade0000 {
2888 compatible = "qcom,sm8450-camcc";
2894 power-domains = <&rpmhpd RPMHPD_MMCX>;
2895 required-opps = <&rpmhpd_opp_low_svs>;
2896 #clock-cells = <1>;
2897 #reset-cells = <1>;
2898 #power-domain-cells = <1>;
2902 mdss: display-subsystem@ae00000 {
2903 compatible = "qcom,sm8450-mdss";
2905 reg-names = "mdss";
2912 interconnect-names = "mdp0-mem",
2913 "mdp1-mem",
2914 "cpu-cfg";
2918 power-domains = <&dispcc MDSS_GDSC>;
2926 interrupt-controller;
2927 #interrupt-cells = <1>;
2931 #address-cells = <2>;
2932 #size-cells = <2>;
2937 mdss_mdp: display-controller@ae01000 {
2938 compatible = "qcom,sm8450-dpu";
2941 reg-names = "mdp", "vbif";
2949 clock-names = "bus",
2956 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2957 assigned-clock-rates = <19200000>;
2959 operating-points-v2 = <&mdp_opp_table>;
2960 power-domains = <&rpmhpd RPMHPD_MMCX>;
2962 interrupt-parent = <&mdss>;
2966 #address-cells = <1>;
2967 #size-cells = <0>;
2972 remote-endpoint = <&mdss_dsi0_in>;
2979 remote-endpoint = <&mdss_dsi1_in>;
2986 remote-endpoint = <&mdss_dp0_in>;
2991 mdp_opp_table: opp-table {
2992 compatible = "operating-points-v2";
2994 opp-172000000 {
2995 opp-hz = /bits/ 64 <172000000>;
2996 required-opps = <&rpmhpd_opp_low_svs_d1>;
2999 opp-200000000 {
3000 opp-hz = /bits/ 64 <200000000>;
3001 required-opps = <&rpmhpd_opp_low_svs>;
3004 opp-325000000 {
3005 opp-hz = /bits/ 64 <325000000>;
3006 required-opps = <&rpmhpd_opp_svs>;
3009 opp-375000000 {
3010 opp-hz = /bits/ 64 <375000000>;
3011 required-opps = <&rpmhpd_opp_svs_l1>;
3014 opp-500000000 {
3015 opp-hz = /bits/ 64 <500000000>;
3016 required-opps = <&rpmhpd_opp_nom>;
3021 mdss_dp0: displayport-controller@ae90000 {
3022 compatible = "qcom,sm8450-dp", "qcom,sm8350-dp";
3028 interrupt-parent = <&mdss>;
3035 clock-names = "core_iface",
3041 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
3043 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3047 phy-names = "dp";
3049 #sound-dai-cells = <0>;
3051 operating-points-v2 = <&dp_opp_table>;
3052 power-domains = <&rpmhpd RPMHPD_MMCX>;
3057 #address-cells = <1>;
3058 #size-cells = <0>;
3063 remote-endpoint = <&dpu_intf0_out>;
3068 dp_opp_table: opp-table {
3069 compatible = "operating-points-v2";
3071 opp-160000000 {
3072 opp-hz = /bits/ 64 <160000000>;
3073 required-opps = <&rpmhpd_opp_low_svs>;
3076 opp-270000000 {
3077 opp-hz = /bits/ 64 <270000000>;
3078 required-opps = <&rpmhpd_opp_svs>;
3081 opp-540000000 {
3082 opp-hz = /bits/ 64 <540000000>;
3083 required-opps = <&rpmhpd_opp_svs_l1>;
3086 opp-810000000 {
3087 opp-hz = /bits/ 64 <810000000>;
3088 required-opps = <&rpmhpd_opp_nom>;
3094 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3096 reg-names = "dsi_ctrl";
3098 interrupt-parent = <&mdss>;
3107 clock-names = "byte",
3114 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
3115 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
3117 operating-points-v2 = <&mdss_dsi_opp_table>;
3118 power-domains = <&rpmhpd RPMHPD_MMCX>;
3121 phy-names = "dsi";
3123 #address-cells = <1>;
3124 #size-cells = <0>;
3129 #address-cells = <1>;
3130 #size-cells = <0>;
3135 remote-endpoint = <&dpu_intf1_out>;
3146 mdss_dsi_opp_table: opp-table {
3147 compatible = "operating-points-v2";
3149 opp-187500000 {
3150 opp-hz = /bits/ 64 <187500000>;
3151 required-opps = <&rpmhpd_opp_low_svs>;
3154 opp-300000000 {
3155 opp-hz = /bits/ 64 <300000000>;
3156 required-opps = <&rpmhpd_opp_svs>;
3159 opp-358000000 {
3160 opp-hz = /bits/ 64 <358000000>;
3161 required-opps = <&rpmhpd_opp_svs_l1>;
3167 compatible = "qcom,sm8450-dsi-phy-5nm";
3171 reg-names = "dsi_phy",
3175 #clock-cells = <1>;
3176 #phy-cells = <0>;
3180 clock-names = "iface", "ref";
3186 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3188 reg-names = "dsi_ctrl";
3190 interrupt-parent = <&mdss>;
3199 clock-names = "byte",
3206 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
3207 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
3209 operating-points-v2 = <&mdss_dsi_opp_table>;
3210 power-domains = <&rpmhpd RPMHPD_MMCX>;
3213 phy-names = "dsi";
3215 #address-cells = <1>;
3216 #size-cells = <0>;
3221 #address-cells = <1>;
3222 #size-cells = <0>;
3227 remote-endpoint = <&dpu_intf2_out>;
3240 compatible = "qcom,sm8450-dsi-phy-5nm";
3244 reg-names = "dsi_phy",
3248 #clock-cells = <1>;
3249 #phy-cells = <0>;
3253 clock-names = "iface", "ref";
3259 dispcc: clock-controller@af00000 {
3260 compatible = "qcom,sm8450-dispcc";
3278 power-domains = <&rpmhpd RPMHPD_MMCX>;
3279 required-opps = <&rpmhpd_opp_low_svs>;
3280 #clock-cells = <1>;
3281 #reset-cells = <1>;
3282 #power-domain-cells = <1>;
3286 pdc: interrupt-controller@b220000 {
3287 compatible = "qcom,sm8450-pdc", "qcom,pdc";
3289 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>,
3291 #interrupt-cells = <2>;
3292 interrupt-parent = <&intc>;
3293 interrupt-controller;
3296 tsens0: thermal-sensor@c263000 {
3297 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2";
3303 interrupt-names = "uplow", "critical";
3304 #thermal-sensor-cells = <1>;
3307 tsens1: thermal-sensor@c265000 {
3308 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2";
3314 interrupt-names = "uplow", "critical";
3315 #thermal-sensor-cells = <1>;
3318 aoss_qmp: power-management@c300000 {
3319 compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp";
3321 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
3325 #clock-cells = <0>;
3329 compatible = "qcom,rpmh-stats";
3334 compatible = "qcom,spmi-pmic-arb";
3340 reg-names = "core",
3345 interrupt-names = "periph_irq";
3346 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3349 interrupt-controller;
3350 #interrupt-cells = <4>;
3351 #address-cells = <2>;
3352 #size-cells = <0>;
3356 compatible = "qcom,sm8450-ipcc", "qcom,ipcc";
3359 interrupt-controller;
3360 #interrupt-cells = <3>;
3361 #mbox-cells = <2>;
3365 compatible = "qcom,sm8450-tlmm";
3368 gpio-controller;
3369 #gpio-cells = <2>;
3370 interrupt-controller;
3371 #interrupt-cells = <2>;
3372 gpio-ranges = <&tlmm 0 0 211>;
3373 wakeup-parent = <&pdc>;
3375 sdc2_default_state: sdc2-default-state {
3376 clk-pins {
3378 drive-strength = <16>;
3379 bias-disable;
3382 cmd-pins {
3384 drive-strength = <16>;
3385 bias-pull-up;
3388 data-pins {
3390 drive-strength = <16>;
3391 bias-pull-up;
3395 sdc2_sleep_state: sdc2-sleep-state {
3396 clk-pins {
3398 drive-strength = <2>;
3399 bias-disable;
3402 cmd-pins {
3404 drive-strength = <2>;
3405 bias-pull-up;
3408 data-pins {
3410 drive-strength = <2>;
3411 bias-pull-up;
3415 cci0_default: cci0-default-state {
3419 drive-strength = <2>;
3420 bias-pull-up;
3423 cci0_sleep: cci0-sleep-state {
3427 drive-strength = <2>;
3428 bias-pull-down;
3431 cci1_default: cci1-default-state {
3435 drive-strength = <2>;
3436 bias-pull-up;
3439 cci1_sleep: cci1-sleep-state {
3443 drive-strength = <2>;
3444 bias-pull-down;
3447 cci2_default: cci2-default-state {
3451 drive-strength = <2>;
3452 bias-pull-up;
3455 cci2_sleep: cci2-sleep-state {
3459 drive-strength = <2>;
3460 bias-pull-down;
3463 cci3_default: cci3-default-state {
3467 drive-strength = <2>;
3468 bias-pull-up;
3471 cci3_sleep: cci3-sleep-state {
3475 drive-strength = <2>;
3476 bias-pull-down;
3479 pcie0_default_state: pcie0-default-state {
3480 perst-pins {
3483 drive-strength = <2>;
3484 bias-pull-down;
3487 clkreq-pins {
3490 drive-strength = <2>;
3491 bias-pull-up;
3494 wake-pins {
3497 drive-strength = <2>;
3498 bias-pull-up;
3502 pcie1_default_state: pcie1-default-state {
3503 perst-pins {
3506 drive-strength = <2>;
3507 bias-pull-down;
3510 clkreq-pins {
3513 drive-strength = <2>;
3514 bias-pull-up;
3517 wake-pins {
3520 drive-strength = <2>;
3521 bias-pull-up;
3525 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
3530 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
3535 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
3540 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
3545 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
3550 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
3555 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
3560 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
3565 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
3570 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
3575 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
3580 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
3585 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
3588 drive-strength = <2>;
3589 bias-pull-up;
3592 qup_i2c14_data_clk: qup-i2c14-data-clk-state {
3595 drive-strength = <2>;
3596 bias-pull-up;
3599 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
3604 qup_i2c16_data_clk: qup-i2c16-data-clk-state {
3609 qup_i2c17_data_clk: qup-i2c17-data-clk-state {
3614 qup_i2c18_data_clk: qup-i2c18-data-clk-state {
3619 qup_i2c19_data_clk: qup-i2c19-data-clk-state {
3624 qup_i2c20_data_clk: qup-i2c20-data-clk-state {
3629 qup_i2c21_data_clk: qup-i2c21-data-clk-state {
3634 qup_spi0_cs: qup-spi0-cs-state {
3639 qup_spi0_data_clk: qup-spi0-data-clk-state {
3644 qup_spi1_cs: qup-spi1-cs-state {
3649 qup_spi1_data_clk: qup-spi1-data-clk-state {
3654 qup_spi2_cs: qup-spi2-cs-state {
3659 qup_spi2_data_clk: qup-spi2-data-clk-state {
3664 qup_spi3_cs: qup-spi3-cs-state {
3669 qup_spi3_data_clk: qup-spi3-data-clk-state {
3674 qup_spi4_cs: qup-spi4-cs-state {
3677 drive-strength = <6>;
3678 bias-disable;
3681 qup_spi4_data_clk: qup-spi4-data-clk-state {
3686 qup_spi5_cs: qup-spi5-cs-state {
3691 qup_spi5_data_clk: qup-spi5-data-clk-state {
3696 qup_spi6_cs: qup-spi6-cs-state {
3701 qup_spi6_data_clk: qup-spi6-data-clk-state {
3706 qup_spi8_cs: qup-spi8-cs-state {
3711 qup_spi8_data_clk: qup-spi8-data-clk-state {
3716 qup_spi9_cs: qup-spi9-cs-state {
3721 qup_spi9_data_clk: qup-spi9-data-clk-state {
3726 qup_spi10_cs: qup-spi10-cs-state {
3731 qup_spi10_data_clk: qup-spi10-data-clk-state {
3736 qup_spi11_cs: qup-spi11-cs-state {
3741 qup_spi11_data_clk: qup-spi11-data-clk-state {
3746 qup_spi12_cs: qup-spi12-cs-state {
3751 qup_spi12_data_clk: qup-spi12-data-clk-state {
3756 qup_spi13_cs: qup-spi13-cs-state {
3761 qup_spi13_data_clk: qup-spi13-data-clk-state {
3766 qup_spi14_cs: qup-spi14-cs-state {
3771 qup_spi14_data_clk: qup-spi14-data-clk-state {
3776 qup_spi15_cs: qup-spi15-cs-state {
3781 qup_spi15_data_clk: qup-spi15-data-clk-state {
3786 qup_spi16_cs: qup-spi16-cs-state {
3791 qup_spi16_data_clk: qup-spi16-data-clk-state {
3796 qup_spi17_cs: qup-spi17-cs-state {
3801 qup_spi17_data_clk: qup-spi17-data-clk-state {
3806 qup_spi18_cs: qup-spi18-cs-state {
3809 drive-strength = <6>;
3810 bias-disable;
3813 qup_spi18_data_clk: qup-spi18-data-clk-state {
3816 drive-strength = <6>;
3817 bias-disable;
3820 qup_spi19_cs: qup-spi19-cs-state {
3823 drive-strength = <6>;
3824 bias-disable;
3827 qup_spi19_data_clk: qup-spi19-data-clk-state {
3830 drive-strength = <6>;
3831 bias-disable;
3834 qup_spi20_cs: qup-spi20-cs-state {
3839 qup_spi20_data_clk: qup-spi20-data-clk-state {
3844 qup_spi21_cs: qup-spi21-cs-state {
3849 qup_spi21_data_clk: qup-spi21-data-clk-state {
3854 qup_uart7_rx: qup-uart7-rx-state {
3857 drive-strength = <2>;
3858 bias-disable;
3861 qup_uart7_tx: qup-uart7-tx-state {
3864 drive-strength = <2>;
3865 bias-disable;
3868 qup_uart20_default: qup-uart20-default-state {
3875 compatible = "qcom,sm8450-lpass-lpi-pinctrl";
3878 gpio-controller;
3879 #gpio-cells = <2>;
3880 gpio-ranges = <&lpass_tlmm 0 0 23>;
3884 clock-names = "core", "audio";
3886 tx_swr_active: tx-swr-active-state {
3887 clk-pins {
3890 drive-strength = <2>;
3891 slew-rate = <1>;
3892 bias-disable;
3895 data-pins {
3898 drive-strength = <2>;
3899 slew-rate = <1>;
3900 bias-bus-hold;
3904 rx_swr_active: rx-swr-active-state {
3905 clk-pins {
3908 drive-strength = <2>;
3909 slew-rate = <1>;
3910 bias-disable;
3913 data-pins {
3916 drive-strength = <2>;
3917 slew-rate = <1>;
3918 bias-bus-hold;
3922 dmic01_default: dmic01-default-state {
3923 clk-pins {
3926 drive-strength = <8>;
3927 output-high;
3930 data-pins {
3933 drive-strength = <8>;
3937 dmic02_default: dmic02-default-state {
3938 clk-pins {
3941 drive-strength = <8>;
3942 output-high;
3945 data-pins {
3948 drive-strength = <8>;
3952 wsa_swr_active: wsa-swr-active-state {
3953 clk-pins {
3956 drive-strength = <2>;
3957 slew-rate = <1>;
3958 bias-disable;
3961 data-pins {
3964 drive-strength = <2>;
3965 slew-rate = <1>;
3966 bias-bus-hold;
3970 wsa2_swr_active: wsa2-swr-active-state {
3971 clk-pins {
3974 drive-strength = <2>;
3975 slew-rate = <1>;
3976 bias-disable;
3979 data-pins {
3982 drive-strength = <2>;
3983 slew-rate = <1>;
3984 bias-bus-hold;
3990 compatible = "qcom,sm8450-imem", "syscon", "simple-mfd";
3994 #address-cells = <1>;
3995 #size-cells = <1>;
3997 pil-reloc@94c {
3998 compatible = "qcom,pil-reloc-info";
4004 compatible = "qcom,sm8450-smmu-500", "arm,mmu-500";
4006 #iommu-cells = <2>;
4007 #global-interrupts = <1>;
4107 intc: interrupt-controller@17100000 {
4108 compatible = "arm,gic-v3";
4109 #interrupt-cells = <3>;
4110 interrupt-controller;
4111 #redistributor-regions = <1>;
4112 redistributor-stride = <0x0 0x40000>;
4116 #address-cells = <2>;
4117 #size-cells = <2>;
4120 gic_its: msi-controller@17140000 {
4121 compatible = "arm,gic-v3-its";
4123 msi-controller;
4124 #msi-cells = <1>;
4129 compatible = "arm,armv7-timer-mem";
4130 #address-cells = <1>;
4131 #size-cells = <1>;
4134 clock-frequency = <19200000>;
4137 frame-number = <0>;
4145 frame-number = <1>;
4152 frame-number = <2>;
4159 frame-number = <3>;
4166 frame-number = <4>;
4173 frame-number = <5>;
4180 frame-number = <6>;
4189 compatible = "qcom,rpmh-rsc";
4194 reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
4198 qcom,tcs-offset = <0xd00>;
4199 qcom,drv-id = <2>;
4200 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
4202 power-domains = <&CLUSTER_PD>;
4204 apps_bcm_voter: bcm-voter {
4205 compatible = "qcom,bcm-voter";
4208 rpmhcc: clock-controller {
4209 compatible = "qcom,sm8450-rpmh-clk";
4210 #clock-cells = <1>;
4211 clock-names = "xo";
4215 rpmhpd: power-controller {
4216 compatible = "qcom,sm8450-rpmhpd";
4217 #power-domain-cells = <1>;
4218 operating-points-v2 = <&rpmhpd_opp_table>;
4220 rpmhpd_opp_table: opp-table {
4221 compatible = "operating-points-v2";
4224 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4228 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4232 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
4236 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4240 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
4244 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4248 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
4252 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4256 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
4260 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4264 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4268 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4272 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4276 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4283 compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss";
4287 reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
4289 clock-names = "xo", "alternate";
4293 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
4294 #freq-domain-cells = <1>;
4295 #clock-cells = <1>;
4299 compatible = "qcom,sm8450-gem-noc";
4301 #interconnect-cells = <2>;
4302 qcom,bcm-voters = <&apps_bcm_voter>;
4305 system-cache-controller@19200000 {
4306 compatible = "qcom,sm8450-llcc";
4310 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
4316 compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
4317 "jedec,ufs-2.0";
4321 phy-names = "ufsphy";
4322 lanes-per-direction = <2>;
4323 #reset-cells = <1>;
4325 reset-names = "rst";
4327 power-domains = <&gcc UFS_PHY_GDSC>;
4330 dma-coherent;
4334 interconnect-names = "ufs-ddr", "cpu-ufs";
4335 clock-names =
4353 freq-table-hz =
4368 compatible = "qcom,sm8450-qmp-ufs-phy";
4371 clock-names = "ref", "ref_aux", "qref";
4377 reset-names = "ufsphy";
4379 #clock-cells = <1>;
4380 #phy-cells = <0>;
4386 compatible = "qcom,sm8450-inline-crypto-engine",
4387 "qcom,inline-crypto-engine";
4392 cryptobam: dma-controller@1dc4000 {
4393 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
4396 #dma-cells = <1>;
4398 qcom,controlled-remotely;
4407 compatible = "qcom,sm8450-qce", "qcom,sm8150-qce", "qcom,qce";
4410 dma-names = "rx", "tx";
4417 interconnect-names = "memory";
4421 compatible = "qcom,sm8450-sdhci", "qcom,sdhci-msm-v5";
4426 interrupt-names = "hc_irq", "pwr_irq";
4431 clock-names = "iface", "core", "xo";
4435 interconnect-names = "sdhc-ddr","cpu-sdhc";
4437 power-domains = <&rpmhpd RPMHPD_CX>;
4438 operating-points-v2 = <&sdhc2_opp_table>;
4439 bus-width = <4>;
4440 dma-coherent;
4442 /* Forbid SDR104/SDR50 - broken hw! */
4443 sdhci-caps-mask = <0x3 0x0>;
4447 sdhc2_opp_table: opp-table {
4448 compatible = "operating-points-v2";
4450 opp-100000000 {
4451 opp-hz = /bits/ 64 <100000000>;
4452 required-opps = <&rpmhpd_opp_low_svs>;
4455 opp-202000000 {
4456 opp-hz = /bits/ 64 <202000000>;
4457 required-opps = <&rpmhpd_opp_svs_l1>;
4463 compatible = "qcom,sm8450-dwc3", "qcom,dwc3";
4466 #address-cells = <2>;
4467 #size-cells = <2>;
4476 clock-names = "cfg_noc",
4483 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4485 assigned-clock-rates = <19200000>, <200000000>;
4487 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
4491 interrupt-names = "hs_phy_irq",
4496 power-domains = <&gcc USB30_PRIM_GDSC>;
4502 interconnect-names = "usb-ddr", "apps-usb";
4512 phy-names = "usb2-phy", "usb3-phy";
4515 #address-cells = <1>;
4516 #size-cells = <0>;
4536 compatible = "qcom,sm8450-nsp-noc";
4538 #interconnect-cells = <2>;
4539 qcom,bcm-voters = <&apps_bcm_voter>;
4543 compatible = "qcom,sm8450-lpass-ag-noc";
4545 #interconnect-cells = <2>;
4546 qcom,bcm-voters = <&apps_bcm_voter>;
4553 thermal-zones {
4554 aoss0-thermal {
4555 polling-delay-passive = <0>;
4556 polling-delay = <0>;
4557 thermal-sensors = <&tsens0 0>;
4560 thermal-engine-config {
4566 reset-mon-cfg {
4574 cpuss0-thermal {
4575 polling-delay-passive = <0>;
4576 polling-delay = <0>;
4577 thermal-sensors = <&tsens0 1>;
4580 thermal-engine-config {
4586 reset-mon-cfg {
4594 cpuss1-thermal {
4595 polling-delay-passive = <0>;
4596 polling-delay = <0>;
4597 thermal-sensors = <&tsens0 2>;
4600 thermal-engine-config {
4606 reset-mon-cfg {
4614 cpuss3-thermal {
4615 polling-delay-passive = <0>;
4616 polling-delay = <0>;
4617 thermal-sensors = <&tsens0 3>;
4620 thermal-engine-config {
4626 reset-mon-cfg {
4634 cpuss4-thermal {
4635 polling-delay-passive = <0>;
4636 polling-delay = <0>;
4637 thermal-sensors = <&tsens0 4>;
4640 thermal-engine-config {
4646 reset-mon-cfg {
4654 cpu4-top-thermal {
4655 polling-delay-passive = <0>;
4656 polling-delay = <0>;
4657 thermal-sensors = <&tsens0 5>;
4660 cpu4_top_alert0: trip-point0 {
4666 cpu4_top_alert1: trip-point1 {
4672 cpu4_top_crit: cpu-crit {
4680 cpu4-bottom-thermal {
4681 polling-delay-passive = <0>;
4682 polling-delay = <0>;
4683 thermal-sensors = <&tsens0 6>;
4686 cpu4_bottom_alert0: trip-point0 {
4692 cpu4_bottom_alert1: trip-point1 {
4698 cpu4_bottom_crit: cpu-crit {
4706 cpu5-top-thermal {
4707 polling-delay-passive = <0>;
4708 polling-delay = <0>;
4709 thermal-sensors = <&tsens0 7>;
4712 cpu5_top_alert0: trip-point0 {
4718 cpu5_top_alert1: trip-point1 {
4724 cpu5_top_crit: cpu-crit {
4732 cpu5-bottom-thermal {
4733 polling-delay-passive = <0>;
4734 polling-delay = <0>;
4735 thermal-sensors = <&tsens0 8>;
4738 cpu5_bottom_alert0: trip-point0 {
4744 cpu5_bottom_alert1: trip-point1 {
4750 cpu5_bottom_crit: cpu-crit {
4758 cpu6-top-thermal {
4759 polling-delay-passive = <0>;
4760 polling-delay = <0>;
4761 thermal-sensors = <&tsens0 9>;
4764 cpu6_top_alert0: trip-point0 {
4770 cpu6_top_alert1: trip-point1 {
4776 cpu6_top_crit: cpu-crit {
4784 cpu6-bottom-thermal {
4785 polling-delay-passive = <0>;
4786 polling-delay = <0>;
4787 thermal-sensors = <&tsens0 10>;
4790 cpu6_bottom_alert0: trip-point0 {
4796 cpu6_bottom_alert1: trip-point1 {
4802 cpu6_bottom_crit: cpu-crit {
4810 cpu7-top-thermal {
4811 polling-delay-passive = <0>;
4812 polling-delay = <0>;
4813 thermal-sensors = <&tsens0 11>;
4816 cpu7_top_alert0: trip-point0 {
4822 cpu7_top_alert1: trip-point1 {
4828 cpu7_top_crit: cpu-crit {
4836 cpu7-middle-thermal {
4837 polling-delay-passive = <0>;
4838 polling-delay = <0>;
4839 thermal-sensors = <&tsens0 12>;
4842 cpu7_middle_alert0: trip-point0 {
4848 cpu7_middle_alert1: trip-point1 {
4854 cpu7_middle_crit: cpu-crit {
4862 cpu7-bottom-thermal {
4863 polling-delay-passive = <0>;
4864 polling-delay = <0>;
4865 thermal-sensors = <&tsens0 13>;
4868 cpu7_bottom_alert0: trip-point0 {
4874 cpu7_bottom_alert1: trip-point1 {
4880 cpu7_bottom_crit: cpu-crit {
4888 gpu-top-thermal {
4889 polling-delay-passive = <10>;
4890 polling-delay = <0>;
4891 thermal-sensors = <&tsens0 14>;
4894 thermal-engine-config {
4900 thermal-hal-config {
4906 reset-mon-cfg {
4912 gpu0_tj_cfg: tj-cfg {
4920 gpu-bottom-thermal {
4921 polling-delay-passive = <10>;
4922 polling-delay = <0>;
4923 thermal-sensors = <&tsens0 15>;
4926 thermal-engine-config {
4932 thermal-hal-config {
4938 reset-mon-cfg {
4944 gpu1_tj_cfg: tj-cfg {
4952 aoss1-thermal {
4953 polling-delay-passive = <0>;
4954 polling-delay = <0>;
4955 thermal-sensors = <&tsens1 0>;
4958 thermal-engine-config {
4964 reset-mon-cfg {
4972 cpu0-thermal {
4973 polling-delay-passive = <0>;
4974 polling-delay = <0>;
4975 thermal-sensors = <&tsens1 1>;
4978 cpu0_alert0: trip-point0 {
4984 cpu0_alert1: trip-point1 {
4990 cpu0_crit: cpu-crit {
4998 cpu1-thermal {
4999 polling-delay-passive = <0>;
5000 polling-delay = <0>;
5001 thermal-sensors = <&tsens1 2>;
5004 cpu1_alert0: trip-point0 {
5010 cpu1_alert1: trip-point1 {
5016 cpu1_crit: cpu-crit {
5024 cpu2-thermal {
5025 polling-delay-passive = <0>;
5026 polling-delay = <0>;
5027 thermal-sensors = <&tsens1 3>;
5030 cpu2_alert0: trip-point0 {
5036 cpu2_alert1: trip-point1 {
5042 cpu2_crit: cpu-crit {
5050 cpu3-thermal {
5051 polling-delay-passive = <0>;
5052 polling-delay = <0>;
5053 thermal-sensors = <&tsens1 4>;
5056 cpu3_alert0: trip-point0 {
5062 cpu3_alert1: trip-point1 {
5068 cpu3_crit: cpu-crit {
5076 cdsp0-thermal {
5077 polling-delay-passive = <10>;
5078 polling-delay = <0>;
5079 thermal-sensors = <&tsens1 5>;
5082 thermal-engine-config {
5088 thermal-hal-config {
5094 reset-mon-cfg {
5100 cdsp_0_config: junction-config {
5108 cdsp1-thermal {
5109 polling-delay-passive = <10>;
5110 polling-delay = <0>;
5111 thermal-sensors = <&tsens1 6>;
5114 thermal-engine-config {
5120 thermal-hal-config {
5126 reset-mon-cfg {
5132 cdsp_1_config: junction-config {
5140 cdsp2-thermal {
5141 polling-delay-passive = <10>;
5142 polling-delay = <0>;
5143 thermal-sensors = <&tsens1 7>;
5146 thermal-engine-config {
5152 thermal-hal-config {
5158 reset-mon-cfg {
5164 cdsp_2_config: junction-config {
5172 video-thermal {
5173 polling-delay-passive = <0>;
5174 polling-delay = <0>;
5175 thermal-sensors = <&tsens1 8>;
5178 thermal-engine-config {
5184 reset-mon-cfg {
5192 mem-thermal {
5193 polling-delay-passive = <10>;
5194 polling-delay = <0>;
5195 thermal-sensors = <&tsens1 9>;
5198 thermal-engine-config {
5204 ddr_config0: ddr0-config {
5210 reset-mon-cfg {
5218 modem0-thermal {
5219 polling-delay-passive = <0>;
5220 polling-delay = <0>;
5221 thermal-sensors = <&tsens1 10>;
5224 thermal-engine-config {
5230 mdmss0_config0: mdmss0-config0 {
5236 mdmss0_config1: mdmss0-config1 {
5242 reset-mon-cfg {
5250 modem1-thermal {
5251 polling-delay-passive = <0>;
5252 polling-delay = <0>;
5253 thermal-sensors = <&tsens1 11>;
5256 thermal-engine-config {
5262 mdmss1_config0: mdmss1-config0 {
5268 mdmss1_config1: mdmss1-config1 {
5274 reset-mon-cfg {
5282 modem2-thermal {
5283 polling-delay-passive = <0>;
5284 polling-delay = <0>;
5285 thermal-sensors = <&tsens1 12>;
5288 thermal-engine-config {
5294 mdmss2_config0: mdmss2-config0 {
5300 mdmss2_config1: mdmss2-config1 {
5306 reset-mon-cfg {
5314 modem3-thermal {
5315 polling-delay-passive = <0>;
5316 polling-delay = <0>;
5317 thermal-sensors = <&tsens1 13>;
5320 thermal-engine-config {
5326 mdmss3_config0: mdmss3-config0 {
5332 mdmss3_config1: mdmss3-config1 {
5338 reset-mon-cfg {
5346 camera0-thermal {
5347 polling-delay-passive = <0>;
5348 polling-delay = <0>;
5349 thermal-sensors = <&tsens1 14>;
5352 thermal-engine-config {
5358 reset-mon-cfg {
5366 camera1-thermal {
5367 polling-delay-passive = <0>;
5368 polling-delay = <0>;
5369 thermal-sensors = <&tsens1 15>;
5372 thermal-engine-config {
5378 reset-mon-cfg {
5388 compatible = "arm,armv8-timer";
5393 clock-frequency = <19200000>;