Lines Matching +full:0 +full:x0aaf0000
39 #clock-cells = <0>;
45 #clock-cells = <0>;
52 #size-cells = <0>;
54 CPU0: cpu@0 {
57 reg = <0x0 0x0>;
62 qcom,freq-domain = <&cpufreq_hw 0>;
64 clocks = <&cpufreq_hw 0>;
81 reg = <0x0 0x100>;
86 qcom,freq-domain = <&cpufreq_hw 0>;
88 clocks = <&cpufreq_hw 0>;
100 reg = <0x0 0x200>;
105 qcom,freq-domain = <&cpufreq_hw 0>;
107 clocks = <&cpufreq_hw 0>;
119 reg = <0x0 0x300>;
124 qcom,freq-domain = <&cpufreq_hw 0>;
126 clocks = <&cpufreq_hw 0>;
138 reg = <0x0 0x400>;
157 reg = <0x0 0x500>;
176 reg = <0x0 0x600>;
195 reg = <0x0 0x700>;
250 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
253 arm,psci-suspend-param = <0x40000004>;
260 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
263 arm,psci-suspend-param = <0x40000004>;
272 CLUSTER_SLEEP_0: cluster-sleep-0 {
274 arm,psci-suspend-param = <0x41000044>;
282 arm,psci-suspend-param = <0x4100c344>;
293 qcom,dload-mode = <&tcsr 0x13000>;
294 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
299 clk_virt: interconnect-0 {
314 reg = <0x0 0xa0000000 0x0 0x0>;
327 #power-domain-cells = <0>;
333 #power-domain-cells = <0>;
339 #power-domain-cells = <0>;
345 #power-domain-cells = <0>;
351 #power-domain-cells = <0>;
357 #power-domain-cells = <0>;
363 #power-domain-cells = <0>;
369 #power-domain-cells = <0>;
375 #power-domain-cells = <0>;
405 reg = <0x0 0x80000000 0x0 0x600000>;
410 reg = <0x0 0x80600000 0x0 0x40000>;
415 reg = <0x0 0x80640000 0x0 0x180000>;
420 reg = <0x0 0x807c0000 0x0 0x40000>;
425 reg = <0x0 0x80800000 0x0 0x60000>;
431 reg = <0x0 0x80860000 0x0 0x20000>;
436 reg = <0x0 0x80880000 0x0 0x20000>;
441 reg = <0x0 0x808a0000 0x0 0x40000>;
446 reg = <0x0 0x808e0000 0x0 0x4000>;
451 reg = <0x0 0x808e4000 0x0 0x10000>;
458 reg = <0x0 0x80900000 0x0 0x200000>;
464 reg = <0x0 0x80b00000 0x0 0x100000>;
469 reg = <0x0 0x80c00000 0x0 0x4600000>;
474 reg = <0x0 0x85700000 0x0 0x700000>;
479 reg = <0x0 0x85e00000 0x0 0x2100000>;
484 reg = <0x0 0x88000000 0x0 0x1900000>;
489 reg = <0x0 0x89900000 0x0 0x2000000>;
494 reg = <0x0 0x8b900000 0x0 0x10000>;
499 reg = <0x0 0x8b910000 0x0 0xa000>;
504 reg = <0x0 0x8b91a000 0x0 0x2000>;
509 reg = <0x0 0x8ba00000 0x0 0x180000>;
515 reg = <0x0 0x8bb80000 0x0 0x60000>;
521 reg = <0x0 0x8bbe0000 0x0 0x20000>;
526 reg = <0x0 0x8bc00000 0x0 0x13200000>;
531 reg = <0x0 0x9ee00000 0x0 0x700000>;
536 reg = <0x0 0x9f500000 0x0 0x800000>;
542 reg = <0x0 0x9fd00000 0x0 0x280000>;
550 reg = <0x0 0xa6e00000 0x0 0x40000>;
555 reg = <0x0 0xa6f00000 0x0 0x100000>;
561 /* Linux kernel image is loaded at 0xa0000000 */
564 reg = <0x0 0xbb000000 0x0 0x5000000>;
569 reg = <0x0 0xc0000000 0x0 0x20000000>;
574 reg = <0x0 0xe0000000 0x0 0x600000>;
579 reg = <0x0 0xe0600000 0x0 0x400000>;
584 reg = <0x0 0xe0a00000 0x0 0x100000>;
589 reg = <0x0 0xe0b00000 0x0 0x4af3000>;
594 reg = <0x0 0xe55f3000 0x0 0x9000>;
599 reg = <0x0 0xe55fc000 0x0 0x4000>;
604 reg = <0x0 0xe5600000 0x0 0x100000>;
609 reg = <0x0 0xe8800000 0x0 0x100000>;
614 reg = <0x0 0xe8900000 0x0 0x1200000>;
619 reg = <0x0 0xe9b00000 0x0 0x500000>;
624 reg = <0x0 0xea000000 0x0 0x3900000>;
629 reg = <0x0 0xed900000 0x0 0x3b00000>;
643 qcom,local-pid = <0>;
667 qcom,local-pid = <0>;
691 qcom,local-pid = <0>;
726 qcom,local-pid = <0>;
741 soc: soc@0 {
744 ranges = <0 0 0 0 0x10 0>;
745 dma-ranges = <0 0 0 0 0x10 0>;
750 reg = <0x0 0x00100000 0x0 0x1f4200>;
758 <0>,
759 <&ufs_mem_phy 0>,
777 reg = <0 0x00800000 0 0x60000>;
791 dma-channel-mask = <0x7e>;
792 iommus = <&apps_smmu 0x496 0x0>;
798 reg = <0x0 0x008c0000 0x0 0x2000>;
802 iommus = <&apps_smmu 0x483 0x0>;
810 reg = <0x0 0x00880000 0x0 0x4000>;
814 pinctrl-0 = <&qup_i2c15_data_clk>;
817 #size-cells = <0>;
818 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
819 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
820 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
822 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
823 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
830 reg = <0x0 0x00880000 0x0 0x4000>;
835 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
836 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
837 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
839 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
840 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
843 #size-cells = <0>;
849 reg = <0x0 0x00884000 0x0 0x4000>;
853 pinctrl-0 = <&qup_i2c16_data_clk>;
856 #size-cells = <0>;
857 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
858 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
859 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
861 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
869 reg = <0x0 0x00884000 0x0 0x4000>;
874 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>;
875 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
876 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
878 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
882 #size-cells = <0>;
888 reg = <0x0 0x00888000 0x0 0x4000>;
892 pinctrl-0 = <&qup_i2c17_data_clk>;
895 #size-cells = <0>;
896 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
897 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
898 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
900 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
908 reg = <0x0 0x00888000 0x0 0x4000>;
913 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>;
914 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
915 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
917 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
921 #size-cells = <0>;
927 reg = <0x0 0x0088c000 0x0 0x4000>;
931 pinctrl-0 = <&qup_i2c18_data_clk>;
934 #size-cells = <0>;
935 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
936 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
937 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
939 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
947 reg = <0 0x0088c000 0 0x4000>;
952 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>;
953 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
954 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
956 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
960 #size-cells = <0>;
966 reg = <0x0 0x00890000 0x0 0x4000>;
970 pinctrl-0 = <&qup_i2c19_data_clk>;
973 #size-cells = <0>;
974 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
975 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
976 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
978 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
986 reg = <0 0x00890000 0 0x4000>;
991 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>;
992 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
993 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
995 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
999 #size-cells = <0>;
1005 reg = <0x0 0x00894000 0x0 0x4000>;
1009 pinctrl-0 = <&qup_i2c20_data_clk>;
1012 #size-cells = <0>;
1013 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1014 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1015 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1017 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1025 reg = <0 0x00894000 0 0x4000>;
1029 pinctrl-0 = <&qup_uart20_default>;
1036 reg = <0 0x00894000 0 0x4000>;
1041 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>;
1042 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1043 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1045 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1049 #size-cells = <0>;
1055 reg = <0x0 0x00898000 0x0 0x4000>;
1059 pinctrl-0 = <&qup_i2c21_data_clk>;
1062 #size-cells = <0>;
1063 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1064 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1065 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1067 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>,
1075 reg = <0 0x00898000 0 0x4000>;
1080 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>;
1081 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1082 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1084 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>,
1088 #size-cells = <0>;
1096 reg = <0 0x00900000 0 0x60000>;
1110 dma-channel-mask = <0x7e>;
1111 iommus = <&apps_smmu 0x5b6 0x0>;
1117 reg = <0x0 0x009c0000 0x0 0x2000>;
1121 iommus = <&apps_smmu 0x5a3 0x0>;
1122 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>;
1131 reg = <0x0 0x00980000 0x0 0x4000>;
1135 pinctrl-0 = <&qup_i2c0_data_clk>;
1138 #size-cells = <0>;
1139 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1140 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1141 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1143 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1144 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1151 reg = <0x0 0x00980000 0x0 0x4000>;
1156 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1159 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1160 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1161 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1163 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1164 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1167 #size-cells = <0>;
1173 reg = <0x0 0x00984000 0x0 0x4000>;
1177 pinctrl-0 = <&qup_i2c1_data_clk>;
1180 #size-cells = <0>;
1181 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1182 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1183 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1185 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1193 reg = <0x0 0x00984000 0x0 0x4000>;
1198 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1199 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1200 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1201 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1203 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1207 #size-cells = <0>;
1213 reg = <0x0 0x00988000 0x0 0x4000>;
1217 pinctrl-0 = <&qup_i2c2_data_clk>;
1220 #size-cells = <0>;
1221 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1222 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1223 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1225 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1233 reg = <0x0 0x00988000 0x0 0x4000>;
1238 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1239 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1240 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1241 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1243 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1247 #size-cells = <0>;
1254 reg = <0x0 0x0098c000 0x0 0x4000>;
1258 pinctrl-0 = <&qup_i2c3_data_clk>;
1261 #size-cells = <0>;
1262 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1263 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1264 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1266 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1274 reg = <0x0 0x0098c000 0x0 0x4000>;
1279 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1280 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1281 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1282 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1284 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1288 #size-cells = <0>;
1294 reg = <0x0 0x00990000 0x0 0x4000>;
1298 pinctrl-0 = <&qup_i2c4_data_clk>;
1301 #size-cells = <0>;
1302 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1303 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1304 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1306 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1314 reg = <0x0 0x00990000 0x0 0x4000>;
1319 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1322 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1323 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1324 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1326 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1330 #size-cells = <0>;
1336 reg = <0x0 0x00994000 0x0 0x4000>;
1340 pinctrl-0 = <&qup_i2c5_data_clk>;
1343 #size-cells = <0>;
1344 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1345 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1346 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1348 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1356 reg = <0x0 0x00994000 0x0 0x4000>;
1361 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1362 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1363 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1364 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1366 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1370 #size-cells = <0>;
1377 reg = <0x0 0x00998000 0x0 0x4000>;
1381 pinctrl-0 = <&qup_i2c6_data_clk>;
1384 #size-cells = <0>;
1385 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1386 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1387 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1389 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1397 reg = <0x0 0x00998000 0x0 0x4000>;
1402 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1403 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1404 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1405 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1407 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1411 #size-cells = <0>;
1417 reg = <0 0x0099c000 0 0x4000>;
1421 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
1430 reg = <0 0x00a00000 0 0x60000>;
1444 dma-channel-mask = <0x7e>;
1445 iommus = <&apps_smmu 0x56 0x0>;
1451 reg = <0x0 0x00ac0000 0x0 0x6000>;
1455 iommus = <&apps_smmu 0x43 0x0>;
1456 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>;
1465 reg = <0x0 0x00a80000 0x0 0x4000>;
1469 pinctrl-0 = <&qup_i2c8_data_clk>;
1472 #size-cells = <0>;
1473 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1474 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1475 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1477 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1478 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1485 reg = <0x0 0x00a80000 0x0 0x4000>;
1490 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1491 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1492 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1493 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1495 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1496 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1499 #size-cells = <0>;
1505 reg = <0x0 0x00a84000 0x0 0x4000>;
1509 pinctrl-0 = <&qup_i2c9_data_clk>;
1512 #size-cells = <0>;
1513 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1514 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1515 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1517 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1525 reg = <0x0 0x00a84000 0x0 0x4000>;
1530 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1531 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1532 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1533 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1535 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1539 #size-cells = <0>;
1545 reg = <0x0 0x00a88000 0x0 0x4000>;
1549 pinctrl-0 = <&qup_i2c10_data_clk>;
1552 #size-cells = <0>;
1553 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1554 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1555 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1557 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1565 reg = <0x0 0x00a88000 0x0 0x4000>;
1570 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1571 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1572 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1573 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1575 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1579 #size-cells = <0>;
1585 reg = <0x0 0x00a8c000 0x0 0x4000>;
1589 pinctrl-0 = <&qup_i2c11_data_clk>;
1592 #size-cells = <0>;
1593 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1594 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1595 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1597 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1605 reg = <0x0 0x00a8c000 0x0 0x4000>;
1610 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1611 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1612 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1613 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1615 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1619 #size-cells = <0>;
1625 reg = <0x0 0x00a90000 0x0 0x4000>;
1629 pinctrl-0 = <&qup_i2c12_data_clk>;
1632 #size-cells = <0>;
1633 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1634 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1635 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1637 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1645 reg = <0x0 0x00a90000 0x0 0x4000>;
1650 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1651 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1652 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1653 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1655 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1659 #size-cells = <0>;
1665 reg = <0 0x00a94000 0 0x4000>;
1669 pinctrl-0 = <&qup_i2c13_data_clk>;
1671 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1672 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1673 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1675 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1679 #size-cells = <0>;
1685 reg = <0x0 0x00a94000 0x0 0x4000>;
1690 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1691 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1692 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1693 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1695 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1699 #size-cells = <0>;
1705 reg = <0 0x00a98000 0 0x4000>;
1709 pinctrl-0 = <&qup_i2c14_data_clk>;
1711 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1712 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1713 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1715 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1719 #size-cells = <0>;
1725 reg = <0x0 0x00a98000 0x0 0x4000>;
1730 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
1731 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1732 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1733 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1735 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
1739 #size-cells = <0>;
1746 reg = <0 0x010c3000 0 0x1000>;
1751 reg = <0 0x01c00000 0 0x3000>,
1752 <0 0x60000000 0 0xf1d>,
1753 <0 0x60000f20 0 0xa8>,
1754 <0 0x60001000 0 0x1000>,
1755 <0 0x60100000 0 0x100000>;
1758 linux,pci-domain = <0>;
1759 bus-range = <0x00 0xff>;
1765 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1766 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1769 * MSIs for BDF (1:0.0) only works with Device ID 0x5980.
1772 msi-map = <0x0 &gic_its 0x5981 0x1>,
1773 <0x100 &gic_its 0x5980 0x1>;
1774 msi-map-mask = <0xff00>;
1778 interrupt-map-mask = <0 0 0 0x7>;
1779 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1780 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1781 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1782 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1809 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
1810 <0x100 &apps_smmu 0x1c01 0x1>;
1824 pinctrl-0 = <&pcie0_default_state>;
1831 reg = <0 0x01c06000 0 0x2000>;
1845 #clock-cells = <0>;
1847 #phy-cells = <0>;
1860 reg = <0 0x01c08000 0 0x3000>,
1861 <0 0x40000000 0 0xf1d>,
1862 <0 0x40000f20 0 0xa8>,
1863 <0 0x40001000 0 0x1000>,
1864 <0 0x40100000 0 0x100000>;
1868 bus-range = <0x00 0xff>;
1874 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1875 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1878 * MSIs for BDF (1:0.0) only works with Device ID 0x5a00.
1881 msi-map = <0x0 &gic_its 0x5a01 0x1>,
1882 <0x100 &gic_its 0x5a00 0x1>;
1883 msi-map-mask = <0xff00>;
1887 interrupt-map-mask = <0 0 0 0x7>;
1888 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1889 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1890 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1891 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1916 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
1917 <0x100 &apps_smmu 0x1c81 0x1>;
1931 pinctrl-0 = <&pcie1_default_state>;
1938 reg = <0 0x01c0e000 0 0x2000>;
1952 #clock-cells = <0>;
1954 #phy-cells = <0>;
1967 reg = <0 0x01500000 0 0x1c000>;
1974 reg = <0 0x01680000 0 0x1e200>;
1981 reg = <0 0x016c0000 0 0xe280>;
1988 reg = <0 0x016e0000 0 0x1c080>;
1997 reg = <0 0x01700000 0 0x31080>;
2008 reg = <0 0x01740000 0 0x1f080>;
2015 reg = <0x0 0x01f40000 0x0 0x40000>;
2021 reg = <0x0 0x1fc0000 0x0 0x30000>;
2026 reg = <0x0 0x03d00000 0x0 0x40000>,
2027 <0x0 0x03d9e000 0x0 0x1000>,
2028 <0x0 0x03d61000 0x0 0x800>;
2035 iommus = <&adreno_smmu 0 0x400>,
2036 <&adreno_smmu 1 0x400>;
2115 reg = <0x0 0x03d6a000 0x0 0x35000>,
2116 <0x0 0x03d50000 0x0 0x10000>,
2117 <0x0 0x0b290000 0x0 0x10000>;
2144 iommus = <&adreno_smmu 5 0x400>;
2167 reg = <0x0 0x03d90000 0x0 0xa000>;
2179 reg = <0x0 0x03da0000 0x0 0x40000>;
2227 reg = <0 0x088e3000 0 0x400>;
2229 #phy-cells = <0>;
2239 reg = <0 0x088e8000 0 0x3000>;
2258 #size-cells = <0>;
2260 port@0 {
2261 reg = <0>;
2285 reg = <0 0x02400000 0 0x4000>;
2288 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
2306 qcom,smem-states = <&smp2p_slpi_out 0>;
2326 #size-cells = <0>;
2331 iommus = <&apps_smmu 0x0541 0x0>;
2337 iommus = <&apps_smmu 0x0542 0x0>;
2343 iommus = <&apps_smmu 0x0543 0x0>;
2352 reg = <0 0x031e0000 0 0x1000>;
2360 #clock-cells = <0>;
2367 reg = <0 0x031f0000 0 0x2000>;
2373 pinctrl-0 = <&wsa2_swr_active>;
2379 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2380 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2381 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2382 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2383 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2384 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2385 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2386 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2387 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2390 #size-cells = <0>;
2397 reg = <0 0x03200000 0 0x1000>;
2405 #clock-cells = <0>;
2412 reg = <0 0x03210000 0 0x2000>;
2417 qcom,din-ports = <0>;
2420 pinctrl-0 = <&rx_swr_active>;
2423 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2424 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>;
2425 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2426 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2427 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2428 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2429 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2430 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2431 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2434 #size-cells = <0>;
2441 reg = <0 0x03220000 0 0x1000>;
2449 #clock-cells = <0>;
2456 reg = <0 0x03240000 0 0x1000>;
2464 #clock-cells = <0>;
2471 reg = <0 0x03250000 0 0x2000>;
2477 pinctrl-0 = <&wsa_swr_active>;
2483 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2484 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2485 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2486 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2487 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2488 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2489 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2490 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2491 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2494 #size-cells = <0>;
2501 reg = <0 0x033b0000 0 0x2000>;
2510 pinctrl-0 = <&tx_swr_active>;
2514 qcom,dout-ports = <0>;
2515 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
2516 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>;
2517 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
2518 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
2519 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
2520 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
2521 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
2522 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
2523 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>;
2526 #size-cells = <0>;
2533 reg = <0 0x033f0000 0 0x1000>;
2540 #clock-cells = <0>;
2548 reg = <0 0x30000000 0 0x100>;
2551 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2569 qcom,smem-states = <&smp2p_adsp_out 0>;
2590 #size-cells = <0>;
2595 #sound-dai-cells = <0>;
2601 iommus = <&apps_smmu 0x1801 0x0>;
2628 #size-cells = <0>;
2633 iommus = <&apps_smmu 0x1803 0x0>;
2639 iommus = <&apps_smmu 0x1804 0x0>;
2645 iommus = <&apps_smmu 0x1805 0x0>;
2653 reg = <0 0x32300000 0 0x1400000>;
2656 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
2674 qcom,smem-states = <&smp2p_cdsp_out 0>;
2694 #size-cells = <0>;
2699 iommus = <&apps_smmu 0x2161 0x0400>,
2700 <&apps_smmu 0x1021 0x1420>;
2706 iommus = <&apps_smmu 0x2162 0x0400>,
2707 <&apps_smmu 0x1022 0x1420>;
2713 iommus = <&apps_smmu 0x2163 0x0400>,
2714 <&apps_smmu 0x1023 0x1420>;
2720 iommus = <&apps_smmu 0x2164 0x0400>,
2721 <&apps_smmu 0x1024 0x1420>;
2727 iommus = <&apps_smmu 0x2165 0x0400>,
2728 <&apps_smmu 0x1025 0x1420>;
2734 iommus = <&apps_smmu 0x2166 0x0400>,
2735 <&apps_smmu 0x1026 0x1420>;
2741 iommus = <&apps_smmu 0x2167 0x0400>,
2742 <&apps_smmu 0x1027 0x1420>;
2748 iommus = <&apps_smmu 0x2168 0x0400>,
2749 <&apps_smmu 0x1028 0x1420>;
2759 reg = <0x0 0x04080000 0x0 0x4040>;
2762 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
2781 qcom,smem-states = <&smp2p_modem_out 0>;
2799 reg = <0 0x0aaf0000 0 0x10000>;
2811 reg = <0 0x0ac15000 0 0x1000>;
2825 pinctrl-0 = <&cci0_default &cci1_default>;
2831 #size-cells = <0>;
2833 cci0_i2c0: i2c-bus@0 {
2834 reg = <0>;
2837 #size-cells = <0>;
2844 #size-cells = <0>;
2850 reg = <0 0x0ac16000 0 0x1000>;
2864 pinctrl-0 = <&cci2_default &cci3_default>;
2870 #size-cells = <0>;
2872 cci1_i2c0: i2c-bus@0 {
2873 reg = <0>;
2876 #size-cells = <0>;
2883 #size-cells = <0>;
2889 reg = <0 0x0ade0000 0 0x20000>;
2904 reg = <0 0x0ae00000 0 0x1000>;
2908 interconnects = <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>,
2909 <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>,
2929 iommus = <&apps_smmu 0x2800 0x402>;
2939 reg = <0 0x0ae01000 0 0x8f000>,
2940 <0 0x0aeb0000 0 0x2008>;
2963 interrupts = <0>;
2967 #size-cells = <0>;
2969 port@0 {
2970 reg = <0>;
3023 reg = <0 0xae90000 0 0x200>,
3024 <0 0xae90200 0 0x200>,
3025 <0 0xae90400 0 0xc00>,
3026 <0 0xae91000 0 0x400>,
3027 <0 0xae91400 0 0x400>;
3049 #sound-dai-cells = <0>;
3058 #size-cells = <0>;
3060 port@0 {
3061 reg = <0>;
3095 reg = <0 0x0ae94000 0 0x400>;
3115 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
3124 #size-cells = <0>;
3130 #size-cells = <0>;
3132 port@0 {
3133 reg = <0>;
3168 reg = <0 0x0ae94400 0 0x200>,
3169 <0 0x0ae94600 0 0x280>,
3170 <0 0x0ae94900 0 0x260>;
3176 #phy-cells = <0>;
3187 reg = <0 0x0ae96000 0 0x400>;
3207 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
3216 #size-cells = <0>;
3222 #size-cells = <0>;
3224 port@0 {
3225 reg = <0>;
3241 reg = <0 0x0ae96400 0 0x200>,
3242 <0 0x0ae96600 0 0x280>,
3243 <0 0x0ae96900 0 0x260>;
3249 #phy-cells = <0>;
3261 reg = <0 0x0af00000 0 0x20000>;
3266 <&mdss_dsi0_phy 0>,
3268 <&mdss_dsi1_phy 0>,
3272 <0>, /* dp1 */
3273 <0>,
3274 <0>, /* dp2 */
3275 <0>,
3276 <0>, /* dp3 */
3277 <0>;
3288 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
3289 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>,
3298 reg = <0 0x0c263000 0 0x1000>, /* TM */
3299 <0 0x0c222000 0 0x1000>; /* SROT */
3309 reg = <0 0x0c265000 0 0x1000>, /* TM */
3310 <0 0x0c223000 0 0x1000>; /* SROT */
3320 reg = <0 0x0c300000 0 0x400>;
3325 #clock-cells = <0>;
3330 reg = <0 0x0c3f0000 0 0x400>;
3335 reg = <0 0x0c400000 0 0x00003000>,
3336 <0 0x0c500000 0 0x00400000>,
3337 <0 0x0c440000 0 0x00080000>,
3338 <0 0x0c4c0000 0 0x00010000>,
3339 <0 0x0c42d000 0 0x00010000>;
3347 qcom,ee = <0>;
3348 qcom,channel = <0>;
3352 #size-cells = <0>;
3357 reg = <0 0x0ed18000 0 0x1000>;
3366 reg = <0 0x0f100000 0 0x300000>;
3372 gpio-ranges = <&tlmm 0 0 211>;
3876 reg = <0 0x03440000 0x0 0x20000>,
3877 <0 0x034d0000 0x0 0x10000>;
3880 gpio-ranges = <&lpass_tlmm 0 0 23>;
3991 reg = <0 0x146aa000 0 0x1000>;
3992 ranges = <0 0 0x146aa000 0x1000>;
3999 reg = <0x94c 0xc8>;
4005 reg = <0 0x15000000 0 0x100000>;
4112 redistributor-stride = <0x0 0x40000>;
4113 reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */
4114 <0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */
4122 reg = <0x0 0x17140000 0x0 0x20000>;
4132 ranges = <0 0 0 0x20000000>;
4133 reg = <0x0 0x17420000 0x0 0x1000>;
4137 frame-number = <0>;
4140 reg = <0x17421000 0x1000>,
4141 <0x17422000 0x1000>;
4147 reg = <0x17423000 0x1000>;
4154 reg = <0x17425000 0x1000>;
4161 reg = <0x17427000 0x1000>;
4168 reg = <0x17429000 0x1000>;
4175 reg = <0x1742b000 0x1000>;
4182 reg = <0x1742d000 0x1000>;
4190 reg = <0x0 0x17a00000 0x0 0x10000>,
4191 <0x0 0x17a10000 0x0 0x10000>,
4192 <0x0 0x17a20000 0x0 0x10000>,
4193 <0x0 0x17a30000 0x0 0x10000>;
4194 reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
4198 qcom,tcs-offset = <0xd00>;
4201 <WAKE_TCS 2>, <CONTROL_TCS 0>;
4284 reg = <0 0x17d91000 0 0x1000>,
4285 <0 0x17d92000 0 0x1000>,
4286 <0 0x17d93000 0 0x1000>;
4293 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
4300 reg = <0 0x19100000 0 0xbb800>;
4307 reg = <0 0x19200000 0 0x80000>, <0 0x19600000 0 0x80000>,
4308 <0 0x19300000 0 0x80000>, <0 0x19700000 0 0x80000>,
4309 <0 0x19a00000 0 0x80000>;
4318 reg = <0 0x01d84000 0 0x3000>;
4329 iommus = <&apps_smmu 0xe0 0x0>;
4332 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,
4333 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
4355 <0 0>,
4356 <0 0>,
4359 <0 0>,
4360 <0 0>,
4361 <0 0>;
4369 reg = <0 0x01d87000 0 0x1000>;
4376 resets = <&ufs_mem_hc 0>;
4380 #phy-cells = <0>;
4388 reg = <0 0x01d88000 0 0x8000>;
4394 reg = <0 0x01dc4000 0 0x28000>;
4397 qcom,ee = <0>;
4399 iommus = <&apps_smmu 0x584 0x11>,
4400 <&apps_smmu 0x588 0x0>,
4401 <&apps_smmu 0x598 0x5>,
4402 <&apps_smmu 0x59a 0x0>,
4403 <&apps_smmu 0x59f 0x0>;
4408 reg = <0 0x01dfa000 0 0x6000>;
4411 iommus = <&apps_smmu 0x584 0x11>,
4412 <&apps_smmu 0x588 0x0>,
4413 <&apps_smmu 0x598 0x5>,
4414 <&apps_smmu 0x59a 0x0>,
4415 <&apps_smmu 0x59f 0x0>;
4416 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
4422 reg = <0 0x08804000 0 0x1000>;
4433 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
4434 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
4436 iommus = <&apps_smmu 0x4a0 0x0>;
4443 sdhci-caps-mask = <0x3 0x0>;
4464 reg = <0 0x0a6f8800 0 0x400>;
4500 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
4501 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
4506 reg = <0 0x0a600000 0 0xcd00>;
4508 iommus = <&apps_smmu 0x0 0x0>;
4516 #size-cells = <0>;
4518 port@0 {
4519 reg = <0>;
4537 reg = <0 0x320c0000 0 0x10000>;
4544 reg = <0 0x03c40000 0 0x17200>;
4555 polling-delay-passive = <0>;
4556 polling-delay = <0>;
4557 thermal-sensors = <&tsens0 0>;
4575 polling-delay-passive = <0>;
4576 polling-delay = <0>;
4595 polling-delay-passive = <0>;
4596 polling-delay = <0>;
4615 polling-delay-passive = <0>;
4616 polling-delay = <0>;
4635 polling-delay-passive = <0>;
4636 polling-delay = <0>;
4655 polling-delay-passive = <0>;
4656 polling-delay = <0>;
4681 polling-delay-passive = <0>;
4682 polling-delay = <0>;
4707 polling-delay-passive = <0>;
4708 polling-delay = <0>;
4733 polling-delay-passive = <0>;
4734 polling-delay = <0>;
4759 polling-delay-passive = <0>;
4760 polling-delay = <0>;
4785 polling-delay-passive = <0>;
4786 polling-delay = <0>;
4811 polling-delay-passive = <0>;
4812 polling-delay = <0>;
4837 polling-delay-passive = <0>;
4838 polling-delay = <0>;
4863 polling-delay-passive = <0>;
4864 polling-delay = <0>;
4890 polling-delay = <0>;
4922 polling-delay = <0>;
4953 polling-delay-passive = <0>;
4954 polling-delay = <0>;
4955 thermal-sensors = <&tsens1 0>;
4973 polling-delay-passive = <0>;
4974 polling-delay = <0>;
4999 polling-delay-passive = <0>;
5000 polling-delay = <0>;
5025 polling-delay-passive = <0>;
5026 polling-delay = <0>;
5051 polling-delay-passive = <0>;
5052 polling-delay = <0>;
5078 polling-delay = <0>;
5110 polling-delay = <0>;
5142 polling-delay = <0>;
5173 polling-delay-passive = <0>;
5174 polling-delay = <0>;
5194 polling-delay = <0>;
5219 polling-delay-passive = <0>;
5220 polling-delay = <0>;
5251 polling-delay-passive = <0>;
5252 polling-delay = <0>;
5283 polling-delay-passive = <0>;
5284 polling-delay = <0>;
5315 polling-delay-passive = <0>;
5316 polling-delay = <0>;
5347 polling-delay-passive = <0>;
5348 polling-delay = <0>;
5367 polling-delay-passive = <0>;
5368 polling-delay = <0>;