Lines Matching +full:sm8350 +full:- +full:dpu
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/interconnect/qcom,sm8350.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/clock/qcom,dispcc-sm8350.h>
9 #include <dt-bindings/clock/qcom,gcc-sm8350.h>
10 #include <dt-bindings/clock/qcom,gpucc-sm8350.h>
11 #include <dt-bindings/clock/qcom,rpmh.h>
12 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/firmware/qcom,scm.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/interconnect/qcom,sm8350.h>
16 #include <dt-bindings/mailbox/qcom-ipcc.h>
17 #include <dt-bindings/phy/phy-qcom-qmp.h>
18 #include <dt-bindings/power/qcom-rpmpd.h>
19 #include <dt-bindings/power/qcom,rpmhpd.h>
20 #include <dt-bindings/soc/qcom,apr.h>
21 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
22 #include <dt-bindings/sound/qcom,q6afe.h>
23 #include <dt-bindings/thermal/thermal.h>
24 #include <dt-bindings/interconnect/qcom,sm8350.h>
27 interrupt-parent = <&intc>;
29 #address-cells = <2>;
30 #size-cells = <2>;
35 xo_board: xo-board {
36 compatible = "fixed-clock";
37 #clock-cells = <0>;
38 clock-frequency = <38400000>;
39 clock-output-names = "xo_board";
42 sleep_clk: sleep-clk {
43 compatible = "fixed-clock";
44 clock-frequency = <32000>;
45 #clock-cells = <0>;
50 #address-cells = <2>;
51 #size-cells = <0>;
55 compatible = "arm,cortex-a55";
58 enable-method = "psci";
59 next-level-cache = <&L2_0>;
60 qcom,freq-domain = <&cpufreq_hw 0>;
61 power-domains = <&CPU_PD0>;
62 power-domain-names = "psci";
63 #cooling-cells = <2>;
64 L2_0: l2-cache {
66 cache-level = <2>;
67 cache-unified;
68 next-level-cache = <&L3_0>;
69 L3_0: l3-cache {
71 cache-level = <3>;
72 cache-unified;
79 compatible = "arm,cortex-a55";
82 enable-method = "psci";
83 next-level-cache = <&L2_100>;
84 qcom,freq-domain = <&cpufreq_hw 0>;
85 power-domains = <&CPU_PD1>;
86 power-domain-names = "psci";
87 #cooling-cells = <2>;
88 L2_100: l2-cache {
90 cache-level = <2>;
91 cache-unified;
92 next-level-cache = <&L3_0>;
98 compatible = "arm,cortex-a55";
101 enable-method = "psci";
102 next-level-cache = <&L2_200>;
103 qcom,freq-domain = <&cpufreq_hw 0>;
104 power-domains = <&CPU_PD2>;
105 power-domain-names = "psci";
106 #cooling-cells = <2>;
107 L2_200: l2-cache {
109 cache-level = <2>;
110 cache-unified;
111 next-level-cache = <&L3_0>;
117 compatible = "arm,cortex-a55";
120 enable-method = "psci";
121 next-level-cache = <&L2_300>;
122 qcom,freq-domain = <&cpufreq_hw 0>;
123 power-domains = <&CPU_PD3>;
124 power-domain-names = "psci";
125 #cooling-cells = <2>;
126 L2_300: l2-cache {
128 cache-level = <2>;
129 cache-unified;
130 next-level-cache = <&L3_0>;
136 compatible = "arm,cortex-a78";
139 enable-method = "psci";
140 next-level-cache = <&L2_400>;
141 qcom,freq-domain = <&cpufreq_hw 1>;
142 power-domains = <&CPU_PD4>;
143 power-domain-names = "psci";
144 #cooling-cells = <2>;
145 L2_400: l2-cache {
147 cache-level = <2>;
148 cache-unified;
149 next-level-cache = <&L3_0>;
155 compatible = "arm,cortex-a78";
158 enable-method = "psci";
159 next-level-cache = <&L2_500>;
160 qcom,freq-domain = <&cpufreq_hw 1>;
161 power-domains = <&CPU_PD5>;
162 power-domain-names = "psci";
163 #cooling-cells = <2>;
164 L2_500: l2-cache {
166 cache-level = <2>;
167 cache-unified;
168 next-level-cache = <&L3_0>;
174 compatible = "arm,cortex-a78";
177 enable-method = "psci";
178 next-level-cache = <&L2_600>;
179 qcom,freq-domain = <&cpufreq_hw 1>;
180 power-domains = <&CPU_PD6>;
181 power-domain-names = "psci";
182 #cooling-cells = <2>;
183 L2_600: l2-cache {
185 cache-level = <2>;
186 cache-unified;
187 next-level-cache = <&L3_0>;
193 compatible = "arm,cortex-x1";
196 enable-method = "psci";
197 next-level-cache = <&L2_700>;
198 qcom,freq-domain = <&cpufreq_hw 2>;
199 power-domains = <&CPU_PD7>;
200 power-domain-names = "psci";
201 #cooling-cells = <2>;
202 L2_700: l2-cache {
204 cache-level = <2>;
205 cache-unified;
206 next-level-cache = <&L3_0>;
210 cpu-map {
246 idle-states {
247 entry-method = "psci";
249 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
250 compatible = "arm,idle-state";
251 idle-state-name = "silver-rail-power-collapse";
252 arm,psci-suspend-param = <0x40000004>;
253 entry-latency-us = <360>;
254 exit-latency-us = <531>;
255 min-residency-us = <3934>;
256 local-timer-stop;
259 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
260 compatible = "arm,idle-state";
261 idle-state-name = "gold-rail-power-collapse";
262 arm,psci-suspend-param = <0x40000004>;
263 entry-latency-us = <702>;
264 exit-latency-us = <1061>;
265 min-residency-us = <4488>;
266 local-timer-stop;
270 domain-idle-states {
271 CLUSTER_SLEEP_APSS_OFF: cluster-sleep-0 {
272 compatible = "domain-idle-state";
273 arm,psci-suspend-param = <0x41000044>;
274 entry-latency-us = <2752>;
275 exit-latency-us = <3048>;
276 min-residency-us = <6118>;
279 CLUSTER_SLEEP_AOSS_SLEEP: cluster-sleep-1 {
280 compatible = "domain-idle-state";
281 arm,psci-suspend-param = <0x4100c344>;
282 entry-latency-us = <3263>;
283 exit-latency-us = <6562>;
284 min-residency-us = <9987>;
291 compatible = "qcom,scm-sm8350", "qcom,scm";
292 qcom,dload-mode = <&tcsr 0x13000>;
293 #reset-cells = <1>;
304 compatible = "arm,armv8-pmuv3";
309 compatible = "arm,psci-1.0";
312 CPU_PD0: power-domain-cpu0 {
313 #power-domain-cells = <0>;
314 power-domains = <&CLUSTER_PD>;
315 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
318 CPU_PD1: power-domain-cpu1 {
319 #power-domain-cells = <0>;
320 power-domains = <&CLUSTER_PD>;
321 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
324 CPU_PD2: power-domain-cpu2 {
325 #power-domain-cells = <0>;
326 power-domains = <&CLUSTER_PD>;
327 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
330 CPU_PD3: power-domain-cpu3 {
331 #power-domain-cells = <0>;
332 power-domains = <&CLUSTER_PD>;
333 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
336 CPU_PD4: power-domain-cpu4 {
337 #power-domain-cells = <0>;
338 power-domains = <&CLUSTER_PD>;
339 domain-idle-states = <&BIG_CPU_SLEEP_0>;
342 CPU_PD5: power-domain-cpu5 {
343 #power-domain-cells = <0>;
344 power-domains = <&CLUSTER_PD>;
345 domain-idle-states = <&BIG_CPU_SLEEP_0>;
348 CPU_PD6: power-domain-cpu6 {
349 #power-domain-cells = <0>;
350 power-domains = <&CLUSTER_PD>;
351 domain-idle-states = <&BIG_CPU_SLEEP_0>;
354 CPU_PD7: power-domain-cpu7 {
355 #power-domain-cells = <0>;
356 power-domains = <&CLUSTER_PD>;
357 domain-idle-states = <&BIG_CPU_SLEEP_0>;
360 CLUSTER_PD: power-domain-cpu-cluster0 {
361 #power-domain-cells = <0>;
362 domain-idle-states = <&CLUSTER_SLEEP_APSS_OFF &CLUSTER_SLEEP_AOSS_SLEEP>;
366 qup_opp_table_100mhz: opp-table-qup100mhz {
367 compatible = "operating-points-v2";
369 opp-50000000 {
370 opp-hz = /bits/ 64 <50000000>;
371 required-opps = <&rpmhpd_opp_min_svs>;
374 opp-75000000 {
375 opp-hz = /bits/ 64 <75000000>;
376 required-opps = <&rpmhpd_opp_low_svs>;
379 opp-100000000 {
380 opp-hz = /bits/ 64 <100000000>;
381 required-opps = <&rpmhpd_opp_svs>;
385 qup_opp_table_120mhz: opp-table-qup120mhz {
386 compatible = "operating-points-v2";
388 opp-50000000 {
389 opp-hz = /bits/ 64 <50000000>;
390 required-opps = <&rpmhpd_opp_min_svs>;
393 opp-75000000 {
394 opp-hz = /bits/ 64 <75000000>;
395 required-opps = <&rpmhpd_opp_low_svs>;
398 opp-120000000 {
399 opp-hz = /bits/ 64 <120000000>;
400 required-opps = <&rpmhpd_opp_svs>;
404 reserved_memory: reserved-memory {
405 #address-cells = <2>;
406 #size-cells = <2>;
411 no-map;
415 no-map;
420 compatible = "qcom,cmd-db";
422 no-map;
427 no-map;
434 no-map;
439 no-map;
444 no-map;
449 no-map;
454 no-map;
459 no-map;
464 no-map;
469 no-map;
474 no-map;
479 no-map;
484 no-map;
489 no-map;
494 no-map;
499 no-map;
503 compatible = "qcom,rmtfs-mem";
505 no-map;
507 qcom,client-id = <1>;
513 no-map;
518 no-map;
523 no-map;
528 no-map;
533 no-map;
538 no-map;
542 smp2p-adsp {
545 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
551 qcom,local-pid = <0>;
552 qcom,remote-pid = <2>;
554 smp2p_adsp_out: master-kernel {
555 qcom,entry-name = "master-kernel";
556 #qcom,smem-state-cells = <1>;
559 smp2p_adsp_in: slave-kernel {
560 qcom,entry-name = "slave-kernel";
561 interrupt-controller;
562 #interrupt-cells = <2>;
566 smp2p-cdsp {
569 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
575 qcom,local-pid = <0>;
576 qcom,remote-pid = <5>;
578 smp2p_cdsp_out: master-kernel {
579 qcom,entry-name = "master-kernel";
580 #qcom,smem-state-cells = <1>;
583 smp2p_cdsp_in: slave-kernel {
584 qcom,entry-name = "slave-kernel";
585 interrupt-controller;
586 #interrupt-cells = <2>;
590 smp2p-modem {
593 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
599 qcom,local-pid = <0>;
600 qcom,remote-pid = <1>;
602 smp2p_modem_out: master-kernel {
603 qcom,entry-name = "master-kernel";
604 #qcom,smem-state-cells = <1>;
607 smp2p_modem_in: slave-kernel {
608 qcom,entry-name = "slave-kernel";
609 interrupt-controller;
610 #interrupt-cells = <2>;
613 ipa_smp2p_out: ipa-ap-to-modem {
614 qcom,entry-name = "ipa";
615 #qcom,smem-state-cells = <1>;
618 ipa_smp2p_in: ipa-modem-to-ap {
619 qcom,entry-name = "ipa";
620 interrupt-controller;
621 #interrupt-cells = <2>;
625 smp2p-slpi {
628 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
634 qcom,local-pid = <0>;
635 qcom,remote-pid = <3>;
637 smp2p_slpi_out: master-kernel {
638 qcom,entry-name = "master-kernel";
639 #qcom,smem-state-cells = <1>;
642 smp2p_slpi_in: slave-kernel {
643 qcom,entry-name = "slave-kernel";
644 interrupt-controller;
645 #interrupt-cells = <2>;
650 #address-cells = <2>;
651 #size-cells = <2>;
653 dma-ranges = <0 0 0 0 0x10 0>;
654 compatible = "simple-bus";
656 gcc: clock-controller@100000 {
657 compatible = "qcom,gcc-sm8350";
659 #clock-cells = <1>;
660 #reset-cells = <1>;
661 #power-domain-cells = <1>;
662 clock-names = "bi_tcxo",
689 compatible = "qcom,sm8350-ipcc", "qcom,ipcc";
692 interrupt-controller;
693 #interrupt-cells = <3>;
694 #mbox-cells = <2>;
697 gpi_dma2: dma-controller@800000 {
698 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma";
712 dma-channels = <12>;
713 dma-channel-mask = <0xff>;
715 #dma-cells = <3>;
720 compatible = "qcom,geni-se-qup";
722 clock-names = "m-ahb", "s-ahb";
726 #address-cells = <2>;
727 #size-cells = <2>;
732 compatible = "qcom,geni-i2c";
734 clock-names = "se";
736 pinctrl-names = "default";
737 pinctrl-0 = <&qup_i2c14_default>;
741 dma-names = "tx", "rx";
742 #address-cells = <1>;
743 #size-cells = <0>;
748 compatible = "qcom,geni-spi";
750 clock-names = "se";
753 power-domains = <&rpmhpd RPMHPD_CX>;
754 operating-points-v2 = <&qup_opp_table_120mhz>;
757 dma-names = "tx", "rx";
758 #address-cells = <1>;
759 #size-cells = <0>;
764 compatible = "qcom,geni-i2c";
766 clock-names = "se";
768 pinctrl-names = "default";
769 pinctrl-0 = <&qup_i2c15_default>;
773 dma-names = "tx", "rx";
774 #address-cells = <1>;
775 #size-cells = <0>;
780 compatible = "qcom,geni-spi";
782 clock-names = "se";
785 power-domains = <&rpmhpd RPMHPD_CX>;
786 operating-points-v2 = <&qup_opp_table_120mhz>;
789 dma-names = "tx", "rx";
790 #address-cells = <1>;
791 #size-cells = <0>;
796 compatible = "qcom,geni-i2c";
798 clock-names = "se";
800 pinctrl-names = "default";
801 pinctrl-0 = <&qup_i2c16_default>;
805 dma-names = "tx", "rx";
806 #address-cells = <1>;
807 #size-cells = <0>;
812 compatible = "qcom,geni-spi";
814 clock-names = "se";
817 power-domains = <&rpmhpd RPMHPD_CX>;
818 operating-points-v2 = <&qup_opp_table_100mhz>;
821 dma-names = "tx", "rx";
822 #address-cells = <1>;
823 #size-cells = <0>;
828 compatible = "qcom,geni-i2c";
830 clock-names = "se";
832 pinctrl-names = "default";
833 pinctrl-0 = <&qup_i2c17_default>;
837 dma-names = "tx", "rx";
838 #address-cells = <1>;
839 #size-cells = <0>;
844 compatible = "qcom,geni-spi";
846 clock-names = "se";
849 power-domains = <&rpmhpd RPMHPD_CX>;
850 operating-points-v2 = <&qup_opp_table_100mhz>;
853 dma-names = "tx", "rx";
854 #address-cells = <1>;
855 #size-cells = <0>;
859 /* QUP no. 18 seems to be strictly SPI/UART-only */
862 compatible = "qcom,geni-spi";
864 clock-names = "se";
867 power-domains = <&rpmhpd RPMHPD_CX>;
868 operating-points-v2 = <&qup_opp_table_100mhz>;
871 dma-names = "tx", "rx";
872 #address-cells = <1>;
873 #size-cells = <0>;
878 compatible = "qcom,geni-uart";
880 clock-names = "se";
882 pinctrl-names = "default";
883 pinctrl-0 = <&qup_uart18_default>;
885 power-domains = <&rpmhpd RPMHPD_CX>;
886 operating-points-v2 = <&qup_opp_table_100mhz>;
891 compatible = "qcom,geni-i2c";
893 clock-names = "se";
895 pinctrl-names = "default";
896 pinctrl-0 = <&qup_i2c19_default>;
900 dma-names = "tx", "rx";
901 #address-cells = <1>;
902 #size-cells = <0>;
907 compatible = "qcom,geni-spi";
909 clock-names = "se";
912 power-domains = <&rpmhpd RPMHPD_CX>;
913 operating-points-v2 = <&qup_opp_table_100mhz>;
916 dma-names = "tx", "rx";
917 #address-cells = <1>;
918 #size-cells = <0>;
923 gpi_dma0: dma-controller@900000 {
924 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma";
938 dma-channels = <12>;
939 dma-channel-mask = <0x7e>;
941 #dma-cells = <3>;
946 compatible = "qcom,geni-se-qup";
948 clock-names = "m-ahb", "s-ahb";
952 #address-cells = <2>;
953 #size-cells = <2>;
958 compatible = "qcom,geni-i2c";
960 clock-names = "se";
962 pinctrl-names = "default";
963 pinctrl-0 = <&qup_i2c0_default>;
967 dma-names = "tx", "rx";
968 #address-cells = <1>;
969 #size-cells = <0>;
974 compatible = "qcom,geni-spi";
976 clock-names = "se";
979 power-domains = <&rpmhpd RPMHPD_CX>;
980 operating-points-v2 = <&qup_opp_table_100mhz>;
983 dma-names = "tx", "rx";
984 #address-cells = <1>;
985 #size-cells = <0>;
990 compatible = "qcom,geni-i2c";
992 clock-names = "se";
994 pinctrl-names = "default";
995 pinctrl-0 = <&qup_i2c1_default>;
999 dma-names = "tx", "rx";
1000 #address-cells = <1>;
1001 #size-cells = <0>;
1006 compatible = "qcom,geni-spi";
1008 clock-names = "se";
1011 power-domains = <&rpmhpd RPMHPD_CX>;
1012 operating-points-v2 = <&qup_opp_table_100mhz>;
1015 dma-names = "tx", "rx";
1016 #address-cells = <1>;
1017 #size-cells = <0>;
1022 compatible = "qcom,geni-i2c";
1024 clock-names = "se";
1026 pinctrl-names = "default";
1027 pinctrl-0 = <&qup_i2c2_default>;
1031 dma-names = "tx", "rx";
1032 #address-cells = <1>;
1033 #size-cells = <0>;
1038 compatible = "qcom,geni-spi";
1040 clock-names = "se";
1043 power-domains = <&rpmhpd RPMHPD_CX>;
1044 operating-points-v2 = <&qup_opp_table_100mhz>;
1047 dma-names = "tx", "rx";
1048 #address-cells = <1>;
1049 #size-cells = <0>;
1054 compatible = "qcom,geni-debug-uart";
1056 clock-names = "se";
1058 pinctrl-names = "default";
1059 pinctrl-0 = <&qup_uart3_default_state>;
1061 power-domains = <&rpmhpd RPMHPD_CX>;
1062 operating-points-v2 = <&qup_opp_table_100mhz>;
1066 /* QUP no. 3 seems to be strictly SPI-only */
1069 compatible = "qcom,geni-spi";
1071 clock-names = "se";
1074 power-domains = <&rpmhpd RPMHPD_CX>;
1075 operating-points-v2 = <&qup_opp_table_100mhz>;
1078 dma-names = "tx", "rx";
1079 #address-cells = <1>;
1080 #size-cells = <0>;
1085 compatible = "qcom,geni-i2c";
1087 clock-names = "se";
1089 pinctrl-names = "default";
1090 pinctrl-0 = <&qup_i2c4_default>;
1094 dma-names = "tx", "rx";
1095 #address-cells = <1>;
1096 #size-cells = <0>;
1101 compatible = "qcom,geni-spi";
1103 clock-names = "se";
1106 power-domains = <&rpmhpd RPMHPD_CX>;
1107 operating-points-v2 = <&qup_opp_table_100mhz>;
1110 dma-names = "tx", "rx";
1111 #address-cells = <1>;
1112 #size-cells = <0>;
1117 compatible = "qcom,geni-i2c";
1119 clock-names = "se";
1121 pinctrl-names = "default";
1122 pinctrl-0 = <&qup_i2c5_default>;
1126 dma-names = "tx", "rx";
1127 #address-cells = <1>;
1128 #size-cells = <0>;
1133 compatible = "qcom,geni-spi";
1135 clock-names = "se";
1138 power-domains = <&rpmhpd RPMHPD_CX>;
1139 operating-points-v2 = <&qup_opp_table_100mhz>;
1142 dma-names = "tx", "rx";
1143 #address-cells = <1>;
1144 #size-cells = <0>;
1149 compatible = "qcom,geni-i2c";
1151 clock-names = "se";
1153 pinctrl-names = "default";
1154 pinctrl-0 = <&qup_i2c6_default>;
1158 dma-names = "tx", "rx";
1159 #address-cells = <1>;
1160 #size-cells = <0>;
1165 compatible = "qcom,geni-spi";
1167 clock-names = "se";
1170 power-domains = <&rpmhpd RPMHPD_CX>;
1171 operating-points-v2 = <&qup_opp_table_100mhz>;
1174 dma-names = "tx", "rx";
1175 #address-cells = <1>;
1176 #size-cells = <0>;
1181 compatible = "qcom,geni-uart";
1183 clock-names = "se";
1185 pinctrl-names = "default";
1186 pinctrl-0 = <&qup_uart6_default>;
1188 power-domains = <&rpmhpd RPMHPD_CX>;
1189 operating-points-v2 = <&qup_opp_table_100mhz>;
1194 compatible = "qcom,geni-i2c";
1196 clock-names = "se";
1198 pinctrl-names = "default";
1199 pinctrl-0 = <&qup_i2c7_default>;
1203 dma-names = "tx", "rx";
1204 #address-cells = <1>;
1205 #size-cells = <0>;
1210 compatible = "qcom,geni-spi";
1212 clock-names = "se";
1215 power-domains = <&rpmhpd RPMHPD_CX>;
1216 operating-points-v2 = <&qup_opp_table_100mhz>;
1219 dma-names = "tx", "rx";
1220 #address-cells = <1>;
1221 #size-cells = <0>;
1226 gpi_dma1: dma-controller@a00000 {
1227 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma";
1241 dma-channels = <12>;
1242 dma-channel-mask = <0xff>;
1244 #dma-cells = <3>;
1249 compatible = "qcom,geni-se-qup";
1251 clock-names = "m-ahb", "s-ahb";
1255 #address-cells = <2>;
1256 #size-cells = <2>;
1261 compatible = "qcom,geni-i2c";
1263 clock-names = "se";
1265 pinctrl-names = "default";
1266 pinctrl-0 = <&qup_i2c8_default>;
1270 dma-names = "tx", "rx";
1271 #address-cells = <1>;
1272 #size-cells = <0>;
1277 compatible = "qcom,geni-spi";
1279 clock-names = "se";
1282 power-domains = <&rpmhpd RPMHPD_CX>;
1283 operating-points-v2 = <&qup_opp_table_120mhz>;
1286 dma-names = "tx", "rx";
1287 #address-cells = <1>;
1288 #size-cells = <0>;
1293 compatible = "qcom,geni-i2c";
1295 clock-names = "se";
1297 pinctrl-names = "default";
1298 pinctrl-0 = <&qup_i2c9_default>;
1302 dma-names = "tx", "rx";
1303 #address-cells = <1>;
1304 #size-cells = <0>;
1309 compatible = "qcom,geni-spi";
1311 clock-names = "se";
1314 power-domains = <&rpmhpd RPMHPD_CX>;
1315 operating-points-v2 = <&qup_opp_table_100mhz>;
1318 dma-names = "tx", "rx";
1319 #address-cells = <1>;
1320 #size-cells = <0>;
1325 compatible = "qcom,geni-i2c";
1327 clock-names = "se";
1329 pinctrl-names = "default";
1330 pinctrl-0 = <&qup_i2c10_default>;
1334 dma-names = "tx", "rx";
1335 #address-cells = <1>;
1336 #size-cells = <0>;
1341 compatible = "qcom,geni-spi";
1343 clock-names = "se";
1346 power-domains = <&rpmhpd RPMHPD_CX>;
1347 operating-points-v2 = <&qup_opp_table_100mhz>;
1350 dma-names = "tx", "rx";
1351 #address-cells = <1>;
1352 #size-cells = <0>;
1357 compatible = "qcom,geni-i2c";
1359 clock-names = "se";
1361 pinctrl-names = "default";
1362 pinctrl-0 = <&qup_i2c11_default>;
1366 dma-names = "tx", "rx";
1367 #address-cells = <1>;
1368 #size-cells = <0>;
1373 compatible = "qcom,geni-spi";
1375 clock-names = "se";
1378 power-domains = <&rpmhpd RPMHPD_CX>;
1379 operating-points-v2 = <&qup_opp_table_100mhz>;
1382 dma-names = "tx", "rx";
1383 #address-cells = <1>;
1384 #size-cells = <0>;
1389 compatible = "qcom,geni-i2c";
1391 clock-names = "se";
1393 pinctrl-names = "default";
1394 pinctrl-0 = <&qup_i2c12_default>;
1398 dma-names = "tx", "rx";
1399 #address-cells = <1>;
1400 #size-cells = <0>;
1405 compatible = "qcom,geni-spi";
1407 clock-names = "se";
1410 power-domains = <&rpmhpd RPMHPD_CX>;
1411 operating-points-v2 = <&qup_opp_table_100mhz>;
1414 dma-names = "tx", "rx";
1415 #address-cells = <1>;
1416 #size-cells = <0>;
1421 compatible = "qcom,geni-i2c";
1423 clock-names = "se";
1425 pinctrl-names = "default";
1426 pinctrl-0 = <&qup_i2c13_default>;
1430 dma-names = "tx", "rx";
1431 #address-cells = <1>;
1432 #size-cells = <0>;
1437 compatible = "qcom,geni-spi";
1439 clock-names = "se";
1442 power-domains = <&rpmhpd RPMHPD_CX>;
1443 operating-points-v2 = <&qup_opp_table_100mhz>;
1446 dma-names = "tx", "rx";
1447 #address-cells = <1>;
1448 #size-cells = <0>;
1454 compatible = "qcom,prng-ee";
1457 clock-names = "core";
1461 compatible = "qcom,sm8350-config-noc";
1463 #interconnect-cells = <2>;
1464 qcom,bcm-voters = <&apps_bcm_voter>;
1468 compatible = "qcom,sm8350-mc-virt";
1470 #interconnect-cells = <2>;
1471 qcom,bcm-voters = <&apps_bcm_voter>;
1475 compatible = "qcom,sm8350-system-noc";
1477 #interconnect-cells = <2>;
1478 qcom,bcm-voters = <&apps_bcm_voter>;
1482 compatible = "qcom,sm8350-aggre1-noc";
1484 #interconnect-cells = <2>;
1485 qcom,bcm-voters = <&apps_bcm_voter>;
1489 compatible = "qcom,sm8350-aggre2-noc";
1491 #interconnect-cells = <2>;
1492 qcom,bcm-voters = <&apps_bcm_voter>;
1496 compatible = "qcom,sm8350-mmss-noc";
1498 #interconnect-cells = <2>;
1499 qcom,bcm-voters = <&apps_bcm_voter>;
1503 compatible = "qcom,pcie-sm8350";
1509 reg-names = "parf", "dbi", "elbi", "atu", "config";
1511 linux,pci-domain = <0>;
1512 bus-range = <0x00 0xff>;
1513 num-lanes = <1>;
1515 #address-cells = <3>;
1516 #size-cells = <2>;
1529 interrupt-names = "msi0", "msi1", "msi2", "msi3",
1531 #interrupt-cells = <1>;
1532 interrupt-map-mask = <0 0 0 0x7>;
1533 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1547 clock-names = "aux",
1557 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
1561 reset-names = "pci";
1563 power-domains = <&gcc PCIE_0_GDSC>;
1566 phy-names = "pciephy";
1572 compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy";
1579 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe";
1582 reset-names = "phy";
1584 assigned-clocks = <&gcc GCC_PCIE0_PHY_RCHNG_CLK>;
1585 assigned-clock-rates = <100000000>;
1587 #clock-cells = <0>;
1588 clock-output-names = "pcie_0_pipe_clk";
1590 #phy-cells = <0>;
1596 compatible = "qcom,pcie-sm8350";
1602 reg-names = "parf", "dbi", "elbi", "atu", "config";
1604 linux,pci-domain = <1>;
1605 bus-range = <0x00 0xff>;
1606 num-lanes = <2>;
1608 #address-cells = <3>;
1609 #size-cells = <2>;
1615 interrupt-names = "msi";
1616 #interrupt-cells = <1>;
1617 interrupt-map-mask = <0 0 0 0x7>;
1618 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1631 clock-names = "aux",
1640 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
1644 reset-names = "pci";
1646 power-domains = <&gcc PCIE_1_GDSC>;
1649 phy-names = "pciephy";
1655 compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy";
1662 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe";
1665 reset-names = "phy";
1667 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>;
1668 assigned-clock-rates = <100000000>;
1670 #clock-cells = <0>;
1671 clock-output-names = "pcie_1_pipe_clk";
1673 #phy-cells = <0>;
1679 compatible = "qcom,sm8350-ufshc", "qcom,ufshc",
1680 "jedec,ufs-2.0";
1684 phy-names = "ufsphy";
1685 lanes-per-direction = <2>;
1686 #reset-cells = <1>;
1688 reset-names = "rst";
1690 power-domains = <&gcc UFS_PHY_GDSC>;
1693 dma-coherent;
1695 clock-names =
1713 freq-table-hz =
1726 compatible = "qcom,sm8350-qmp-ufs-phy";
1729 clock-names = "ref",
1735 reset-names = "ufsphy";
1737 #clock-cells = <1>;
1738 #phy-cells = <0>;
1743 cryptobam: dma-controller@1dc4000 {
1744 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
1747 #dma-cells = <1>;
1749 qcom,controlled-remotely;
1757 compatible = "qcom,sm8350-qce", "qcom,sm8150-qce", "qcom,qce";
1760 dma-names = "rx", "tx";
1764 interconnect-names = "memory";
1770 compatible = "qcom,sm8350-ipa";
1777 reg-names = "ipa-reg",
1778 "ipa-shared",
1781 interrupts-extended = <&intc GIC_SPI 655 IRQ_TYPE_EDGE_RISING>,
1785 interrupt-names = "ipa",
1787 "ipa-clock-query",
1788 "ipa-setup-ready";
1791 clock-names = "core";
1795 interconnect-names = "memory",
1800 qcom,smem-states = <&ipa_smp2p_out 0>,
1802 qcom,smem-state-names = "ipa-clock-enabled-valid",
1803 "ipa-clock-enabled";
1809 compatible = "qcom,tcsr-mutex";
1811 #hwlock-cells = <1>;
1815 compatible = "qcom,sm8350-tcsr", "syscon";
1820 compatible = "qcom,sm8350-lpass-lpi-pinctrl";
1826 clock-names = "core", "audio";
1828 gpio-controller;
1829 #gpio-cells = <2>;
1830 gpio-ranges = <&lpass_tlmm 0 0 15>;
1834 compatible = "qcom,adreno-660.1", "qcom,adreno";
1839 reg-names = "kgsl_3d0_reg_memory",
1847 operating-points-v2 = <&gpu_opp_table>;
1853 zap-shader {
1854 memory-region = <&pil_gpu_mem>;
1858 gpu_opp_table: opp-table {
1859 compatible = "operating-points-v2";
1861 opp-840000000 {
1862 opp-hz = /bits/ 64 <840000000>;
1863 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1866 opp-778000000 {
1867 opp-hz = /bits/ 64 <778000000>;
1868 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1871 opp-738000000 {
1872 opp-hz = /bits/ 64 <738000000>;
1873 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1876 opp-676000000 {
1877 opp-hz = /bits/ 64 <676000000>;
1878 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1881 opp-608000000 {
1882 opp-hz = /bits/ 64 <608000000>;
1883 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
1886 opp-540000000 {
1887 opp-hz = /bits/ 64 <540000000>;
1888 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1891 opp-491000000 {
1892 opp-hz = /bits/ 64 <491000000>;
1893 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
1896 opp-443000000 {
1897 opp-hz = /bits/ 64 <443000000>;
1898 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1901 opp-379000000 {
1902 opp-hz = /bits/ 64 <379000000>;
1903 opp-level = <80 /* RPMH_REGULATOR_LEVEL_LOW_SVS_L1 */>;
1906 opp-315000000 {
1907 opp-hz = /bits/ 64 <315000000>;
1908 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1914 compatible = "qcom,adreno-gmu-660.1", "qcom,adreno-gmu";
1919 reg-names = "gmu", "rscc", "gmu_pdc";
1923 interrupt-names = "hfi", "gmu";
1932 clock-names = "gmu",
1940 power-domains = <&gpucc GPU_CX_GDSC>,
1942 power-domain-names = "cx",
1947 operating-points-v2 = <&gmu_opp_table>;
1949 gmu_opp_table: opp-table {
1950 compatible = "operating-points-v2";
1952 opp-200000000 {
1953 opp-hz = /bits/ 64 <200000000>;
1954 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1959 gpucc: clock-controller@3d90000 {
1960 compatible = "qcom,sm8350-gpucc";
1965 clock-names = "bi_tcxo",
1968 #clock-cells = <1>;
1969 #reset-cells = <1>;
1970 #power-domain-cells = <1>;
1974 compatible = "qcom,sm8350-smmu-500", "qcom,adreno-smmu",
1975 "qcom,smmu-500", "arm,mmu-500";
1977 #iommu-cells = <2>;
1978 #global-interrupts = <2>;
1999 clock-names = "bus",
2007 power-domains = <&gpucc GPU_CX_GDSC>;
2008 dma-coherent;
2012 compatible = "qcom,sm8350-lpass-ag-noc";
2014 #interconnect-cells = <2>;
2015 qcom,bcm-voters = <&apps_bcm_voter>;
2019 compatible = "qcom,sm8350-mpss-pas";
2022 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
2028 interrupt-names = "wdog", "fatal", "ready", "handover",
2029 "stop-ack", "shutdown-ack";
2032 clock-names = "xo";
2034 power-domains = <&rpmhpd RPMHPD_CX>,
2036 power-domain-names = "cx", "mss";
2040 memory-region = <&pil_modem_mem>;
2044 qcom,smem-states = <&smp2p_modem_out 0>;
2045 qcom,smem-state-names = "stop";
2049 glink-edge {
2050 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2056 qcom,remote-pid = <1>;
2061 compatible = "qcom,sm8350-slpi-pas";
2064 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>,
2069 interrupt-names = "wdog", "fatal", "ready",
2070 "handover", "stop-ack";
2073 clock-names = "xo";
2075 power-domains = <&rpmhpd RPMHPD_LCX>,
2077 power-domain-names = "lcx", "lmx";
2079 memory-region = <&pil_slpi_mem>;
2083 qcom,smem-states = <&smp2p_slpi_out 0>;
2084 qcom,smem-state-names = "stop";
2088 glink-edge {
2089 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
2096 qcom,remote-pid = <3>;
2100 qcom,glink-channels = "fastrpcglink-apps-dsp";
2102 qcom,non-secure-domain;
2103 #address-cells = <1>;
2104 #size-cells = <0>;
2106 compute-cb@1 {
2107 compatible = "qcom,fastrpc-compute-cb";
2112 compute-cb@2 {
2113 compatible = "qcom,fastrpc-compute-cb";
2118 compute-cb@3 {
2119 compatible = "qcom,fastrpc-compute-cb";
2122 /* note: shared-cb = <4> in downstream */
2129 compatible = "qcom,sm8350-sdhci", "qcom,sdhci-msm-v5";
2134 interrupt-names = "hc_irq", "pwr_irq";
2139 clock-names = "iface", "core", "xo";
2143 interconnect-names = "sdhc-ddr","cpu-sdhc";
2145 power-domains = <&rpmhpd RPMHPD_CX>;
2146 operating-points-v2 = <&sdhc2_opp_table>;
2147 bus-width = <4>;
2148 dma-coherent;
2152 sdhc2_opp_table: opp-table {
2153 compatible = "operating-points-v2";
2155 opp-100000000 {
2156 opp-hz = /bits/ 64 <100000000>;
2157 required-opps = <&rpmhpd_opp_low_svs>;
2160 opp-202000000 {
2161 opp-hz = /bits/ 64 <202000000>;
2162 required-opps = <&rpmhpd_opp_svs_l1>;
2168 compatible = "qcom,sm8350-usb-hs-phy",
2169 "qcom,usb-snps-hs-7nm-phy";
2172 #phy-cells = <0>;
2175 clock-names = "ref";
2181 compatible = "qcom,sm8250-usb-hs-phy",
2182 "qcom,usb-snps-hs-7nm-phy";
2185 #phy-cells = <0>;
2188 clock-names = "ref";
2194 compatible = "qcom,sm8350-qmp-usb3-dp-phy";
2201 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
2205 reset-names = "phy", "common";
2207 #clock-cells = <1>;
2208 #phy-cells = <1>;
2213 #address-cells = <1>;
2214 #size-cells = <0>;
2240 compatible = "qcom,sm8350-qmp-usb3-uni-phy";
2248 clock-names = "aux",
2252 clock-output-names = "usb3_uni_phy_pipe_clk_src";
2253 #clock-cells = <0>;
2254 #phy-cells = <0>;
2258 reset-names = "phy",
2263 compatible = "qcom,sm8350-dc-noc";
2265 #interconnect-cells = <2>;
2266 qcom,bcm-voters = <&apps_bcm_voter>;
2270 compatible = "qcom,sm8350-gem-noc";
2272 #interconnect-cells = <2>;
2273 qcom,bcm-voters = <&apps_bcm_voter>;
2276 system-cache-controller@9200000 {
2277 compatible = "qcom,sm8350-llcc";
2281 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
2286 compatible = "qcom,sm8350-compute-noc";
2288 #interconnect-cells = <2>;
2289 qcom,bcm-voters = <&apps_bcm_voter>;
2293 compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
2296 #address-cells = <2>;
2297 #size-cells = <2>;
2305 clock-names = "cfg_noc",
2311 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2313 assigned-clock-rates = <19200000>, <200000000>;
2315 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
2319 interrupt-names = "hs_phy_irq",
2324 power-domains = <&gcc USB30_PRIM_GDSC>;
2330 interconnect-names = "usb-ddr", "apps-usb";
2340 phy-names = "usb2-phy", "usb3-phy";
2343 #address-cells = <1>;
2344 #size-cells = <0>;
2364 compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
2367 #address-cells = <2>;
2368 #size-cells = <2>;
2377 clock-names = "cfg_noc",
2384 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2386 assigned-clock-rates = <19200000>, <200000000>;
2388 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
2392 interrupt-names = "hs_phy_irq",
2397 power-domains = <&gcc USB30_SEC_GDSC>;
2403 interconnect-names = "usb-ddr", "apps-usb";
2413 phy-names = "usb2-phy", "usb3-phy";
2417 mdss: display-subsystem@ae00000 {
2418 compatible = "qcom,sm8350-mdss";
2420 reg-names = "mdss";
2424 interconnect-names = "mdp0-mem", "mdp1-mem";
2426 power-domains = <&dispcc MDSS_GDSC>;
2433 clock-names = "iface", "bus", "nrt_bus", "core";
2436 interrupt-controller;
2437 #interrupt-cells = <1>;
2443 #address-cells = <2>;
2444 #size-cells = <2>;
2447 mdss_mdp: display-controller@ae01000 {
2448 compatible = "qcom,sm8350-dpu";
2451 reg-names = "mdp", "vbif";
2459 clock-names = "bus",
2466 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2467 assigned-clock-rates = <19200000>;
2469 operating-points-v2 = <&dpu_opp_table>;
2470 power-domains = <&rpmhpd RPMHPD_MMCX>;
2472 interrupt-parent = <&mdss>;
2475 dpu_opp_table: opp-table {
2476 compatible = "operating-points-v2";
2478 /* TODO: opp-200000000 should work with
2483 opp-200000000 {
2484 opp-hz = /bits/ 64 <200000000>;
2485 required-opps = <&rpmhpd_opp_svs>;
2488 opp-300000000 {
2489 opp-hz = /bits/ 64 <300000000>;
2490 required-opps = <&rpmhpd_opp_svs>;
2493 opp-345000000 {
2494 opp-hz = /bits/ 64 <345000000>;
2495 required-opps = <&rpmhpd_opp_svs_l1>;
2498 opp-460000000 {
2499 opp-hz = /bits/ 64 <460000000>;
2500 required-opps = <&rpmhpd_opp_nom>;
2505 #address-cells = <1>;
2506 #size-cells = <0>;
2511 remote-endpoint = <&mdss_dsi0_in>;
2518 remote-endpoint = <&mdss_dsi1_in>;
2525 remote-endpoint = <&mdss_dp_in>;
2531 mdss_dp: displayport-controller@ae90000 {
2532 compatible = "qcom,sm8350-dp";
2538 interrupt-parent = <&mdss>;
2545 clock-names = "core_iface",
2551 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
2553 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
2557 phy-names = "dp";
2559 #sound-dai-cells = <0>;
2561 operating-points-v2 = <&dp_opp_table>;
2562 power-domains = <&rpmhpd RPMHPD_MMCX>;
2567 #address-cells = <1>;
2568 #size-cells = <0>;
2573 remote-endpoint = <&dpu_intf0_out>;
2578 dp_opp_table: opp-table {
2579 compatible = "operating-points-v2";
2581 opp-160000000 {
2582 opp-hz = /bits/ 64 <160000000>;
2583 required-opps = <&rpmhpd_opp_low_svs>;
2586 opp-270000000 {
2587 opp-hz = /bits/ 64 <270000000>;
2588 required-opps = <&rpmhpd_opp_svs>;
2591 opp-540000000 {
2592 opp-hz = /bits/ 64 <540000000>;
2593 required-opps = <&rpmhpd_opp_svs_l1>;
2596 opp-810000000 {
2597 opp-hz = /bits/ 64 <810000000>;
2598 required-opps = <&rpmhpd_opp_nom>;
2604 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2606 reg-names = "dsi_ctrl";
2608 interrupt-parent = <&mdss>;
2617 clock-names = "byte",
2624 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
2626 assigned-clock-parents = <&mdss_dsi0_phy 0>,
2629 operating-points-v2 = <&dsi0_opp_table>;
2630 power-domains = <&rpmhpd RPMHPD_MMCX>;
2634 #address-cells = <1>;
2635 #size-cells = <0>;
2639 dsi0_opp_table: opp-table {
2640 compatible = "operating-points-v2";
2642 /* TODO: opp-187500000 should work with
2647 opp-187500000 {
2648 opp-hz = /bits/ 64 <187500000>;
2649 required-opps = <&rpmhpd_opp_svs>;
2652 opp-300000000 {
2653 opp-hz = /bits/ 64 <300000000>;
2654 required-opps = <&rpmhpd_opp_svs>;
2657 opp-358000000 {
2658 opp-hz = /bits/ 64 <358000000>;
2659 required-opps = <&rpmhpd_opp_svs_l1>;
2664 #address-cells = <1>;
2665 #size-cells = <0>;
2670 remote-endpoint = <&dpu_intf1_out>;
2683 compatible = "qcom,sm8350-dsi-phy-5nm";
2687 reg-names = "dsi_phy",
2691 #clock-cells = <1>;
2692 #phy-cells = <0>;
2696 clock-names = "iface", "ref";
2702 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2704 reg-names = "dsi_ctrl";
2706 interrupt-parent = <&mdss>;
2715 clock-names = "byte",
2722 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
2724 assigned-clock-parents = <&mdss_dsi1_phy 0>,
2727 operating-points-v2 = <&dsi1_opp_table>;
2728 power-domains = <&rpmhpd RPMHPD_MMCX>;
2732 #address-cells = <1>;
2733 #size-cells = <0>;
2737 dsi1_opp_table: opp-table {
2738 compatible = "operating-points-v2";
2740 /* TODO: opp-187500000 should work with
2745 opp-187500000 {
2746 opp-hz = /bits/ 64 <187500000>;
2747 required-opps = <&rpmhpd_opp_svs>;
2750 opp-300000000 {
2751 opp-hz = /bits/ 64 <300000000>;
2752 required-opps = <&rpmhpd_opp_svs>;
2755 opp-358000000 {
2756 opp-hz = /bits/ 64 <358000000>;
2757 required-opps = <&rpmhpd_opp_svs_l1>;
2762 #address-cells = <1>;
2763 #size-cells = <0>;
2768 remote-endpoint = <&dpu_intf2_out>;
2781 compatible = "qcom,sm8350-dsi-phy-5nm";
2785 reg-names = "dsi_phy",
2789 #clock-cells = <1>;
2790 #phy-cells = <0>;
2794 clock-names = "iface", "ref";
2800 dispcc: clock-controller@af00000 {
2801 compatible = "qcom,sm8350-dispcc";
2808 clock-names = "bi_tcxo",
2815 #clock-cells = <1>;
2816 #reset-cells = <1>;
2817 #power-domain-cells = <1>;
2819 power-domains = <&rpmhpd RPMHPD_MMCX>;
2822 pdc: interrupt-controller@b220000 {
2823 compatible = "qcom,sm8350-pdc", "qcom,pdc";
2825 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>,
2829 #interrupt-cells = <2>;
2830 interrupt-parent = <&intc>;
2831 interrupt-controller;
2834 tsens0: thermal-sensor@c263000 {
2835 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
2839 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
2841 interrupt-names = "uplow", "critical";
2842 #thermal-sensor-cells = <1>;
2845 tsens1: thermal-sensor@c265000 {
2846 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
2850 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
2852 interrupt-names = "uplow", "critical";
2853 #thermal-sensor-cells = <1>;
2856 aoss_qmp: power-management@c300000 {
2857 compatible = "qcom,sm8350-aoss-qmp", "qcom,aoss-qmp";
2859 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
2863 #clock-cells = <0>;
2867 compatible = "qcom,rpmh-stats";
2872 compatible = "qcom,spmi-pmic-arb";
2878 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
2879 interrupt-names = "periph_irq";
2880 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
2883 #address-cells = <2>;
2884 #size-cells = <0>;
2885 interrupt-controller;
2886 #interrupt-cells = <4>;
2890 compatible = "qcom,sm8350-tlmm";
2893 gpio-controller;
2894 #gpio-cells = <2>;
2895 interrupt-controller;
2896 #interrupt-cells = <2>;
2897 gpio-ranges = <&tlmm 0 0 204>;
2898 wakeup-parent = <&pdc>;
2900 sdc2_default_state: sdc2-default-state {
2901 clk-pins {
2903 drive-strength = <16>;
2904 bias-disable;
2907 cmd-pins {
2909 drive-strength = <16>;
2910 bias-pull-up;
2913 data-pins {
2915 drive-strength = <16>;
2916 bias-pull-up;
2920 sdc2_sleep_state: sdc2-sleep-state {
2921 clk-pins {
2923 drive-strength = <2>;
2924 bias-disable;
2927 cmd-pins {
2929 drive-strength = <2>;
2930 bias-pull-up;
2933 data-pins {
2935 drive-strength = <2>;
2936 bias-pull-up;
2940 qup_uart3_default_state: qup-uart3-default-state {
2941 rx-pins {
2945 tx-pins {
2951 qup_uart6_default: qup-uart6-default-state {
2954 drive-strength = <2>;
2955 bias-disable;
2958 qup_uart18_default: qup-uart18-default-state {
2961 drive-strength = <2>;
2962 bias-disable;
2965 qup_i2c0_default: qup-i2c0-default-state {
2968 drive-strength = <2>;
2969 bias-pull-up;
2972 qup_i2c1_default: qup-i2c1-default-state {
2975 drive-strength = <2>;
2976 bias-pull-up;
2979 qup_i2c2_default: qup-i2c2-default-state {
2982 drive-strength = <2>;
2983 bias-pull-up;
2986 qup_i2c4_default: qup-i2c4-default-state {
2989 drive-strength = <2>;
2990 bias-pull-up;
2993 qup_i2c5_default: qup-i2c5-default-state {
2996 drive-strength = <2>;
2997 bias-pull-up;
3000 qup_i2c6_default: qup-i2c6-default-state {
3003 drive-strength = <2>;
3004 bias-pull-up;
3007 qup_i2c7_default: qup-i2c7-default-state {
3010 drive-strength = <2>;
3011 bias-disable;
3014 qup_i2c8_default: qup-i2c8-default-state {
3017 drive-strength = <2>;
3018 bias-pull-up;
3021 qup_i2c9_default: qup-i2c9-default-state {
3024 drive-strength = <2>;
3025 bias-pull-up;
3028 qup_i2c10_default: qup-i2c10-default-state {
3031 drive-strength = <2>;
3032 bias-pull-up;
3035 qup_i2c11_default: qup-i2c11-default-state {
3038 drive-strength = <2>;
3039 bias-pull-up;
3042 qup_i2c12_default: qup-i2c12-default-state {
3045 drive-strength = <2>;
3046 bias-pull-up;
3049 qup_i2c13_default: qup-i2c13-default-state {
3052 drive-strength = <2>;
3053 bias-pull-up;
3056 qup_i2c14_default: qup-i2c14-default-state {
3059 drive-strength = <2>;
3060 bias-disable;
3063 qup_i2c15_default: qup-i2c15-default-state {
3066 drive-strength = <2>;
3067 bias-disable;
3070 qup_i2c16_default: qup-i2c16-default-state {
3073 drive-strength = <2>;
3074 bias-disable;
3077 qup_i2c17_default: qup-i2c17-default-state {
3080 drive-strength = <2>;
3081 bias-disable;
3084 qup_i2c19_default: qup-i2c19-default-state {
3087 drive-strength = <2>;
3088 bias-disable;
3093 compatible = "qcom,sm8350-smmu-500", "arm,mmu-500";
3095 #iommu-cells = <2>;
3096 #global-interrupts = <2>;
3198 compatible = "qcom,sm8350-adsp-pas";
3201 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
3206 interrupt-names = "wdog", "fatal", "ready",
3207 "handover", "stop-ack";
3210 clock-names = "xo";
3212 power-domains = <&rpmhpd RPMHPD_LCX>,
3214 power-domain-names = "lcx", "lmx";
3216 memory-region = <&pil_adsp_mem>;
3220 qcom,smem-states = <&smp2p_adsp_out 0>;
3221 qcom,smem-state-names = "stop";
3225 glink-edge {
3226 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
3233 qcom,remote-pid = <2>;
3236 compatible = "qcom,apr-v2";
3237 qcom,glink-channels = "apr_audio_svc";
3239 #address-cells = <1>;
3240 #size-cells = <0>;
3245 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3251 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3254 compatible = "qcom,q6afe-dais";
3255 #address-cells = <1>;
3256 #size-cells = <0>;
3257 #sound-dai-cells = <1>;
3260 q6afecc: clock-controller {
3261 compatible = "qcom,q6afe-clocks";
3262 #clock-cells = <2>;
3269 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3272 compatible = "qcom,q6asm-dais";
3273 #address-cells = <1>;
3274 #size-cells = <0>;
3275 #sound-dai-cells = <1>;
3295 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3298 compatible = "qcom,q6adm-routing";
3299 #sound-dai-cells = <0>;
3306 qcom,glink-channels = "fastrpcglink-apps-dsp";
3308 qcom,non-secure-domain;
3309 #address-cells = <1>;
3310 #size-cells = <0>;
3312 compute-cb@3 {
3313 compatible = "qcom,fastrpc-compute-cb";
3318 compute-cb@4 {
3319 compatible = "qcom,fastrpc-compute-cb";
3324 compute-cb@5 {
3325 compatible = "qcom,fastrpc-compute-cb";
3333 intc: interrupt-controller@17a00000 {
3334 compatible = "arm,gic-v3";
3335 #interrupt-cells = <3>;
3336 interrupt-controller;
3337 #redistributor-regions = <1>;
3338 redistributor-stride = <0 0x20000>;
3345 compatible = "arm,armv7-timer-mem";
3346 #address-cells = <1>;
3347 #size-cells = <1>;
3350 clock-frequency = <19200000>;
3353 frame-number = <0>;
3361 frame-number = <1>;
3368 frame-number = <2>;
3375 frame-number = <3>;
3382 frame-number = <4>;
3389 frame-number = <5>;
3396 frame-number = <6>;
3405 compatible = "qcom,rpmh-rsc";
3409 reg-names = "drv-0", "drv-1", "drv-2";
3413 qcom,tcs-offset = <0xd00>;
3414 qcom,drv-id = <2>;
3415 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
3417 power-domains = <&CLUSTER_PD>;
3419 rpmhcc: clock-controller {
3420 compatible = "qcom,sm8350-rpmh-clk";
3421 #clock-cells = <1>;
3422 clock-names = "xo";
3426 rpmhpd: power-controller {
3427 compatible = "qcom,sm8350-rpmhpd";
3428 #power-domain-cells = <1>;
3429 operating-points-v2 = <&rpmhpd_opp_table>;
3431 rpmhpd_opp_table: opp-table {
3432 compatible = "operating-points-v2";
3435 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3439 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3443 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3447 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3451 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3455 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3459 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3463 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3467 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3471 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3476 apps_bcm_voter: bcm-voter {
3477 compatible = "qcom,bcm-voter";
3482 compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss";
3486 reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
3491 interrupt-names = "dcvsh-irq-0",
3492 "dcvsh-irq-1",
3493 "dcvsh-irq-2";
3496 clock-names = "xo", "alternate";
3498 #freq-domain-cells = <1>;
3499 #clock-cells = <1>;
3503 compatible = "qcom,sm8350-cdsp-pas";
3506 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
3511 interrupt-names = "wdog", "fatal", "ready",
3512 "handover", "stop-ack";
3515 clock-names = "xo";
3517 power-domains = <&rpmhpd RPMHPD_CX>,
3519 power-domain-names = "cx", "mxc";
3523 memory-region = <&pil_cdsp_mem>;
3527 qcom,smem-states = <&smp2p_cdsp_out 0>;
3528 qcom,smem-state-names = "stop";
3532 glink-edge {
3533 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
3540 qcom,remote-pid = <5>;
3544 qcom,glink-channels = "fastrpcglink-apps-dsp";
3546 qcom,non-secure-domain;
3547 #address-cells = <1>;
3548 #size-cells = <0>;
3550 compute-cb@1 {
3551 compatible = "qcom,fastrpc-compute-cb";
3557 compute-cb@2 {
3558 compatible = "qcom,fastrpc-compute-cb";
3564 compute-cb@3 {
3565 compatible = "qcom,fastrpc-compute-cb";
3571 compute-cb@4 {
3572 compatible = "qcom,fastrpc-compute-cb";
3578 compute-cb@5 {
3579 compatible = "qcom,fastrpc-compute-cb";
3585 compute-cb@6 {
3586 compatible = "qcom,fastrpc-compute-cb";
3592 compute-cb@7 {
3593 compatible = "qcom,fastrpc-compute-cb";
3599 compute-cb@8 {
3600 compatible = "qcom,fastrpc-compute-cb";
3612 thermal_zones: thermal-zones {
3613 cpu0-thermal {
3614 polling-delay-passive = <250>;
3615 polling-delay = <1000>;
3617 thermal-sensors = <&tsens0 1>;
3620 cpu0_alert0: trip-point0 {
3626 cpu0_alert1: trip-point1 {
3632 cpu0_crit: cpu-crit {
3639 cooling-maps {
3642 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3649 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3657 cpu1-thermal {
3658 polling-delay-passive = <250>;
3659 polling-delay = <1000>;
3661 thermal-sensors = <&tsens0 2>;
3664 cpu1_alert0: trip-point0 {
3670 cpu1_alert1: trip-point1 {
3676 cpu1_crit: cpu-crit {
3683 cooling-maps {
3686 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3693 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3701 cpu2-thermal {
3702 polling-delay-passive = <250>;
3703 polling-delay = <1000>;
3705 thermal-sensors = <&tsens0 3>;
3708 cpu2_alert0: trip-point0 {
3714 cpu2_alert1: trip-point1 {
3720 cpu2_crit: cpu-crit {
3727 cooling-maps {
3730 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3737 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3745 cpu3-thermal {
3746 polling-delay-passive = <250>;
3747 polling-delay = <1000>;
3749 thermal-sensors = <&tsens0 4>;
3752 cpu3_alert0: trip-point0 {
3758 cpu3_alert1: trip-point1 {
3764 cpu3_crit: cpu-crit {
3771 cooling-maps {
3774 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3781 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3789 cpu4-top-thermal {
3790 polling-delay-passive = <250>;
3791 polling-delay = <1000>;
3793 thermal-sensors = <&tsens0 7>;
3796 cpu4_top_alert0: trip-point0 {
3802 cpu4_top_alert1: trip-point1 {
3808 cpu4_top_crit: cpu-crit {
3815 cooling-maps {
3818 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3825 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3833 cpu5-top-thermal {
3834 polling-delay-passive = <250>;
3835 polling-delay = <1000>;
3837 thermal-sensors = <&tsens0 8>;
3840 cpu5_top_alert0: trip-point0 {
3846 cpu5_top_alert1: trip-point1 {
3852 cpu5_top_crit: cpu-crit {
3859 cooling-maps {
3862 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3869 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3877 cpu6-top-thermal {
3878 polling-delay-passive = <250>;
3879 polling-delay = <1000>;
3881 thermal-sensors = <&tsens0 9>;
3884 cpu6_top_alert0: trip-point0 {
3890 cpu6_top_alert1: trip-point1 {
3896 cpu6_top_crit: cpu-crit {
3903 cooling-maps {
3906 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3913 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3921 cpu7-top-thermal {
3922 polling-delay-passive = <250>;
3923 polling-delay = <1000>;
3925 thermal-sensors = <&tsens0 10>;
3928 cpu7_top_alert0: trip-point0 {
3934 cpu7_top_alert1: trip-point1 {
3940 cpu7_top_crit: cpu-crit {
3947 cooling-maps {
3950 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3957 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3965 cpu4-bottom-thermal {
3966 polling-delay-passive = <250>;
3967 polling-delay = <1000>;
3969 thermal-sensors = <&tsens0 11>;
3972 cpu4_bottom_alert0: trip-point0 {
3978 cpu4_bottom_alert1: trip-point1 {
3984 cpu4_bottom_crit: cpu-crit {
3991 cooling-maps {
3994 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4001 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4009 cpu5-bottom-thermal {
4010 polling-delay-passive = <250>;
4011 polling-delay = <1000>;
4013 thermal-sensors = <&tsens0 12>;
4016 cpu5_bottom_alert0: trip-point0 {
4022 cpu5_bottom_alert1: trip-point1 {
4028 cpu5_bottom_crit: cpu-crit {
4035 cooling-maps {
4038 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4045 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4053 cpu6-bottom-thermal {
4054 polling-delay-passive = <250>;
4055 polling-delay = <1000>;
4057 thermal-sensors = <&tsens0 13>;
4060 cpu6_bottom_alert0: trip-point0 {
4066 cpu6_bottom_alert1: trip-point1 {
4072 cpu6_bottom_crit: cpu-crit {
4079 cooling-maps {
4082 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4089 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4097 cpu7-bottom-thermal {
4098 polling-delay-passive = <250>;
4099 polling-delay = <1000>;
4101 thermal-sensors = <&tsens0 14>;
4104 cpu7_bottom_alert0: trip-point0 {
4110 cpu7_bottom_alert1: trip-point1 {
4116 cpu7_bottom_crit: cpu-crit {
4123 cooling-maps {
4126 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4133 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4141 aoss0-thermal {
4142 polling-delay-passive = <250>;
4143 polling-delay = <1000>;
4145 thermal-sensors = <&tsens0 0>;
4148 aoss0_alert0: trip-point0 {
4156 cluster0-thermal {
4157 polling-delay-passive = <250>;
4158 polling-delay = <1000>;
4160 thermal-sensors = <&tsens0 5>;
4163 cluster0_alert0: trip-point0 {
4176 cluster1-thermal {
4177 polling-delay-passive = <250>;
4178 polling-delay = <1000>;
4180 thermal-sensors = <&tsens0 6>;
4183 cluster1_alert0: trip-point0 {
4196 aoss1-thermal {
4197 polling-delay-passive = <250>;
4198 polling-delay = <1000>;
4200 thermal-sensors = <&tsens1 0>;
4203 aoss1_alert0: trip-point0 {
4211 gpu-top-thermal {
4212 polling-delay-passive = <250>;
4213 polling-delay = <1000>;
4215 thermal-sensors = <&tsens1 1>;
4218 gpu1_alert0: trip-point0 {
4226 gpu-bottom-thermal {
4227 polling-delay-passive = <250>;
4228 polling-delay = <1000>;
4230 thermal-sensors = <&tsens1 2>;
4233 gpu2_alert0: trip-point0 {
4241 nspss1-thermal {
4242 polling-delay-passive = <250>;
4243 polling-delay = <1000>;
4245 thermal-sensors = <&tsens1 3>;
4248 nspss1_alert0: trip-point0 {
4256 nspss2-thermal {
4257 polling-delay-passive = <250>;
4258 polling-delay = <1000>;
4260 thermal-sensors = <&tsens1 4>;
4263 nspss2_alert0: trip-point0 {
4271 nspss3-thermal {
4272 polling-delay-passive = <250>;
4273 polling-delay = <1000>;
4275 thermal-sensors = <&tsens1 5>;
4278 nspss3_alert0: trip-point0 {
4286 video-thermal {
4287 polling-delay-passive = <250>;
4288 polling-delay = <1000>;
4290 thermal-sensors = <&tsens1 6>;
4293 video_alert0: trip-point0 {
4301 mem-thermal {
4302 polling-delay-passive = <250>;
4303 polling-delay = <1000>;
4305 thermal-sensors = <&tsens1 7>;
4308 mem_alert0: trip-point0 {
4316 modem1-top-thermal {
4317 polling-delay-passive = <250>;
4318 polling-delay = <1000>;
4320 thermal-sensors = <&tsens1 8>;
4323 modem1_alert0: trip-point0 {
4331 modem2-top-thermal {
4332 polling-delay-passive = <250>;
4333 polling-delay = <1000>;
4335 thermal-sensors = <&tsens1 9>;
4338 modem2_alert0: trip-point0 {
4346 modem3-top-thermal {
4347 polling-delay-passive = <250>;
4348 polling-delay = <1000>;
4350 thermal-sensors = <&tsens1 10>;
4353 modem3_alert0: trip-point0 {
4361 modem4-top-thermal {
4362 polling-delay-passive = <250>;
4363 polling-delay = <1000>;
4365 thermal-sensors = <&tsens1 11>;
4368 modem4_alert0: trip-point0 {
4376 camera-top-thermal {
4377 polling-delay-passive = <250>;
4378 polling-delay = <1000>;
4380 thermal-sensors = <&tsens1 12>;
4383 camera1_alert0: trip-point0 {
4391 cam-bottom-thermal {
4392 polling-delay-passive = <250>;
4393 polling-delay = <1000>;
4395 thermal-sensors = <&tsens1 13>;
4398 camera2_alert0: trip-point0 {
4408 compatible = "arm,armv8-timer";