Lines Matching +full:1 +full:c25000
138 clocks = <&cpufreq_hw 1>;
141 qcom,freq-domain = <&cpufreq_hw 1>;
157 clocks = <&cpufreq_hw 1>;
160 qcom,freq-domain = <&cpufreq_hw 1>;
176 clocks = <&cpufreq_hw 1>;
179 qcom,freq-domain = <&cpufreq_hw 1>;
259 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
279 CLUSTER_SLEEP_AOSS_SLEEP: cluster-sleep-1 {
293 #reset-cells = <1>;
507 qcom,client-id = <1>;
556 #qcom,smem-state-cells = <1>;
580 #qcom,smem-state-cells = <1>;
600 qcom,remote-pid = <1>;
604 #qcom,smem-state-cells = <1>;
615 #qcom,smem-state-cells = <1>;
639 #qcom,smem-state-cells = <1>;
659 #clock-cells = <1>;
660 #reset-cells = <1>;
661 #power-domain-cells = <1>;
682 <&ufs_mem_phy 1>,
740 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
742 #address-cells = <1>;
756 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
758 #address-cells = <1>;
771 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
772 <&gpi_dma2 1 1 QCOM_GPI_I2C>;
774 #address-cells = <1>;
787 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
788 <&gpi_dma2 1 1 QCOM_GPI_SPI>;
790 #address-cells = <1>;
804 <&gpi_dma2 1 2 QCOM_GPI_I2C>;
806 #address-cells = <1>;
820 <&gpi_dma2 1 2 QCOM_GPI_SPI>;
822 #address-cells = <1>;
836 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
838 #address-cells = <1>;
852 <&gpi_dma2 1 3 QCOM_GPI_SPI>;
854 #address-cells = <1>;
870 <&gpi_dma2 1 4 QCOM_GPI_SPI>;
872 #address-cells = <1>;
899 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
901 #address-cells = <1>;
915 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
917 #address-cells = <1>;
966 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
968 #address-cells = <1>;
982 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
984 #address-cells = <1>;
997 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
998 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1000 #address-cells = <1>;
1013 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1014 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1016 #address-cells = <1>;
1030 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1032 #address-cells = <1>;
1046 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1048 #address-cells = <1>;
1077 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1079 #address-cells = <1>;
1093 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1095 #address-cells = <1>;
1109 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1111 #address-cells = <1>;
1125 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1127 #address-cells = <1>;
1141 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1143 #address-cells = <1>;
1157 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1159 #address-cells = <1>;
1173 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1175 #address-cells = <1>;
1202 <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1204 #address-cells = <1>;
1218 <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1220 #address-cells = <1>;
1269 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1271 #address-cells = <1>;
1285 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1287 #address-cells = <1>;
1300 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1301 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1303 #address-cells = <1>;
1316 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1317 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1319 #address-cells = <1>;
1333 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1335 #address-cells = <1>;
1349 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1351 #address-cells = <1>;
1365 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1367 #address-cells = <1>;
1381 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1383 #address-cells = <1>;
1397 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1399 #address-cells = <1>;
1413 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1415 #address-cells = <1>;
1429 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1431 #address-cells = <1>;
1445 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1447 #address-cells = <1>;
1502 pcie0: pcie@1c00000 {
1513 num-lanes = <1>;
1531 #interrupt-cells = <1>;
1533 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1571 pcie0_phy: phy@1c06000 {
1595 pcie1: pcie@1c08000 {
1604 linux,pci-domain = <1>;
1616 #interrupt-cells = <1>;
1618 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1654 pcie1_phy: phy@1c0e000 {
1678 ufs_mem_hc: ufshc@1d84000 {
1686 #reset-cells = <1>;
1725 ufs_mem_phy: phy@1d87000 {
1737 #clock-cells = <1>;
1743 cryptobam: dma-controller@1dc4000 {
1747 #dma-cells = <1>;
1756 crypto: crypto@1dfa000 {
1769 ipa: ipa@1e40000 {
1784 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
1801 <&ipa_smp2p_out 1>;
1808 tcsr_mutex: hwlock@1f40000 {
1811 #hwlock-cells = <1>;
1814 tcsr: syscon@1fc0000 {
1845 iommus = <&adreno_smmu 0 0x400>, <&adreno_smmu 1 0x400>;
1968 #clock-cells = <1>;
1969 #reset-cells = <1>;
1970 #power-domain-cells = <1>;
2024 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
2056 qcom,remote-pid = <1>;
2066 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
2103 #address-cells = <1>;
2106 compute-cb@1 {
2108 reg = <1>;
2207 #clock-cells = <1>;
2208 #phy-cells = <1>;
2213 #address-cells = <1>;
2223 port@1 {
2224 reg = <1>;
2343 #address-cells = <1>;
2353 port@1 {
2354 reg = <1>;
2437 #interrupt-cells = <1>;
2505 #address-cells = <1>;
2515 port@1 {
2516 reg = <1>;
2567 #address-cells = <1>;
2627 <&mdss_dsi0_phy 1>;
2634 #address-cells = <1>;
2664 #address-cells = <1>;
2674 port@1 {
2675 reg = <1>;
2691 #clock-cells = <1>;
2725 <&mdss_dsi1_phy 1>;
2732 #address-cells = <1>;
2762 #address-cells = <1>;
2772 port@1 {
2773 reg = <1>;
2789 #clock-cells = <1>;
2804 <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>,
2805 <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>,
2815 #clock-cells = <1>;
2816 #reset-cells = <1>;
2817 #power-domain-cells = <1>;
2825 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>,
2827 <69 86 1>, <70 520 54>, <124 609 31>, <155 63 1>,
2842 #thermal-sensor-cells = <1>;
2853 #thermal-sensor-cells = <1>;
2880 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3203 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
3239 #address-cells = <1>;
3255 #address-cells = <1>;
3257 #sound-dai-cells = <1>;
3273 #address-cells = <1>;
3275 #sound-dai-cells = <1>;
3282 dai@1 {
3283 reg = <1>;
3309 #address-cells = <1>;
3337 #redistributor-regions = <1>;
3346 #address-cells = <1>;
3347 #size-cells = <1>;
3361 frame-number = <1>;
3367 frame@17c25000 {
3409 reg-names = "drv-0", "drv-1", "drv-2";
3421 #clock-cells = <1>;
3428 #power-domain-cells = <1>;
3492 "dcvsh-irq-1",
3498 #freq-domain-cells = <1>;
3499 #clock-cells = <1>;
3508 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
3547 #address-cells = <1>;
3550 compute-cb@1 {
3552 reg = <1>;
3617 thermal-sensors = <&tsens0 1>;
4215 thermal-sensors = <&tsens1 1>;