Lines Matching +full:dmic01 +full:- +full:state
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
8 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
9 #include <dt-bindings/clock/qcom,gpucc-sm8250.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/clock/qcom,sm8250-lpass-aoncc.h>
12 #include <dt-bindings/clock/qcom,sm8250-lpass-audiocc.h>
13 #include <dt-bindings/dma/qcom-gpi.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/interconnect/qcom,osm-l3.h>
16 #include <dt-bindings/interconnect/qcom,sm8250.h>
17 #include <dt-bindings/mailbox/qcom-ipcc.h>
18 #include <dt-bindings/phy/phy-qcom-qmp.h>
19 #include <dt-bindings/power/qcom-rpmpd.h>
20 #include <dt-bindings/power/qcom,rpmhpd.h>
21 #include <dt-bindings/soc/qcom,apr.h>
22 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
23 #include <dt-bindings/sound/qcom,q6afe.h>
24 #include <dt-bindings/thermal/thermal.h>
25 #include <dt-bindings/clock/qcom,camcc-sm8250.h>
26 #include <dt-bindings/clock/qcom,videocc-sm8250.h>
29 interrupt-parent = <&intc>;
31 #address-cells = <2>;
32 #size-cells = <2>;
80 xo_board: xo-board {
81 compatible = "fixed-clock";
82 #clock-cells = <0>;
83 clock-frequency = <38400000>;
84 clock-output-names = "xo_board";
87 sleep_clk: sleep-clk {
88 compatible = "fixed-clock";
89 clock-frequency = <32768>;
90 #clock-cells = <0>;
95 #address-cells = <2>;
96 #size-cells = <0>;
103 enable-method = "psci";
104 capacity-dmips-mhz = <448>;
105 dynamic-power-coefficient = <105>;
106 next-level-cache = <&L2_0>;
107 power-domains = <&CPU_PD0>;
108 power-domain-names = "psci";
109 qcom,freq-domain = <&cpufreq_hw 0>;
110 operating-points-v2 = <&cpu0_opp_table>;
113 #cooling-cells = <2>;
114 L2_0: l2-cache {
116 cache-level = <2>;
117 cache-size = <0x20000>;
118 cache-unified;
119 next-level-cache = <&L3_0>;
120 L3_0: l3-cache {
122 cache-level = <3>;
123 cache-size = <0x400000>;
124 cache-unified;
134 enable-method = "psci";
135 capacity-dmips-mhz = <448>;
136 dynamic-power-coefficient = <105>;
137 next-level-cache = <&L2_100>;
138 power-domains = <&CPU_PD1>;
139 power-domain-names = "psci";
140 qcom,freq-domain = <&cpufreq_hw 0>;
141 operating-points-v2 = <&cpu0_opp_table>;
144 #cooling-cells = <2>;
145 L2_100: l2-cache {
147 cache-level = <2>;
148 cache-size = <0x20000>;
149 cache-unified;
150 next-level-cache = <&L3_0>;
159 enable-method = "psci";
160 capacity-dmips-mhz = <448>;
161 dynamic-power-coefficient = <105>;
162 next-level-cache = <&L2_200>;
163 power-domains = <&CPU_PD2>;
164 power-domain-names = "psci";
165 qcom,freq-domain = <&cpufreq_hw 0>;
166 operating-points-v2 = <&cpu0_opp_table>;
169 #cooling-cells = <2>;
170 L2_200: l2-cache {
172 cache-level = <2>;
173 cache-size = <0x20000>;
174 cache-unified;
175 next-level-cache = <&L3_0>;
184 enable-method = "psci";
185 capacity-dmips-mhz = <448>;
186 dynamic-power-coefficient = <105>;
187 next-level-cache = <&L2_300>;
188 power-domains = <&CPU_PD3>;
189 power-domain-names = "psci";
190 qcom,freq-domain = <&cpufreq_hw 0>;
191 operating-points-v2 = <&cpu0_opp_table>;
194 #cooling-cells = <2>;
195 L2_300: l2-cache {
197 cache-level = <2>;
198 cache-size = <0x20000>;
199 cache-unified;
200 next-level-cache = <&L3_0>;
209 enable-method = "psci";
210 capacity-dmips-mhz = <1024>;
211 dynamic-power-coefficient = <379>;
212 next-level-cache = <&L2_400>;
213 power-domains = <&CPU_PD4>;
214 power-domain-names = "psci";
215 qcom,freq-domain = <&cpufreq_hw 1>;
216 operating-points-v2 = <&cpu4_opp_table>;
219 #cooling-cells = <2>;
220 L2_400: l2-cache {
222 cache-level = <2>;
223 cache-size = <0x40000>;
224 cache-unified;
225 next-level-cache = <&L3_0>;
234 enable-method = "psci";
235 capacity-dmips-mhz = <1024>;
236 dynamic-power-coefficient = <379>;
237 next-level-cache = <&L2_500>;
238 power-domains = <&CPU_PD5>;
239 power-domain-names = "psci";
240 qcom,freq-domain = <&cpufreq_hw 1>;
241 operating-points-v2 = <&cpu4_opp_table>;
244 #cooling-cells = <2>;
245 L2_500: l2-cache {
247 cache-level = <2>;
248 cache-size = <0x40000>;
249 cache-unified;
250 next-level-cache = <&L3_0>;
259 enable-method = "psci";
260 capacity-dmips-mhz = <1024>;
261 dynamic-power-coefficient = <379>;
262 next-level-cache = <&L2_600>;
263 power-domains = <&CPU_PD6>;
264 power-domain-names = "psci";
265 qcom,freq-domain = <&cpufreq_hw 1>;
266 operating-points-v2 = <&cpu4_opp_table>;
269 #cooling-cells = <2>;
270 L2_600: l2-cache {
272 cache-level = <2>;
273 cache-size = <0x40000>;
274 cache-unified;
275 next-level-cache = <&L3_0>;
284 enable-method = "psci";
285 capacity-dmips-mhz = <1024>;
286 dynamic-power-coefficient = <444>;
287 next-level-cache = <&L2_700>;
288 power-domains = <&CPU_PD7>;
289 power-domain-names = "psci";
290 qcom,freq-domain = <&cpufreq_hw 2>;
291 operating-points-v2 = <&cpu7_opp_table>;
294 #cooling-cells = <2>;
295 L2_700: l2-cache {
297 cache-level = <2>;
298 cache-size = <0x80000>;
299 cache-unified;
300 next-level-cache = <&L3_0>;
304 cpu-map {
340 idle-states {
341 entry-method = "psci";
343 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
344 compatible = "arm,idle-state";
345 idle-state-name = "silver-rail-power-collapse";
346 arm,psci-suspend-param = <0x40000004>;
347 entry-latency-us = <360>;
348 exit-latency-us = <531>;
349 min-residency-us = <3934>;
350 local-timer-stop;
353 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
354 compatible = "arm,idle-state";
355 idle-state-name = "gold-rail-power-collapse";
356 arm,psci-suspend-param = <0x40000004>;
357 entry-latency-us = <702>;
358 exit-latency-us = <1061>;
359 min-residency-us = <4488>;
360 local-timer-stop;
364 domain-idle-states {
365 CLUSTER_SLEEP_0: cluster-sleep-0 {
366 compatible = "domain-idle-state";
367 arm,psci-suspend-param = <0x4100c244>;
368 entry-latency-us = <3264>;
369 exit-latency-us = <6562>;
370 min-residency-us = <9987>;
375 qup_virt: interconnect-qup-virt {
376 compatible = "qcom,sm8250-qup-virt";
377 #interconnect-cells = <2>;
378 qcom,bcm-voters = <&apps_bcm_voter>;
381 cpu0_opp_table: opp-table-cpu0 {
382 compatible = "operating-points-v2";
383 opp-shared;
385 cpu0_opp1: opp-300000000 {
386 opp-hz = /bits/ 64 <300000000>;
387 opp-peak-kBps = <800000 9600000>;
390 cpu0_opp2: opp-403200000 {
391 opp-hz = /bits/ 64 <403200000>;
392 opp-peak-kBps = <800000 9600000>;
395 cpu0_opp3: opp-518400000 {
396 opp-hz = /bits/ 64 <518400000>;
397 opp-peak-kBps = <800000 16588800>;
400 cpu0_opp4: opp-614400000 {
401 opp-hz = /bits/ 64 <614400000>;
402 opp-peak-kBps = <800000 16588800>;
405 cpu0_opp5: opp-691200000 {
406 opp-hz = /bits/ 64 <691200000>;
407 opp-peak-kBps = <800000 19660800>;
410 cpu0_opp6: opp-787200000 {
411 opp-hz = /bits/ 64 <787200000>;
412 opp-peak-kBps = <1804000 19660800>;
415 cpu0_opp7: opp-883200000 {
416 opp-hz = /bits/ 64 <883200000>;
417 opp-peak-kBps = <1804000 23347200>;
420 cpu0_opp8: opp-979200000 {
421 opp-hz = /bits/ 64 <979200000>;
422 opp-peak-kBps = <1804000 26419200>;
425 cpu0_opp9: opp-1075200000 {
426 opp-hz = /bits/ 64 <1075200000>;
427 opp-peak-kBps = <1804000 29491200>;
430 cpu0_opp10: opp-1171200000 {
431 opp-hz = /bits/ 64 <1171200000>;
432 opp-peak-kBps = <1804000 32563200>;
435 cpu0_opp11: opp-1248000000 {
436 opp-hz = /bits/ 64 <1248000000>;
437 opp-peak-kBps = <1804000 36249600>;
440 cpu0_opp12: opp-1344000000 {
441 opp-hz = /bits/ 64 <1344000000>;
442 opp-peak-kBps = <2188000 36249600>;
445 cpu0_opp13: opp-1420800000 {
446 opp-hz = /bits/ 64 <1420800000>;
447 opp-peak-kBps = <2188000 39321600>;
450 cpu0_opp14: opp-1516800000 {
451 opp-hz = /bits/ 64 <1516800000>;
452 opp-peak-kBps = <3072000 42393600>;
455 cpu0_opp15: opp-1612800000 {
456 opp-hz = /bits/ 64 <1612800000>;
457 opp-peak-kBps = <3072000 42393600>;
460 cpu0_opp16: opp-1708800000 {
461 opp-hz = /bits/ 64 <1708800000>;
462 opp-peak-kBps = <4068000 42393600>;
465 cpu0_opp17: opp-1804800000 {
466 opp-hz = /bits/ 64 <1804800000>;
467 opp-peak-kBps = <4068000 42393600>;
471 cpu4_opp_table: opp-table-cpu4 {
472 compatible = "operating-points-v2";
473 opp-shared;
475 cpu4_opp1: opp-710400000 {
476 opp-hz = /bits/ 64 <710400000>;
477 opp-peak-kBps = <1804000 19660800>;
480 cpu4_opp2: opp-825600000 {
481 opp-hz = /bits/ 64 <825600000>;
482 opp-peak-kBps = <2188000 23347200>;
485 cpu4_opp3: opp-940800000 {
486 opp-hz = /bits/ 64 <940800000>;
487 opp-peak-kBps = <2188000 26419200>;
490 cpu4_opp4: opp-1056000000 {
491 opp-hz = /bits/ 64 <1056000000>;
492 opp-peak-kBps = <3072000 26419200>;
495 cpu4_opp5: opp-1171200000 {
496 opp-hz = /bits/ 64 <1171200000>;
497 opp-peak-kBps = <3072000 29491200>;
500 cpu4_opp6: opp-1286400000 {
501 opp-hz = /bits/ 64 <1286400000>;
502 opp-peak-kBps = <4068000 29491200>;
505 cpu4_opp7: opp-1382400000 {
506 opp-hz = /bits/ 64 <1382400000>;
507 opp-peak-kBps = <4068000 32563200>;
510 cpu4_opp8: opp-1478400000 {
511 opp-hz = /bits/ 64 <1478400000>;
512 opp-peak-kBps = <4068000 32563200>;
515 cpu4_opp9: opp-1574400000 {
516 opp-hz = /bits/ 64 <1574400000>;
517 opp-peak-kBps = <5412000 39321600>;
520 cpu4_opp10: opp-1670400000 {
521 opp-hz = /bits/ 64 <1670400000>;
522 opp-peak-kBps = <5412000 42393600>;
525 cpu4_opp11: opp-1766400000 {
526 opp-hz = /bits/ 64 <1766400000>;
527 opp-peak-kBps = <5412000 45465600>;
530 cpu4_opp12: opp-1862400000 {
531 opp-hz = /bits/ 64 <1862400000>;
532 opp-peak-kBps = <6220000 45465600>;
535 cpu4_opp13: opp-1958400000 {
536 opp-hz = /bits/ 64 <1958400000>;
537 opp-peak-kBps = <6220000 48537600>;
540 cpu4_opp14: opp-2054400000 {
541 opp-hz = /bits/ 64 <2054400000>;
542 opp-peak-kBps = <7216000 48537600>;
545 cpu4_opp15: opp-2150400000 {
546 opp-hz = /bits/ 64 <2150400000>;
547 opp-peak-kBps = <7216000 51609600>;
550 cpu4_opp16: opp-2246400000 {
551 opp-hz = /bits/ 64 <2246400000>;
552 opp-peak-kBps = <7216000 51609600>;
555 cpu4_opp17: opp-2342400000 {
556 opp-hz = /bits/ 64 <2342400000>;
557 opp-peak-kBps = <8368000 51609600>;
560 cpu4_opp18: opp-2419200000 {
561 opp-hz = /bits/ 64 <2419200000>;
562 opp-peak-kBps = <8368000 51609600>;
566 cpu7_opp_table: opp-table-cpu7 {
567 compatible = "operating-points-v2";
568 opp-shared;
570 cpu7_opp1: opp-844800000 {
571 opp-hz = /bits/ 64 <844800000>;
572 opp-peak-kBps = <2188000 19660800>;
575 cpu7_opp2: opp-960000000 {
576 opp-hz = /bits/ 64 <960000000>;
577 opp-peak-kBps = <2188000 26419200>;
580 cpu7_opp3: opp-1075200000 {
581 opp-hz = /bits/ 64 <1075200000>;
582 opp-peak-kBps = <3072000 26419200>;
585 cpu7_opp4: opp-1190400000 {
586 opp-hz = /bits/ 64 <1190400000>;
587 opp-peak-kBps = <3072000 29491200>;
590 cpu7_opp5: opp-1305600000 {
591 opp-hz = /bits/ 64 <1305600000>;
592 opp-peak-kBps = <4068000 32563200>;
595 cpu7_opp6: opp-1401600000 {
596 opp-hz = /bits/ 64 <1401600000>;
597 opp-peak-kBps = <4068000 32563200>;
600 cpu7_opp7: opp-1516800000 {
601 opp-hz = /bits/ 64 <1516800000>;
602 opp-peak-kBps = <4068000 36249600>;
605 cpu7_opp8: opp-1632000000 {
606 opp-hz = /bits/ 64 <1632000000>;
607 opp-peak-kBps = <5412000 39321600>;
610 cpu7_opp9: opp-1747200000 {
611 opp-hz = /bits/ 64 <1708800000>;
612 opp-peak-kBps = <5412000 42393600>;
615 cpu7_opp10: opp-1862400000 {
616 opp-hz = /bits/ 64 <1862400000>;
617 opp-peak-kBps = <6220000 45465600>;
620 cpu7_opp11: opp-1977600000 {
621 opp-hz = /bits/ 64 <1977600000>;
622 opp-peak-kBps = <6220000 48537600>;
625 cpu7_opp12: opp-2073600000 {
626 opp-hz = /bits/ 64 <2073600000>;
627 opp-peak-kBps = <7216000 48537600>;
630 cpu7_opp13: opp-2169600000 {
631 opp-hz = /bits/ 64 <2169600000>;
632 opp-peak-kBps = <7216000 51609600>;
635 cpu7_opp14: opp-2265600000 {
636 opp-hz = /bits/ 64 <2265600000>;
637 opp-peak-kBps = <7216000 51609600>;
640 cpu7_opp15: opp-2361600000 {
641 opp-hz = /bits/ 64 <2361600000>;
642 opp-peak-kBps = <8368000 51609600>;
645 cpu7_opp16: opp-2457600000 {
646 opp-hz = /bits/ 64 <2457600000>;
647 opp-peak-kBps = <8368000 51609600>;
650 cpu7_opp17: opp-2553600000 {
651 opp-hz = /bits/ 64 <2553600000>;
652 opp-peak-kBps = <8368000 51609600>;
655 cpu7_opp18: opp-2649600000 {
656 opp-hz = /bits/ 64 <2649600000>;
657 opp-peak-kBps = <8368000 51609600>;
660 cpu7_opp19: opp-2745600000 {
661 opp-hz = /bits/ 64 <2745600000>;
662 opp-peak-kBps = <8368000 51609600>;
665 cpu7_opp20: opp-2841600000 {
666 opp-hz = /bits/ 64 <2841600000>;
667 opp-peak-kBps = <8368000 51609600>;
673 compatible = "qcom,scm-sm8250", "qcom,scm";
674 qcom,dload-mode = <&tcsr 0x13000>;
675 #reset-cells = <1>;
686 compatible = "arm,armv8-pmuv3";
691 compatible = "arm,psci-1.0";
694 CPU_PD0: power-domain-cpu0 {
695 #power-domain-cells = <0>;
696 power-domains = <&CLUSTER_PD>;
697 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
700 CPU_PD1: power-domain-cpu1 {
701 #power-domain-cells = <0>;
702 power-domains = <&CLUSTER_PD>;
703 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
706 CPU_PD2: power-domain-cpu2 {
707 #power-domain-cells = <0>;
708 power-domains = <&CLUSTER_PD>;
709 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
712 CPU_PD3: power-domain-cpu3 {
713 #power-domain-cells = <0>;
714 power-domains = <&CLUSTER_PD>;
715 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
718 CPU_PD4: power-domain-cpu4 {
719 #power-domain-cells = <0>;
720 power-domains = <&CLUSTER_PD>;
721 domain-idle-states = <&BIG_CPU_SLEEP_0>;
724 CPU_PD5: power-domain-cpu5 {
725 #power-domain-cells = <0>;
726 power-domains = <&CLUSTER_PD>;
727 domain-idle-states = <&BIG_CPU_SLEEP_0>;
730 CPU_PD6: power-domain-cpu6 {
731 #power-domain-cells = <0>;
732 power-domains = <&CLUSTER_PD>;
733 domain-idle-states = <&BIG_CPU_SLEEP_0>;
736 CPU_PD7: power-domain-cpu7 {
737 #power-domain-cells = <0>;
738 power-domains = <&CLUSTER_PD>;
739 domain-idle-states = <&BIG_CPU_SLEEP_0>;
742 CLUSTER_PD: power-domain-cpu-cluster0 {
743 #power-domain-cells = <0>;
744 domain-idle-states = <&CLUSTER_SLEEP_0>;
748 qup_opp_table: opp-table-qup {
749 compatible = "operating-points-v2";
751 opp-50000000 {
752 opp-hz = /bits/ 64 <50000000>;
753 required-opps = <&rpmhpd_opp_min_svs>;
756 opp-75000000 {
757 opp-hz = /bits/ 64 <75000000>;
758 required-opps = <&rpmhpd_opp_low_svs>;
761 opp-120000000 {
762 opp-hz = /bits/ 64 <120000000>;
763 required-opps = <&rpmhpd_opp_svs>;
767 reserved-memory {
768 #address-cells = <2>;
769 #size-cells = <2>;
774 no-map;
779 no-map;
783 compatible = "qcom,cmd-db";
785 no-map;
790 no-map;
795 no-map;
800 no-map;
805 no-map;
810 no-map;
815 no-map;
820 no-map;
825 no-map;
830 no-map;
835 no-map;
840 no-map;
845 no-map;
850 no-map;
855 no-map;
860 no-map;
866 memory-region = <&smem_mem>;
870 smp2p-adsp {
873 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
879 qcom,local-pid = <0>;
880 qcom,remote-pid = <2>;
882 smp2p_adsp_out: master-kernel {
883 qcom,entry-name = "master-kernel";
884 #qcom,smem-state-cells = <1>;
887 smp2p_adsp_in: slave-kernel {
888 qcom,entry-name = "slave-kernel";
889 interrupt-controller;
890 #interrupt-cells = <2>;
894 smp2p-cdsp {
897 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
903 qcom,local-pid = <0>;
904 qcom,remote-pid = <5>;
906 smp2p_cdsp_out: master-kernel {
907 qcom,entry-name = "master-kernel";
908 #qcom,smem-state-cells = <1>;
911 smp2p_cdsp_in: slave-kernel {
912 qcom,entry-name = "slave-kernel";
913 interrupt-controller;
914 #interrupt-cells = <2>;
918 smp2p-slpi {
921 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
927 qcom,local-pid = <0>;
928 qcom,remote-pid = <3>;
930 smp2p_slpi_out: master-kernel {
931 qcom,entry-name = "master-kernel";
932 #qcom,smem-state-cells = <1>;
935 smp2p_slpi_in: slave-kernel {
936 qcom,entry-name = "slave-kernel";
937 interrupt-controller;
938 #interrupt-cells = <2>;
943 #address-cells = <2>;
944 #size-cells = <2>;
946 dma-ranges = <0 0 0 0 0x10 0>;
947 compatible = "simple-bus";
949 gcc: clock-controller@100000 {
950 compatible = "qcom,gcc-sm8250";
952 #clock-cells = <1>;
953 #reset-cells = <1>;
954 #power-domain-cells = <1>;
955 clock-names = "bi_tcxo",
964 compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
967 interrupt-controller;
968 #interrupt-cells = <3>;
969 #mbox-cells = <2>;
973 compatible = "qcom,sm8250-qfprom", "qcom,qfprom";
975 #address-cells = <1>;
976 #size-cells = <1>;
985 compatible = "qcom,prng-ee";
988 clock-names = "core";
991 gpi_dma2: dma-controller@800000 {
992 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma";
1004 dma-channels = <10>;
1005 dma-channel-mask = <0x3f>;
1007 #dma-cells = <3>;
1012 compatible = "qcom,geni-se-qup";
1014 clock-names = "m-ahb", "s-ahb";
1017 #address-cells = <2>;
1018 #size-cells = <2>;
1024 compatible = "qcom,geni-i2c";
1026 clock-names = "se";
1028 pinctrl-names = "default";
1029 pinctrl-0 = <&qup_i2c14_default>;
1033 dma-names = "tx", "rx";
1034 power-domains = <&rpmhpd SM8250_CX>;
1038 interconnect-names = "qup-core",
1039 "qup-config",
1040 "qup-memory";
1041 #address-cells = <1>;
1042 #size-cells = <0>;
1047 compatible = "qcom,geni-spi";
1049 clock-names = "se";
1054 dma-names = "tx", "rx";
1055 power-domains = <&rpmhpd RPMHPD_CX>;
1056 operating-points-v2 = <&qup_opp_table>;
1060 interconnect-names = "qup-core",
1061 "qup-config",
1062 "qup-memory";
1063 #address-cells = <1>;
1064 #size-cells = <0>;
1069 compatible = "qcom,geni-i2c";
1071 clock-names = "se";
1073 pinctrl-names = "default";
1074 pinctrl-0 = <&qup_i2c15_default>;
1078 dma-names = "tx", "rx";
1079 power-domains = <&rpmhpd SM8250_CX>;
1083 interconnect-names = "qup-core",
1084 "qup-config",
1085 "qup-memory";
1086 #address-cells = <1>;
1087 #size-cells = <0>;
1092 compatible = "qcom,geni-spi";
1094 clock-names = "se";
1099 dma-names = "tx", "rx";
1100 power-domains = <&rpmhpd RPMHPD_CX>;
1101 operating-points-v2 = <&qup_opp_table>;
1105 interconnect-names = "qup-core",
1106 "qup-config",
1107 "qup-memory";
1108 #address-cells = <1>;
1109 #size-cells = <0>;
1114 compatible = "qcom,geni-i2c";
1116 clock-names = "se";
1118 pinctrl-names = "default";
1119 pinctrl-0 = <&qup_i2c16_default>;
1123 dma-names = "tx", "rx";
1124 power-domains = <&rpmhpd SM8250_CX>;
1128 interconnect-names = "qup-core",
1129 "qup-config",
1130 "qup-memory";
1131 #address-cells = <1>;
1132 #size-cells = <0>;
1137 compatible = "qcom,geni-spi";
1139 clock-names = "se";
1144 dma-names = "tx", "rx";
1145 power-domains = <&rpmhpd RPMHPD_CX>;
1146 operating-points-v2 = <&qup_opp_table>;
1150 interconnect-names = "qup-core",
1151 "qup-config",
1152 "qup-memory";
1153 #address-cells = <1>;
1154 #size-cells = <0>;
1159 compatible = "qcom,geni-i2c";
1161 clock-names = "se";
1163 pinctrl-names = "default";
1164 pinctrl-0 = <&qup_i2c17_default>;
1168 dma-names = "tx", "rx";
1169 power-domains = <&rpmhpd SM8250_CX>;
1173 interconnect-names = "qup-core",
1174 "qup-config",
1175 "qup-memory";
1176 #address-cells = <1>;
1177 #size-cells = <0>;
1182 compatible = "qcom,geni-spi";
1184 clock-names = "se";
1189 dma-names = "tx", "rx";
1190 power-domains = <&rpmhpd RPMHPD_CX>;
1191 operating-points-v2 = <&qup_opp_table>;
1195 interconnect-names = "qup-core",
1196 "qup-config",
1197 "qup-memory";
1198 #address-cells = <1>;
1199 #size-cells = <0>;
1204 compatible = "qcom,geni-uart";
1206 clock-names = "se";
1208 pinctrl-names = "default";
1209 pinctrl-0 = <&qup_uart17_default>;
1211 power-domains = <&rpmhpd RPMHPD_CX>;
1212 operating-points-v2 = <&qup_opp_table>;
1215 interconnect-names = "qup-core",
1216 "qup-config";
1221 compatible = "qcom,geni-i2c";
1223 clock-names = "se";
1225 pinctrl-names = "default";
1226 pinctrl-0 = <&qup_i2c18_default>;
1230 dma-names = "tx", "rx";
1231 power-domains = <&rpmhpd SM8250_CX>;
1235 interconnect-names = "qup-core",
1236 "qup-config",
1237 "qup-memory";
1238 #address-cells = <1>;
1239 #size-cells = <0>;
1244 compatible = "qcom,geni-spi";
1246 clock-names = "se";
1251 dma-names = "tx", "rx";
1252 power-domains = <&rpmhpd RPMHPD_CX>;
1253 operating-points-v2 = <&qup_opp_table>;
1257 interconnect-names = "qup-core",
1258 "qup-config",
1259 "qup-memory";
1260 #address-cells = <1>;
1261 #size-cells = <0>;
1266 compatible = "qcom,geni-uart";
1268 clock-names = "se";
1270 pinctrl-names = "default";
1271 pinctrl-0 = <&qup_uart18_default>;
1273 power-domains = <&rpmhpd RPMHPD_CX>;
1274 operating-points-v2 = <&qup_opp_table>;
1277 interconnect-names = "qup-core",
1278 "qup-config";
1283 compatible = "qcom,geni-i2c";
1285 clock-names = "se";
1287 pinctrl-names = "default";
1288 pinctrl-0 = <&qup_i2c19_default>;
1292 dma-names = "tx", "rx";
1293 power-domains = <&rpmhpd SM8250_CX>;
1297 interconnect-names = "qup-core",
1298 "qup-config",
1299 "qup-memory";
1300 #address-cells = <1>;
1301 #size-cells = <0>;
1306 compatible = "qcom,geni-spi";
1308 clock-names = "se";
1313 dma-names = "tx", "rx";
1314 power-domains = <&rpmhpd RPMHPD_CX>;
1315 operating-points-v2 = <&qup_opp_table>;
1319 interconnect-names = "qup-core",
1320 "qup-config",
1321 "qup-memory";
1322 #address-cells = <1>;
1323 #size-cells = <0>;
1328 gpi_dma0: dma-controller@900000 {
1329 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma";
1344 dma-channels = <15>;
1345 dma-channel-mask = <0x7ff>;
1347 #dma-cells = <3>;
1352 compatible = "qcom,geni-se-qup";
1354 clock-names = "m-ahb", "s-ahb";
1357 #address-cells = <2>;
1358 #size-cells = <2>;
1364 compatible = "qcom,geni-i2c";
1366 clock-names = "se";
1368 pinctrl-names = "default";
1369 pinctrl-0 = <&qup_i2c0_default>;
1373 dma-names = "tx", "rx";
1374 power-domains = <&rpmhpd SM8250_CX>;
1378 interconnect-names = "qup-core",
1379 "qup-config",
1380 "qup-memory";
1381 #address-cells = <1>;
1382 #size-cells = <0>;
1387 compatible = "qcom,geni-spi";
1389 clock-names = "se";
1394 dma-names = "tx", "rx";
1395 power-domains = <&rpmhpd RPMHPD_CX>;
1396 operating-points-v2 = <&qup_opp_table>;
1400 interconnect-names = "qup-core",
1401 "qup-config",
1402 "qup-memory";
1403 #address-cells = <1>;
1404 #size-cells = <0>;
1409 compatible = "qcom,geni-i2c";
1411 clock-names = "se";
1413 pinctrl-names = "default";
1414 pinctrl-0 = <&qup_i2c1_default>;
1418 dma-names = "tx", "rx";
1419 power-domains = <&rpmhpd SM8250_CX>;
1423 interconnect-names = "qup-core",
1424 "qup-config",
1425 "qup-memory";
1426 #address-cells = <1>;
1427 #size-cells = <0>;
1432 compatible = "qcom,geni-spi";
1434 clock-names = "se";
1439 dma-names = "tx", "rx";
1440 power-domains = <&rpmhpd RPMHPD_CX>;
1441 operating-points-v2 = <&qup_opp_table>;
1445 interconnect-names = "qup-core",
1446 "qup-config",
1447 "qup-memory";
1448 #address-cells = <1>;
1449 #size-cells = <0>;
1454 compatible = "qcom,geni-i2c";
1456 clock-names = "se";
1458 pinctrl-names = "default";
1459 pinctrl-0 = <&qup_i2c2_default>;
1463 dma-names = "tx", "rx";
1464 power-domains = <&rpmhpd SM8250_CX>;
1468 interconnect-names = "qup-core",
1469 "qup-config",
1470 "qup-memory";
1471 #address-cells = <1>;
1472 #size-cells = <0>;
1477 compatible = "qcom,geni-spi";
1479 clock-names = "se";
1484 dma-names = "tx", "rx";
1485 power-domains = <&rpmhpd RPMHPD_CX>;
1486 operating-points-v2 = <&qup_opp_table>;
1490 interconnect-names = "qup-core",
1491 "qup-config",
1492 "qup-memory";
1493 #address-cells = <1>;
1494 #size-cells = <0>;
1499 compatible = "qcom,geni-debug-uart";
1501 clock-names = "se";
1503 pinctrl-names = "default";
1504 pinctrl-0 = <&qup_uart2_default>;
1506 power-domains = <&rpmhpd RPMHPD_CX>;
1507 operating-points-v2 = <&qup_opp_table>;
1510 interconnect-names = "qup-core",
1511 "qup-config";
1516 compatible = "qcom,geni-i2c";
1518 clock-names = "se";
1520 pinctrl-names = "default";
1521 pinctrl-0 = <&qup_i2c3_default>;
1525 dma-names = "tx", "rx";
1526 power-domains = <&rpmhpd SM8250_CX>;
1530 interconnect-names = "qup-core",
1531 "qup-config",
1532 "qup-memory";
1533 #address-cells = <1>;
1534 #size-cells = <0>;
1539 compatible = "qcom,geni-spi";
1541 clock-names = "se";
1546 dma-names = "tx", "rx";
1547 power-domains = <&rpmhpd RPMHPD_CX>;
1548 operating-points-v2 = <&qup_opp_table>;
1552 interconnect-names = "qup-core",
1553 "qup-config",
1554 "qup-memory";
1555 #address-cells = <1>;
1556 #size-cells = <0>;
1561 compatible = "qcom,geni-i2c";
1563 clock-names = "se";
1565 pinctrl-names = "default";
1566 pinctrl-0 = <&qup_i2c4_default>;
1570 dma-names = "tx", "rx";
1571 power-domains = <&rpmhpd SM8250_CX>;
1575 interconnect-names = "qup-core",
1576 "qup-config",
1577 "qup-memory";
1578 #address-cells = <1>;
1579 #size-cells = <0>;
1584 compatible = "qcom,geni-spi";
1586 clock-names = "se";
1591 dma-names = "tx", "rx";
1592 power-domains = <&rpmhpd RPMHPD_CX>;
1593 operating-points-v2 = <&qup_opp_table>;
1597 interconnect-names = "qup-core",
1598 "qup-config",
1599 "qup-memory";
1600 #address-cells = <1>;
1601 #size-cells = <0>;
1606 compatible = "qcom,geni-i2c";
1608 clock-names = "se";
1610 pinctrl-names = "default";
1611 pinctrl-0 = <&qup_i2c5_default>;
1615 dma-names = "tx", "rx";
1616 power-domains = <&rpmhpd SM8250_CX>;
1620 interconnect-names = "qup-core",
1621 "qup-config",
1622 "qup-memory";
1623 #address-cells = <1>;
1624 #size-cells = <0>;
1629 compatible = "qcom,geni-spi";
1631 clock-names = "se";
1636 dma-names = "tx", "rx";
1637 power-domains = <&rpmhpd RPMHPD_CX>;
1638 operating-points-v2 = <&qup_opp_table>;
1642 interconnect-names = "qup-core",
1643 "qup-config",
1644 "qup-memory";
1645 #address-cells = <1>;
1646 #size-cells = <0>;
1651 compatible = "qcom,geni-i2c";
1653 clock-names = "se";
1655 pinctrl-names = "default";
1656 pinctrl-0 = <&qup_i2c6_default>;
1660 dma-names = "tx", "rx";
1661 power-domains = <&rpmhpd SM8250_CX>;
1665 interconnect-names = "qup-core",
1666 "qup-config",
1667 "qup-memory";
1668 #address-cells = <1>;
1669 #size-cells = <0>;
1674 compatible = "qcom,geni-spi";
1676 clock-names = "se";
1681 dma-names = "tx", "rx";
1682 power-domains = <&rpmhpd RPMHPD_CX>;
1683 operating-points-v2 = <&qup_opp_table>;
1687 interconnect-names = "qup-core",
1688 "qup-config",
1689 "qup-memory";
1690 #address-cells = <1>;
1691 #size-cells = <0>;
1696 compatible = "qcom,geni-uart";
1698 clock-names = "se";
1700 pinctrl-names = "default";
1701 pinctrl-0 = <&qup_uart6_default>;
1703 power-domains = <&rpmhpd RPMHPD_CX>;
1704 operating-points-v2 = <&qup_opp_table>;
1707 interconnect-names = "qup-core",
1708 "qup-config";
1713 compatible = "qcom,geni-i2c";
1715 clock-names = "se";
1717 pinctrl-names = "default";
1718 pinctrl-0 = <&qup_i2c7_default>;
1722 dma-names = "tx", "rx";
1723 power-domains = <&rpmhpd SM8250_CX>;
1727 interconnect-names = "qup-core",
1728 "qup-config",
1729 "qup-memory";
1730 #address-cells = <1>;
1731 #size-cells = <0>;
1736 compatible = "qcom,geni-spi";
1738 clock-names = "se";
1743 dma-names = "tx", "rx";
1744 power-domains = <&rpmhpd RPMHPD_CX>;
1745 operating-points-v2 = <&qup_opp_table>;
1749 interconnect-names = "qup-core",
1750 "qup-config",
1751 "qup-memory";
1752 #address-cells = <1>;
1753 #size-cells = <0>;
1758 gpi_dma1: dma-controller@a00000 {
1759 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma";
1771 dma-channels = <10>;
1772 dma-channel-mask = <0x3f>;
1774 #dma-cells = <3>;
1779 compatible = "qcom,geni-se-qup";
1781 clock-names = "m-ahb", "s-ahb";
1784 #address-cells = <2>;
1785 #size-cells = <2>;
1791 compatible = "qcom,geni-i2c";
1793 clock-names = "se";
1795 pinctrl-names = "default";
1796 pinctrl-0 = <&qup_i2c8_default>;
1800 dma-names = "tx", "rx";
1801 power-domains = <&rpmhpd SM8250_CX>;
1805 interconnect-names = "qup-core",
1806 "qup-config",
1807 "qup-memory";
1808 #address-cells = <1>;
1809 #size-cells = <0>;
1814 compatible = "qcom,geni-spi";
1816 clock-names = "se";
1821 dma-names = "tx", "rx";
1822 power-domains = <&rpmhpd RPMHPD_CX>;
1823 operating-points-v2 = <&qup_opp_table>;
1827 interconnect-names = "qup-core",
1828 "qup-config",
1829 "qup-memory";
1830 #address-cells = <1>;
1831 #size-cells = <0>;
1836 compatible = "qcom,geni-i2c";
1838 clock-names = "se";
1840 pinctrl-names = "default";
1841 pinctrl-0 = <&qup_i2c9_default>;
1845 dma-names = "tx", "rx";
1846 power-domains = <&rpmhpd SM8250_CX>;
1850 interconnect-names = "qup-core",
1851 "qup-config",
1852 "qup-memory";
1853 #address-cells = <1>;
1854 #size-cells = <0>;
1859 compatible = "qcom,geni-spi";
1861 clock-names = "se";
1866 dma-names = "tx", "rx";
1867 power-domains = <&rpmhpd RPMHPD_CX>;
1868 operating-points-v2 = <&qup_opp_table>;
1872 interconnect-names = "qup-core",
1873 "qup-config",
1874 "qup-memory";
1875 #address-cells = <1>;
1876 #size-cells = <0>;
1881 compatible = "qcom,geni-i2c";
1883 clock-names = "se";
1885 pinctrl-names = "default";
1886 pinctrl-0 = <&qup_i2c10_default>;
1890 dma-names = "tx", "rx";
1891 power-domains = <&rpmhpd SM8250_CX>;
1895 interconnect-names = "qup-core",
1896 "qup-config",
1897 "qup-memory";
1898 #address-cells = <1>;
1899 #size-cells = <0>;
1904 compatible = "qcom,geni-spi";
1906 clock-names = "se";
1911 dma-names = "tx", "rx";
1912 power-domains = <&rpmhpd RPMHPD_CX>;
1913 operating-points-v2 = <&qup_opp_table>;
1917 interconnect-names = "qup-core",
1918 "qup-config",
1919 "qup-memory";
1920 #address-cells = <1>;
1921 #size-cells = <0>;
1926 compatible = "qcom,geni-i2c";
1928 clock-names = "se";
1930 pinctrl-names = "default";
1931 pinctrl-0 = <&qup_i2c11_default>;
1935 dma-names = "tx", "rx";
1936 power-domains = <&rpmhpd SM8250_CX>;
1940 interconnect-names = "qup-core",
1941 "qup-config",
1942 "qup-memory";
1943 #address-cells = <1>;
1944 #size-cells = <0>;
1949 compatible = "qcom,geni-spi";
1951 clock-names = "se";
1956 dma-names = "tx", "rx";
1957 power-domains = <&rpmhpd RPMHPD_CX>;
1958 operating-points-v2 = <&qup_opp_table>;
1962 interconnect-names = "qup-core",
1963 "qup-config",
1964 "qup-memory";
1965 #address-cells = <1>;
1966 #size-cells = <0>;
1971 compatible = "qcom,geni-i2c";
1973 clock-names = "se";
1975 pinctrl-names = "default";
1976 pinctrl-0 = <&qup_i2c12_default>;
1980 dma-names = "tx", "rx";
1981 power-domains = <&rpmhpd SM8250_CX>;
1985 interconnect-names = "qup-core",
1986 "qup-config",
1987 "qup-memory";
1988 #address-cells = <1>;
1989 #size-cells = <0>;
1994 compatible = "qcom,geni-spi";
1996 clock-names = "se";
2001 dma-names = "tx", "rx";
2002 power-domains = <&rpmhpd RPMHPD_CX>;
2003 operating-points-v2 = <&qup_opp_table>;
2007 interconnect-names = "qup-core",
2008 "qup-config",
2009 "qup-memory";
2010 #address-cells = <1>;
2011 #size-cells = <0>;
2016 compatible = "qcom,geni-debug-uart";
2018 clock-names = "se";
2020 pinctrl-names = "default";
2021 pinctrl-0 = <&qup_uart12_default>;
2023 power-domains = <&rpmhpd RPMHPD_CX>;
2024 operating-points-v2 = <&qup_opp_table>;
2027 interconnect-names = "qup-core",
2028 "qup-config";
2033 compatible = "qcom,geni-i2c";
2035 clock-names = "se";
2037 pinctrl-names = "default";
2038 pinctrl-0 = <&qup_i2c13_default>;
2042 dma-names = "tx", "rx";
2043 power-domains = <&rpmhpd SM8250_CX>;
2047 interconnect-names = "qup-core",
2048 "qup-config",
2049 "qup-memory";
2050 #address-cells = <1>;
2051 #size-cells = <0>;
2056 compatible = "qcom,geni-spi";
2058 clock-names = "se";
2063 dma-names = "tx", "rx";
2064 power-domains = <&rpmhpd RPMHPD_CX>;
2065 operating-points-v2 = <&qup_opp_table>;
2069 interconnect-names = "qup-core",
2070 "qup-config",
2071 "qup-memory";
2072 #address-cells = <1>;
2073 #size-cells = <0>;
2079 compatible = "qcom,sm8250-config-noc";
2081 #interconnect-cells = <2>;
2082 qcom,bcm-voters = <&apps_bcm_voter>;
2086 compatible = "qcom,sm8250-system-noc";
2088 #interconnect-cells = <2>;
2089 qcom,bcm-voters = <&apps_bcm_voter>;
2093 compatible = "qcom,sm8250-mc-virt";
2095 #interconnect-cells = <2>;
2096 qcom,bcm-voters = <&apps_bcm_voter>;
2100 compatible = "qcom,sm8250-aggre1-noc";
2102 #interconnect-cells = <2>;
2103 qcom,bcm-voters = <&apps_bcm_voter>;
2107 compatible = "qcom,sm8250-aggre2-noc";
2109 #interconnect-cells = <2>;
2110 qcom,bcm-voters = <&apps_bcm_voter>;
2114 compatible = "qcom,sm8250-compute-noc";
2116 #interconnect-cells = <2>;
2117 qcom,bcm-voters = <&apps_bcm_voter>;
2121 compatible = "qcom,sm8250-mmss-noc";
2123 #interconnect-cells = <2>;
2124 qcom,bcm-voters = <&apps_bcm_voter>;
2128 compatible = "qcom,pcie-sm8250";
2135 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2137 linux,pci-domain = <0>;
2138 bus-range = <0x00 0xff>;
2139 num-lanes = <1>;
2141 #address-cells = <3>;
2142 #size-cells = <2>;
2155 interrupt-names = "msi0", "msi1", "msi2", "msi3",
2157 #interrupt-cells = <1>;
2158 interrupt-map-mask = <0 0 0 0x7>;
2159 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2172 clock-names = "pipe",
2181 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
2185 reset-names = "pci";
2187 power-domains = <&gcc PCIE_0_GDSC>;
2190 phy-names = "pciephy";
2192 perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>;
2193 wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
2195 pinctrl-names = "default";
2196 pinctrl-0 = <&pcie0_default_state>;
2197 dma-coherent;
2203 compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy";
2211 clock-names = "aux",
2217 clock-output-names = "pcie_0_pipe_clk";
2218 #clock-cells = <0>;
2220 #phy-cells = <0>;
2223 reset-names = "phy";
2225 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
2226 assigned-clock-rates = <100000000>;
2232 compatible = "qcom,pcie-sm8250";
2239 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2241 linux,pci-domain = <1>;
2242 bus-range = <0x00 0xff>;
2243 num-lanes = <2>;
2245 #address-cells = <3>;
2246 #size-cells = <2>;
2252 interrupt-names = "msi";
2253 #interrupt-cells = <1>;
2254 interrupt-map-mask = <0 0 0 0x7>;
2255 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2269 clock-names = "pipe",
2279 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2280 assigned-clock-rates = <19200000>;
2282 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2286 reset-names = "pci";
2288 power-domains = <&gcc PCIE_1_GDSC>;
2291 phy-names = "pciephy";
2293 perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>;
2294 wake-gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>;
2296 pinctrl-names = "default";
2297 pinctrl-0 = <&pcie1_default_state>;
2298 dma-coherent;
2304 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
2312 clock-names = "aux",
2318 clock-output-names = "pcie_1_pipe_clk";
2319 #clock-cells = <0>;
2321 #phy-cells = <0>;
2324 reset-names = "phy";
2326 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2327 assigned-clock-rates = <100000000>;
2333 compatible = "qcom,pcie-sm8250";
2340 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2342 linux,pci-domain = <2>;
2343 bus-range = <0x00 0xff>;
2344 num-lanes = <2>;
2346 #address-cells = <3>;
2347 #size-cells = <2>;
2353 interrupt-names = "msi";
2354 #interrupt-cells = <1>;
2355 interrupt-map-mask = <0 0 0 0x7>;
2356 interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2370 clock-names = "pipe",
2380 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>;
2381 assigned-clock-rates = <19200000>;
2383 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,
2387 reset-names = "pci";
2389 power-domains = <&gcc PCIE_2_GDSC>;
2392 phy-names = "pciephy";
2394 perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>;
2395 wake-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>;
2397 pinctrl-names = "default";
2398 pinctrl-0 = <&pcie2_default_state>;
2399 dma-coherent;
2405 compatible = "qcom,sm8250-qmp-modem-pcie-phy";
2413 clock-names = "aux",
2419 clock-output-names = "pcie_2_pipe_clk";
2420 #clock-cells = <0>;
2422 #phy-cells = <0>;
2425 reset-names = "phy";
2427 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2428 assigned-clock-rates = <100000000>;
2434 compatible = "qcom,sm8250-ufshc", "qcom,ufshc",
2435 "jedec,ufs-2.0";
2439 phy-names = "ufsphy";
2440 lanes-per-direction = <2>;
2441 #reset-cells = <1>;
2443 reset-names = "rst";
2445 power-domains = <&gcc UFS_PHY_GDSC>;
2449 clock-names =
2468 operating-points-v2 = <&ufs_opp_table>;
2472 interconnect-names = "ufs-ddr", "cpu-ufs";
2476 ufs_opp_table: opp-table {
2477 compatible = "operating-points-v2";
2479 opp-37500000 {
2480 opp-hz = /bits/ 64 <37500000>,
2488 required-opps = <&rpmhpd_opp_low_svs>;
2491 opp-300000000 {
2492 opp-hz = /bits/ 64 <300000000>,
2500 required-opps = <&rpmhpd_opp_nom>;
2506 compatible = "qcom,sm8250-qmp-ufs-phy";
2509 clock-names = "ref",
2515 reset-names = "ufsphy";
2517 #phy-cells = <0>;
2522 cryptobam: dma-controller@1dc4000 {
2523 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
2526 #dma-cells = <1>;
2528 qcom,controlled-remotely;
2529 num-channels = <8>;
2530 qcom,num-ees = <2>;
2540 compatible = "qcom,sm8250-qce", "qcom,sm8150-qce", "qcom,qce";
2543 dma-names = "rx", "tx";
2551 interconnect-names = "memory";
2555 compatible = "qcom,tcsr-mutex";
2557 #hwlock-cells = <1>;
2561 compatible = "qcom,sm8250-tcsr", "syscon";
2566 compatible = "qcom,sm8250-lpass-wsa-macro";
2575 clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen";
2577 #clock-cells = <0>;
2578 clock-output-names = "mclk";
2579 #sound-dai-cells = <1>;
2581 pinctrl-names = "default";
2582 pinctrl-0 = <&wsa_swr_active>;
2589 compatible = "qcom,soundwire-v1.5.1";
2592 clock-names = "iface";
2594 qcom,din-ports = <2>;
2595 qcom,dout-ports = <6>;
2597 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2598 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2599 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2600 qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>;
2602 #sound-dai-cells = <1>;
2603 #address-cells = <2>;
2604 #size-cells = <0>;
2609 audiocc: clock-controller@3300000 {
2610 compatible = "qcom,sm8250-lpass-audiocc";
2612 #clock-cells = <1>;
2616 clock-names = "core", "audio", "bus";
2620 compatible = "qcom,sm8250-lpass-va-macro";
2626 clock-names = "mclk", "macro", "dcodec";
2628 #clock-cells = <0>;
2629 clock-output-names = "fsgen";
2630 #sound-dai-cells = <1>;
2634 pinctrl-names = "default";
2635 pinctrl-0 = <&rx_swr_active>;
2636 compatible = "qcom,sm8250-lpass-rx-macro";
2646 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2648 #clock-cells = <0>;
2649 clock-output-names = "mclk";
2650 #sound-dai-cells = <1>;
2655 compatible = "qcom,soundwire-v1.5.1";
2659 clock-names = "iface";
2661 qcom,din-ports = <0>;
2662 qcom,dout-ports = <5>;
2664 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2665 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>;
2666 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2667 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2668 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2669 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2670 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2671 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2672 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2674 #sound-dai-cells = <1>;
2675 #address-cells = <2>;
2676 #size-cells = <0>;
2680 pinctrl-names = "default";
2681 pinctrl-0 = <&tx_swr_active>;
2682 compatible = "qcom,sm8250-lpass-tx-macro";
2692 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2694 #clock-cells = <0>;
2695 clock-output-names = "mclk";
2696 #sound-dai-cells = <1>;
2702 compatible = "qcom,soundwire-v1.5.1";
2704 interrupt-names = "core";
2708 clock-names = "iface";
2711 qcom,din-ports = <5>;
2712 qcom,dout-ports = <0>;
2713 qcom,ports-sinterval-low = /bits/ 8 <0xff 0x01 0x01 0x03 0x03>;
2714 qcom,ports-offset1 = /bits/ 8 <0xff 0x01 0x00 0x02 0x00>;
2715 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x00 0x00 0x00>;
2716 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2717 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2718 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2719 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2720 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2721 qcom,ports-lane-control = /bits/ 8 <0xff 0x00 0x01 0x00 0x01>;
2722 #sound-dai-cells = <1>;
2723 #address-cells = <2>;
2724 #size-cells = <0>;
2727 aoncc: clock-controller@3380000 {
2728 compatible = "qcom,sm8250-lpass-aoncc";
2730 #clock-cells = <1>;
2734 clock-names = "core", "audio", "bus";
2738 compatible = "qcom,sm8250-lpass-lpi-pinctrl";
2741 gpio-controller;
2742 #gpio-cells = <2>;
2743 gpio-ranges = <&lpass_tlmm 0 0 14>;
2747 clock-names = "core", "audio";
2749 wsa_swr_active: wsa-swr-active-state {
2750 clk-pins {
2753 drive-strength = <2>;
2754 slew-rate = <1>;
2755 bias-disable;
2758 data-pins {
2761 drive-strength = <2>;
2762 slew-rate = <1>;
2763 bias-bus-hold;
2767 wsa_swr_sleep: wsa-swr-sleep-state {
2768 clk-pins {
2771 drive-strength = <2>;
2772 bias-pull-down;
2775 data-pins {
2778 drive-strength = <2>;
2779 bias-pull-down;
2783 dmic01_active: dmic01-active-state {
2784 clk-pins {
2787 drive-strength = <8>;
2788 output-high;
2790 data-pins {
2793 drive-strength = <8>;
2797 dmic01_sleep: dmic01-sleep-state {
2798 clk-pins {
2801 drive-strength = <2>;
2802 bias-disable;
2803 output-low;
2806 data-pins {
2809 drive-strength = <2>;
2810 bias-pull-down;
2814 rx_swr_active: rx-swr-active-state {
2815 clk-pins {
2818 drive-strength = <2>;
2819 slew-rate = <1>;
2820 bias-disable;
2823 data-pins {
2826 drive-strength = <2>;
2827 slew-rate = <1>;
2828 bias-bus-hold;
2832 tx_swr_active: tx-swr-active-state {
2833 clk-pins {
2836 drive-strength = <2>;
2837 slew-rate = <1>;
2838 bias-disable;
2841 data-pins {
2844 drive-strength = <2>;
2845 slew-rate = <1>;
2846 bias-bus-hold;
2850 tx_swr_sleep: tx-swr-sleep-state {
2851 clk-pins {
2854 drive-strength = <2>;
2855 bias-pull-down;
2858 data1-pins {
2861 drive-strength = <2>;
2862 bias-bus-hold;
2865 data2-pins {
2868 drive-strength = <2>;
2869 bias-pull-down;
2875 compatible = "qcom,adreno-650.2",
2879 reg-names = "kgsl_3d0_reg_memory";
2885 operating-points-v2 = <&gpu_opp_table>;
2889 nvmem-cells = <&gpu_speed_bin>;
2890 nvmem-cell-names = "speed_bin";
2894 zap-shader {
2895 memory-region = <&gpu_mem>;
2898 gpu_opp_table: opp-table {
2899 compatible = "operating-points-v2";
2901 opp-670000000 {
2902 opp-hz = /bits/ 64 <670000000>;
2903 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2904 opp-supported-hw = <0xa>;
2907 opp-587000000 {
2908 opp-hz = /bits/ 64 <587000000>;
2909 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2910 opp-supported-hw = <0xb>;
2913 opp-525000000 {
2914 opp-hz = /bits/ 64 <525000000>;
2915 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2916 opp-supported-hw = <0xf>;
2919 opp-490000000 {
2920 opp-hz = /bits/ 64 <490000000>;
2921 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2922 opp-supported-hw = <0xf>;
2925 opp-441600000 {
2926 opp-hz = /bits/ 64 <441600000>;
2927 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
2928 opp-supported-hw = <0xf>;
2931 opp-400000000 {
2932 opp-hz = /bits/ 64 <400000000>;
2933 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2934 opp-supported-hw = <0xf>;
2937 opp-305000000 {
2938 opp-hz = /bits/ 64 <305000000>;
2939 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2940 opp-supported-hw = <0xf>;
2946 compatible = "qcom,adreno-gmu-650.2", "qcom,adreno-gmu";
2952 reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq";
2956 interrupt-names = "hfi", "gmu";
2963 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
2965 power-domains = <&gpucc GPU_CX_GDSC>,
2967 power-domain-names = "cx", "gx";
2971 operating-points-v2 = <&gmu_opp_table>;
2975 gmu_opp_table: opp-table {
2976 compatible = "operating-points-v2";
2978 opp-200000000 {
2979 opp-hz = /bits/ 64 <200000000>;
2980 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2985 gpucc: clock-controller@3d90000 {
2986 compatible = "qcom,sm8250-gpucc";
2991 clock-names = "bi_tcxo",
2994 #clock-cells = <1>;
2995 #reset-cells = <1>;
2996 #power-domain-cells = <1>;
3000 compatible = "qcom,sm8250-smmu-500", "qcom,adreno-smmu",
3001 "qcom,smmu-500", "arm,mmu-500";
3003 #iommu-cells = <2>;
3004 #global-interrupts = <2>;
3018 clock-names = "ahb", "bus", "iface";
3020 power-domains = <&gpucc GPU_CX_GDSC>;
3021 dma-coherent;
3025 compatible = "qcom,sm8250-slpi-pas";
3028 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
3033 interrupt-names = "wdog", "fatal", "ready",
3034 "handover", "stop-ack";
3037 clock-names = "xo";
3039 power-domains = <&rpmhpd RPMHPD_LCX>,
3041 power-domain-names = "lcx", "lmx";
3043 memory-region = <&slpi_mem>;
3047 qcom,smem-states = <&smp2p_slpi_out 0>;
3048 qcom,smem-state-names = "stop";
3052 glink-edge {
3053 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
3060 qcom,remote-pid = <3>;
3064 qcom,glink-channels = "fastrpcglink-apps-dsp";
3066 qcom,non-secure-domain;
3067 #address-cells = <1>;
3068 #size-cells = <0>;
3070 compute-cb@1 {
3071 compatible = "qcom,fastrpc-compute-cb";
3076 compute-cb@2 {
3077 compatible = "qcom,fastrpc-compute-cb";
3082 compute-cb@3 {
3083 compatible = "qcom,fastrpc-compute-cb";
3086 /* note: shared-cb = <4> in downstream */
3093 compatible = "arm,coresight-stm", "arm,primecell";
3095 reg-names = "stm-base", "stm-stimulus-base";
3098 clock-names = "apb_pclk";
3100 out-ports {
3103 remote-endpoint = <&funnel0_in7>;
3110 compatible = "qcom,coresight-tpda", "arm,primecell";
3114 clock-names = "apb_pclk";
3116 out-ports {
3120 remote-endpoint = <&funnel_qatb_in_tpda>;
3125 in-ports {
3126 #address-cells = <1>;
3127 #size-cells = <0>;
3132 remote-endpoint = <&tpdm_mm_out_tpda9>;
3139 remote-endpoint = <&tpdm_prng_out_tpda_23>;
3146 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3150 clock-names = "apb_pclk";
3152 out-ports {
3155 remote-endpoint = <&funnel_in0_in_funnel_qatb>;
3160 in-ports {
3163 remote-endpoint = <&tpda_out_funnel_qatb>;
3170 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3174 clock-names = "apb_pclk";
3176 out-ports {
3179 remote-endpoint = <&funnel_merg_in_funnel_in0>;
3184 in-ports {
3185 #address-cells = <1>;
3186 #size-cells = <0>;
3191 remote-endpoint = <&funnel_qatb_out_funnel_in0>;
3198 remote-endpoint = <&stm_out>;
3205 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3209 clock-names = "apb_pclk";
3211 out-ports {
3214 remote-endpoint = <&funnel_merg_in_funnel_in1>;
3219 in-ports {
3220 #address-cells = <1>;
3221 #size-cells = <0>;
3226 remote-endpoint = <&funnel_apss_merg_out_funnel_in1>;
3233 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3237 clock-names = "apb_pclk";
3239 out-ports {
3242 remote-endpoint = <&funnel_swao_in_funnel_merg>;
3247 in-ports {
3248 #address-cells = <1>;
3249 #size-cells = <0>;
3254 remote-endpoint = <&funnel_in0_out_funnel_merg>;
3261 remote-endpoint = <&funnel_in1_out_funnel_merg>;
3268 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3272 clock-names = "apb_pclk";
3274 out-ports {
3277 remote-endpoint = <&etr_in>;
3282 in-ports {
3285 remote-endpoint = <&replicator_swao_out_cx_in>;
3292 compatible = "arm,coresight-tmc", "arm,primecell";
3296 clock-names = "apb_pclk";
3297 arm,scatter-gather;
3299 in-ports {
3302 remote-endpoint = <&replicator_out>;
3309 compatible = "qcom,coresight-tpdm", "arm,primecell";
3313 clock-names = "apb_pclk";
3315 out-ports {
3318 remote-endpoint = <&tpda_23_in_tpdm_prng>;
3325 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3326 arm,primecell-periphid = <0x000bb908>;
3331 clock-names = "apb_pclk";
3333 out-ports {
3336 remote-endpoint = <&etf_in_funnel_swao_out>;
3341 in-ports {
3342 #address-cells = <1>;
3343 #size-cells = <0>;
3348 remote-endpoint = <&funnel_merg_out_funnel_swao>;
3355 compatible = "arm,coresight-tmc", "arm,primecell";
3359 clock-names = "apb_pclk";
3361 out-ports {
3364 remote-endpoint = <&replicator_in>;
3369 in-ports {
3373 remote-endpoint = <&funnel_swao_out_etf>;
3380 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3384 clock-names = "apb_pclk";
3386 out-ports {
3389 remote-endpoint = <&replicator_cx_in_swao_out>;
3394 in-ports {
3397 remote-endpoint = <&etf_out>;
3404 compatible = "qcom,coresight-tpdm", "arm,primecell";
3408 clock-names = "apb_pclk";
3410 out-ports {
3413 remote-endpoint = <&funnel_dl_mm_in_tpdm_mm>;
3420 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3424 clock-names = "apb_pclk";
3426 out-ports {
3429 remote-endpoint = <&funnel_dl_center_in_funnel_dl_mm>;
3434 in-ports {
3435 #address-cells = <1>;
3436 #size-cells = <0>;
3441 remote-endpoint = <&tpdm_mm_out_funnel_dl_mm>;
3448 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3452 clock-names = "apb_pclk";
3454 out-ports {
3457 remote-endpoint = <&tpda_9_in_tpdm_mm>;
3462 in-ports {
3463 #address-cells = <1>;
3464 #size-cells = <0>;
3469 remote-endpoint = <&funnel_dl_mm_out_funnel_dl_center>;
3476 compatible = "arm,coresight-etm4x", "arm,primecell";
3482 clock-names = "apb_pclk";
3483 arm,coresight-loses-context-with-cpu;
3485 out-ports {
3488 remote-endpoint = <&apss_funnel_in0>;
3495 compatible = "arm,coresight-etm4x", "arm,primecell";
3501 clock-names = "apb_pclk";
3502 arm,coresight-loses-context-with-cpu;
3504 out-ports {
3507 remote-endpoint = <&apss_funnel_in1>;
3514 compatible = "arm,coresight-etm4x", "arm,primecell";
3520 clock-names = "apb_pclk";
3521 arm,coresight-loses-context-with-cpu;
3523 out-ports {
3526 remote-endpoint = <&apss_funnel_in2>;
3533 compatible = "arm,coresight-etm4x", "arm,primecell";
3539 clock-names = "apb_pclk";
3540 arm,coresight-loses-context-with-cpu;
3542 out-ports {
3545 remote-endpoint = <&apss_funnel_in3>;
3552 compatible = "arm,coresight-etm4x", "arm,primecell";
3558 clock-names = "apb_pclk";
3559 arm,coresight-loses-context-with-cpu;
3561 out-ports {
3564 remote-endpoint = <&apss_funnel_in4>;
3571 compatible = "arm,coresight-etm4x", "arm,primecell";
3577 clock-names = "apb_pclk";
3578 arm,coresight-loses-context-with-cpu;
3580 out-ports {
3583 remote-endpoint = <&apss_funnel_in5>;
3590 compatible = "arm,coresight-etm4x", "arm,primecell";
3596 clock-names = "apb_pclk";
3597 arm,coresight-loses-context-with-cpu;
3599 out-ports {
3602 remote-endpoint = <&apss_funnel_in6>;
3609 compatible = "arm,coresight-etm4x", "arm,primecell";
3615 clock-names = "apb_pclk";
3616 arm,coresight-loses-context-with-cpu;
3618 out-ports {
3621 remote-endpoint = <&apss_funnel_in7>;
3628 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3632 clock-names = "apb_pclk";
3634 out-ports {
3637 remote-endpoint = <&funnel_apss_merg_in_funnel_apss>;
3642 in-ports {
3643 #address-cells = <1>;
3644 #size-cells = <0>;
3649 remote-endpoint = <&etm0_out>;
3656 remote-endpoint = <&etm1_out>;
3663 remote-endpoint = <&etm2_out>;
3670 remote-endpoint = <&etm3_out>;
3677 remote-endpoint = <&etm4_out>;
3684 remote-endpoint = <&etm5_out>;
3691 remote-endpoint = <&etm6_out>;
3698 remote-endpoint = <&etm7_out>;
3705 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3709 clock-names = "apb_pclk";
3711 out-ports {
3714 remote-endpoint = <&funnel_in1_in_funnel_apss_merg>;
3719 in-ports {
3722 remote-endpoint = <&funnel_apss_out_funnel_apss_merg>;
3729 compatible = "qcom,sm8250-cdsp-pas";
3732 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
3737 interrupt-names = "wdog", "fatal", "ready",
3738 "handover", "stop-ack";
3741 clock-names = "xo";
3743 power-domains = <&rpmhpd RPMHPD_CX>;
3745 memory-region = <&cdsp_mem>;
3749 qcom,smem-states = <&smp2p_cdsp_out 0>;
3750 qcom,smem-state-names = "stop";
3754 glink-edge {
3755 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
3762 qcom,remote-pid = <5>;
3766 qcom,glink-channels = "fastrpcglink-apps-dsp";
3768 qcom,non-secure-domain;
3769 #address-cells = <1>;
3770 #size-cells = <0>;
3772 compute-cb@1 {
3773 compatible = "qcom,fastrpc-compute-cb";
3778 compute-cb@2 {
3779 compatible = "qcom,fastrpc-compute-cb";
3784 compute-cb@3 {
3785 compatible = "qcom,fastrpc-compute-cb";
3790 compute-cb@4 {
3791 compatible = "qcom,fastrpc-compute-cb";
3796 compute-cb@5 {
3797 compatible = "qcom,fastrpc-compute-cb";
3802 compute-cb@6 {
3803 compatible = "qcom,fastrpc-compute-cb";
3808 compute-cb@7 {
3809 compatible = "qcom,fastrpc-compute-cb";
3814 compute-cb@8 {
3815 compatible = "qcom,fastrpc-compute-cb";
3826 compatible = "qcom,sm8250-usb-hs-phy",
3827 "qcom,usb-snps-hs-7nm-phy";
3830 #phy-cells = <0>;
3833 clock-names = "ref";
3839 compatible = "qcom,sm8250-usb-hs-phy",
3840 "qcom,usb-snps-hs-7nm-phy";
3843 #phy-cells = <0>;
3846 clock-names = "ref";
3852 compatible = "qcom,sm8250-qmp-usb3-dp-phy";
3860 clock-names = "aux",
3867 reset-names = "phy", "common";
3869 #clock-cells = <1>;
3870 #phy-cells = <1>;
3873 #address-cells = <1>;
3874 #size-cells = <0>;
3894 compatible = "qcom,sm8250-qmp-usb3-uni-phy";
3901 clock-names = "aux",
3905 clock-output-names = "usb3_uni_phy_pipe_clk_src";
3906 #clock-cells = <0>;
3907 #phy-cells = <0>;
3911 reset-names = "phy",
3918 compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
3923 interrupt-names = "hc_irq", "pwr_irq";
3928 clock-names = "iface", "core", "xo";
3930 qcom,dll-config = <0x0007642c>;
3931 qcom,ddr-config = <0x80040868>;
3932 power-domains = <&rpmhpd RPMHPD_CX>;
3933 operating-points-v2 = <&sdhc2_opp_table>;
3937 sdhc2_opp_table: opp-table {
3938 compatible = "operating-points-v2";
3940 opp-19200000 {
3941 opp-hz = /bits/ 64 <19200000>;
3942 required-opps = <&rpmhpd_opp_min_svs>;
3945 opp-50000000 {
3946 opp-hz = /bits/ 64 <50000000>;
3947 required-opps = <&rpmhpd_opp_low_svs>;
3950 opp-100000000 {
3951 opp-hz = /bits/ 64 <100000000>;
3952 required-opps = <&rpmhpd_opp_svs>;
3955 opp-202000000 {
3956 opp-hz = /bits/ 64 <202000000>;
3957 required-opps = <&rpmhpd_opp_svs_l1>;
3963 compatible = "qcom,sm8250-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
3970 operating-points-v2 = <&llcc_bwmon_opp_table>;
3972 llcc_bwmon_opp_table: opp-table {
3973 compatible = "operating-points-v2";
3975 opp-800000 {
3976 opp-peak-kBps = <(200 * 4 * 1000)>;
3979 opp-1200000 {
3980 opp-peak-kBps = <(300 * 4 * 1000)>;
3983 opp-1804000 {
3984 opp-peak-kBps = <(451 * 4 * 1000)>;
3987 opp-2188000 {
3988 opp-peak-kBps = <(547 * 4 * 1000)>;
3991 opp-2724000 {
3992 opp-peak-kBps = <(681 * 4 * 1000)>;
3995 opp-3072000 {
3996 opp-peak-kBps = <(768 * 4 * 1000)>;
3999 opp-4068000 {
4000 opp-peak-kBps = <(1017 * 4 * 1000)>;
4005 opp-6220000 {
4006 opp-peak-kBps = <(1555 * 4 * 1000)>;
4009 opp-7216000 {
4010 opp-peak-kBps = <(1804 * 4 * 1000)>;
4013 opp-8368000 {
4014 opp-peak-kBps = <(2092 * 4 * 1000)>;
4018 opp-10944000 {
4019 opp-peak-kBps = <(2736 * 4 * 1000)>;
4025 compatible = "qcom,sm8250-cpu-bwmon", "qcom,sdm845-bwmon";
4031 operating-points-v2 = <&cpu_bwmon_opp_table>;
4033 cpu_bwmon_opp_table: opp-table {
4034 compatible = "operating-points-v2";
4036 opp-800000 {
4037 opp-peak-kBps = <(200 * 4 * 1000)>;
4040 opp-1804000 {
4041 opp-peak-kBps = <(451 * 4 * 1000)>;
4044 opp-2188000 {
4045 opp-peak-kBps = <(547 * 4 * 1000)>;
4048 opp-2724000 {
4049 opp-peak-kBps = <(681 * 4 * 1000)>;
4052 opp-3072000 {
4053 opp-peak-kBps = <(768 * 4 * 1000)>;
4058 opp-6220000 {
4059 opp-peak-kBps = <(1555 * 4 * 1000)>;
4062 opp-6832000 {
4063 opp-peak-kBps = <(1708 * 4 * 1000)>;
4066 opp-8368000 {
4067 opp-peak-kBps = <(2092 * 4 * 1000)>;
4073 opp-10944000 {
4074 opp-peak-kBps = <(2736 * 4 * 1000)>;
4078 opp-12784000 {
4079 opp-peak-kBps = <(3196 * 4 * 1000)>;
4085 compatible = "qcom,sm8250-dc-noc";
4087 #interconnect-cells = <2>;
4088 qcom,bcm-voters = <&apps_bcm_voter>;
4092 compatible = "qcom,sm8250-gem-noc";
4094 #interconnect-cells = <2>;
4095 qcom,bcm-voters = <&apps_bcm_voter>;
4099 compatible = "qcom,sm8250-npu-noc";
4101 #interconnect-cells = <2>;
4102 qcom,bcm-voters = <&apps_bcm_voter>;
4106 compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
4109 #address-cells = <2>;
4110 #size-cells = <2>;
4112 dma-ranges;
4120 clock-names = "cfg_noc",
4127 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4129 assigned-clock-rates = <19200000>, <200000000>;
4131 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
4135 interrupt-names = "hs_phy_irq",
4140 power-domains = <&gcc USB30_PRIM_GDSC>;
4141 wakeup-source;
4147 interconnect-names = "usb-ddr", "apps-usb";
4157 phy-names = "usb2-phy", "usb3-phy";
4165 system-cache-controller@9200000 {
4166 compatible = "qcom,sm8250-llcc";
4170 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
4175 compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
4178 #address-cells = <2>;
4179 #size-cells = <2>;
4181 dma-ranges;
4189 clock-names = "cfg_noc",
4196 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4198 assigned-clock-rates = <19200000>, <200000000>;
4200 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
4204 interrupt-names = "hs_phy_irq",
4209 power-domains = <&gcc USB30_SEC_GDSC>;
4210 wakeup-source;
4216 interconnect-names = "usb-ddr", "apps-usb";
4226 phy-names = "usb2-phy", "usb3-phy";
4230 venus: video-codec@aa00000 {
4231 compatible = "qcom,sm8250-venus";
4234 power-domains = <&videocc MVS0C_GDSC>,
4237 power-domain-names = "venus", "vcodec0", "mx";
4238 operating-points-v2 = <&venus_opp_table>;
4243 clock-names = "iface", "core", "vcodec0_core";
4247 interconnect-names = "cpu-cfg", "video-mem";
4250 memory-region = <&video_mem>;
4254 reset-names = "bus", "core";
4258 video-decoder {
4259 compatible = "venus-decoder";
4262 video-encoder {
4263 compatible = "venus-encoder";
4266 venus_opp_table: opp-table {
4267 compatible = "operating-points-v2";
4269 opp-720000000 {
4270 opp-hz = /bits/ 64 <720000000>;
4271 required-opps = <&rpmhpd_opp_low_svs>;
4274 opp-1014000000 {
4275 opp-hz = /bits/ 64 <1014000000>;
4276 required-opps = <&rpmhpd_opp_svs>;
4279 opp-1098000000 {
4280 opp-hz = /bits/ 64 <1098000000>;
4281 required-opps = <&rpmhpd_opp_svs_l1>;
4284 opp-1332000000 {
4285 opp-hz = /bits/ 64 <1332000000>;
4286 required-opps = <&rpmhpd_opp_nom>;
4291 videocc: clock-controller@abf0000 {
4292 compatible = "qcom,sm8250-videocc";
4297 power-domains = <&rpmhpd RPMHPD_MMCX>;
4298 required-opps = <&rpmhpd_opp_low_svs>;
4299 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao";
4300 #clock-cells = <1>;
4301 #reset-cells = <1>;
4302 #power-domain-cells = <1>;
4306 compatible = "qcom,sm8250-cci", "qcom,msm8996-cci";
4307 #address-cells = <1>;
4308 #size-cells = <0>;
4312 power-domains = <&camcc TITAN_TOP_GDSC>;
4319 clock-names = "camnoc_axi",
4325 pinctrl-0 = <&cci0_default>;
4326 pinctrl-1 = <&cci0_sleep>;
4327 pinctrl-names = "default", "sleep";
4331 cci0_i2c0: i2c-bus@0 {
4333 clock-frequency = <1000000>;
4334 #address-cells = <1>;
4335 #size-cells = <0>;
4338 cci0_i2c1: i2c-bus@1 {
4340 clock-frequency = <1000000>;
4341 #address-cells = <1>;
4342 #size-cells = <0>;
4347 compatible = "qcom,sm8250-cci", "qcom,msm8996-cci";
4348 #address-cells = <1>;
4349 #size-cells = <0>;
4353 power-domains = <&camcc TITAN_TOP_GDSC>;
4360 clock-names = "camnoc_axi",
4366 pinctrl-0 = <&cci1_default>;
4367 pinctrl-1 = <&cci1_sleep>;
4368 pinctrl-names = "default", "sleep";
4372 cci1_i2c0: i2c-bus@0 {
4374 clock-frequency = <1000000>;
4375 #address-cells = <1>;
4376 #size-cells = <0>;
4379 cci1_i2c1: i2c-bus@1 {
4381 clock-frequency = <1000000>;
4382 #address-cells = <1>;
4383 #size-cells = <0>;
4388 compatible = "qcom,sm8250-camss";
4401 reg-names = "csiphy0",
4426 interrupt-names = "csiphy0",
4441 power-domains = <&camcc IFE_0_GDSC>,
4483 clock-names = "cam_ahb_clk",
4534 interconnect-names = "cam_ahb",
4540 #address-cells = <1>;
4541 #size-cells = <0>;
4569 camcc: clock-controller@ad00000 {
4570 compatible = "qcom,sm8250-camcc";
4576 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
4577 power-domains = <&rpmhpd RPMHPD_MMCX>;
4578 required-opps = <&rpmhpd_opp_low_svs>;
4580 #clock-cells = <1>;
4581 #reset-cells = <1>;
4582 #power-domain-cells = <1>;
4585 mdss: display-subsystem@ae00000 {
4586 compatible = "qcom,sm8250-mdss";
4588 reg-names = "mdss";
4592 interconnect-names = "mdp0-mem", "mdp1-mem";
4594 power-domains = <&dispcc MDSS_GDSC>;
4600 clock-names = "iface", "bus", "nrt_bus", "core";
4603 interrupt-controller;
4604 #interrupt-cells = <1>;
4610 #address-cells = <2>;
4611 #size-cells = <2>;
4614 mdss_mdp: display-controller@ae01000 {
4615 compatible = "qcom,sm8250-dpu";
4618 reg-names = "mdp", "vbif";
4624 clock-names = "iface", "bus", "core", "vsync";
4626 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4627 assigned-clock-rates = <19200000>;
4629 operating-points-v2 = <&mdp_opp_table>;
4630 power-domains = <&rpmhpd RPMHPD_MMCX>;
4632 interrupt-parent = <&mdss>;
4636 #address-cells = <1>;
4637 #size-cells = <0>;
4642 remote-endpoint = <&mdss_dsi0_in>;
4649 remote-endpoint = <&mdss_dsi1_in>;
4657 remote-endpoint = <&mdss_dp_in>;
4662 mdp_opp_table: opp-table {
4663 compatible = "operating-points-v2";
4665 opp-200000000 {
4666 opp-hz = /bits/ 64 <200000000>;
4667 required-opps = <&rpmhpd_opp_low_svs>;
4670 opp-300000000 {
4671 opp-hz = /bits/ 64 <300000000>;
4672 required-opps = <&rpmhpd_opp_svs>;
4675 opp-345000000 {
4676 opp-hz = /bits/ 64 <345000000>;
4677 required-opps = <&rpmhpd_opp_svs_l1>;
4680 opp-460000000 {
4681 opp-hz = /bits/ 64 <460000000>;
4682 required-opps = <&rpmhpd_opp_nom>;
4687 mdss_dp: displayport-controller@ae90000 {
4688 compatible = "qcom,sm8250-dp", "qcom,sm8350-dp";
4694 interrupt-parent = <&mdss>;
4701 clock-names = "core_iface",
4707 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
4709 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4713 phy-names = "dp";
4715 #sound-dai-cells = <0>;
4717 operating-points-v2 = <&dp_opp_table>;
4718 power-domains = <&rpmhpd SM8250_MMCX>;
4723 #address-cells = <1>;
4724 #size-cells = <0>;
4729 remote-endpoint = <&dpu_intf0_out>;
4741 dp_opp_table: opp-table {
4742 compatible = "operating-points-v2";
4744 opp-160000000 {
4745 opp-hz = /bits/ 64 <160000000>;
4746 required-opps = <&rpmhpd_opp_low_svs>;
4749 opp-270000000 {
4750 opp-hz = /bits/ 64 <270000000>;
4751 required-opps = <&rpmhpd_opp_svs>;
4754 opp-540000000 {
4755 opp-hz = /bits/ 64 <540000000>;
4756 required-opps = <&rpmhpd_opp_svs_l1>;
4759 opp-810000000 {
4760 opp-hz = /bits/ 64 <810000000>;
4761 required-opps = <&rpmhpd_opp_nom>;
4767 compatible = "qcom,sm8250-dsi-ctrl",
4768 "qcom,mdss-dsi-ctrl";
4770 reg-names = "dsi_ctrl";
4772 interrupt-parent = <&mdss>;
4781 clock-names = "byte",
4788 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
4789 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
4791 operating-points-v2 = <&dsi_opp_table>;
4792 power-domains = <&rpmhpd RPMHPD_MMCX>;
4798 #address-cells = <1>;
4799 #size-cells = <0>;
4802 #address-cells = <1>;
4803 #size-cells = <0>;
4808 remote-endpoint = <&dpu_intf1_out>;
4819 dsi_opp_table: opp-table {
4820 compatible = "operating-points-v2";
4822 opp-187500000 {
4823 opp-hz = /bits/ 64 <187500000>;
4824 required-opps = <&rpmhpd_opp_low_svs>;
4827 opp-300000000 {
4828 opp-hz = /bits/ 64 <300000000>;
4829 required-opps = <&rpmhpd_opp_svs>;
4832 opp-358000000 {
4833 opp-hz = /bits/ 64 <358000000>;
4834 required-opps = <&rpmhpd_opp_svs_l1>;
4840 compatible = "qcom,dsi-phy-7nm";
4844 reg-names = "dsi_phy",
4848 #clock-cells = <1>;
4849 #phy-cells = <0>;
4853 clock-names = "iface", "ref";
4859 compatible = "qcom,sm8250-dsi-ctrl",
4860 "qcom,mdss-dsi-ctrl";
4862 reg-names = "dsi_ctrl";
4864 interrupt-parent = <&mdss>;
4873 clock-names = "byte",
4880 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
4881 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
4883 operating-points-v2 = <&dsi_opp_table>;
4884 power-domains = <&rpmhpd RPMHPD_MMCX>;
4890 #address-cells = <1>;
4891 #size-cells = <0>;
4894 #address-cells = <1>;
4895 #size-cells = <0>;
4900 remote-endpoint = <&dpu_intf2_out>;
4913 compatible = "qcom,dsi-phy-7nm";
4917 reg-names = "dsi_phy",
4921 #clock-cells = <1>;
4922 #phy-cells = <0>;
4926 clock-names = "iface", "ref";
4932 dispcc: clock-controller@af00000 {
4933 compatible = "qcom,sm8250-dispcc";
4935 power-domains = <&rpmhpd RPMHPD_MMCX>;
4936 required-opps = <&rpmhpd_opp_low_svs>;
4944 clock-names = "bi_tcxo",
4951 #clock-cells = <1>;
4952 #reset-cells = <1>;
4953 #power-domain-cells = <1>;
4956 pdc: interrupt-controller@b220000 {
4957 compatible = "qcom,sm8250-pdc", "qcom,pdc";
4959 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
4961 #interrupt-cells = <2>;
4962 interrupt-parent = <&intc>;
4963 interrupt-controller;
4966 tsens0: thermal-sensor@c263000 {
4967 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
4973 interrupt-names = "uplow", "critical";
4974 #thermal-sensor-cells = <1>;
4977 tsens1: thermal-sensor@c265000 {
4978 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
4984 interrupt-names = "uplow", "critical";
4985 #thermal-sensor-cells = <1>;
4988 aoss_qmp: power-management@c300000 {
4989 compatible = "qcom,sm8250-aoss-qmp", "qcom,aoss-qmp";
4991 interrupts-extended = <&ipcc IPCC_CLIENT_AOP
4997 #clock-cells = <0>;
5001 compatible = "qcom,rpmh-stats";
5006 compatible = "qcom,spmi-pmic-arb";
5012 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
5013 interrupt-names = "periph_irq";
5014 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
5017 #address-cells = <2>;
5018 #size-cells = <0>;
5019 interrupt-controller;
5020 #interrupt-cells = <4>;
5024 compatible = "qcom,sm8250-pinctrl";
5028 reg-names = "west", "south", "north";
5030 gpio-controller;
5031 #gpio-cells = <2>;
5032 interrupt-controller;
5033 #interrupt-cells = <2>;
5034 gpio-ranges = <&tlmm 0 0 181>;
5035 wakeup-parent = <&pdc>;
5037 cam2_default: cam2-default-state {
5038 rst-pins {
5041 drive-strength = <2>;
5042 bias-disable;
5045 mclk-pins {
5048 drive-strength = <16>;
5049 bias-disable;
5053 cam2_suspend: cam2-suspend-state {
5054 rst-pins {
5057 drive-strength = <2>;
5058 bias-pull-down;
5059 output-low;
5062 mclk-pins {
5065 drive-strength = <2>;
5066 bias-disable;
5070 cci0_default: cci0-default-state {
5071 cci0_i2c0_default: cci0-i2c0-default-pins {
5076 bias-pull-up;
5077 drive-strength = <2>; /* 2 mA */
5080 cci0_i2c1_default: cci0-i2c1-default-pins {
5085 bias-pull-up;
5086 drive-strength = <2>; /* 2 mA */
5090 cci0_sleep: cci0-sleep-state {
5091 cci0_i2c0_sleep: cci0-i2c0-sleep-pins {
5096 drive-strength = <2>; /* 2 mA */
5097 bias-pull-down;
5100 cci0_i2c1_sleep: cci0-i2c1-sleep-pins {
5105 drive-strength = <2>; /* 2 mA */
5106 bias-pull-down;
5110 cci1_default: cci1-default-state {
5111 cci1_i2c0_default: cci1-i2c0-default-pins {
5116 bias-pull-up;
5117 drive-strength = <2>; /* 2 mA */
5120 cci1_i2c1_default: cci1-i2c1-default-pins {
5125 bias-pull-up;
5126 drive-strength = <2>; /* 2 mA */
5130 cci1_sleep: cci1-sleep-state {
5131 cci1_i2c0_sleep: cci1-i2c0-sleep-pins {
5136 bias-pull-down;
5137 drive-strength = <2>; /* 2 mA */
5140 cci1_i2c1_sleep: cci1-i2c1-sleep-pins {
5145 bias-pull-down;
5146 drive-strength = <2>; /* 2 mA */
5150 pri_mi2s_active: pri-mi2s-active-state {
5151 sclk-pins {
5154 drive-strength = <8>;
5155 bias-disable;
5158 ws-pins {
5161 drive-strength = <8>;
5162 output-high;
5165 data0-pins {
5168 drive-strength = <8>;
5169 bias-disable;
5170 output-high;
5173 data1-pins {
5176 drive-strength = <8>;
5177 output-high;
5181 qup_i2c0_default: qup-i2c0-default-state {
5184 drive-strength = <2>;
5185 bias-disable;
5188 qup_i2c1_default: qup-i2c1-default-state {
5191 drive-strength = <2>;
5192 bias-disable;
5195 qup_i2c2_default: qup-i2c2-default-state {
5198 drive-strength = <2>;
5199 bias-disable;
5202 qup_i2c3_default: qup-i2c3-default-state {
5205 drive-strength = <2>;
5206 bias-disable;
5209 qup_i2c4_default: qup-i2c4-default-state {
5212 drive-strength = <2>;
5213 bias-disable;
5216 qup_i2c5_default: qup-i2c5-default-state {
5219 drive-strength = <2>;
5220 bias-disable;
5223 qup_i2c6_default: qup-i2c6-default-state {
5226 drive-strength = <2>;
5227 bias-disable;
5230 qup_i2c7_default: qup-i2c7-default-state {
5233 drive-strength = <2>;
5234 bias-disable;
5237 qup_i2c8_default: qup-i2c8-default-state {
5240 drive-strength = <2>;
5241 bias-disable;
5244 qup_i2c9_default: qup-i2c9-default-state {
5247 drive-strength = <2>;
5248 bias-disable;
5251 qup_i2c10_default: qup-i2c10-default-state {
5254 drive-strength = <2>;
5255 bias-disable;
5258 qup_i2c11_default: qup-i2c11-default-state {
5261 drive-strength = <2>;
5262 bias-disable;
5265 qup_i2c12_default: qup-i2c12-default-state {
5268 drive-strength = <2>;
5269 bias-disable;
5272 qup_i2c13_default: qup-i2c13-default-state {
5275 drive-strength = <2>;
5276 bias-disable;
5279 qup_i2c14_default: qup-i2c14-default-state {
5282 drive-strength = <2>;
5283 bias-disable;
5286 qup_i2c15_default: qup-i2c15-default-state {
5289 drive-strength = <2>;
5290 bias-disable;
5293 qup_i2c16_default: qup-i2c16-default-state {
5296 drive-strength = <2>;
5297 bias-disable;
5300 qup_i2c17_default: qup-i2c17-default-state {
5303 drive-strength = <2>;
5304 bias-disable;
5307 qup_i2c18_default: qup-i2c18-default-state {
5310 drive-strength = <2>;
5311 bias-disable;
5314 qup_i2c19_default: qup-i2c19-default-state {
5317 drive-strength = <2>;
5318 bias-disable;
5321 qup_spi0_cs: qup-spi0-cs-state {
5326 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state {
5331 qup_spi0_data_clk: qup-spi0-data-clk-state {
5337 qup_spi1_cs: qup-spi1-cs-state {
5342 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state {
5347 qup_spi1_data_clk: qup-spi1-data-clk-state {
5353 qup_spi2_cs: qup-spi2-cs-state {
5358 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state {
5363 qup_spi2_data_clk: qup-spi2-data-clk-state {
5369 qup_spi3_cs: qup-spi3-cs-state {
5374 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state {
5379 qup_spi3_data_clk: qup-spi3-data-clk-state {
5385 qup_spi4_cs: qup-spi4-cs-state {
5390 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state {
5395 qup_spi4_data_clk: qup-spi4-data-clk-state {
5401 qup_spi5_cs: qup-spi5-cs-state {
5406 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state {
5411 qup_spi5_data_clk: qup-spi5-data-clk-state {
5417 qup_spi6_cs: qup-spi6-cs-state {
5422 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state {
5427 qup_spi6_data_clk: qup-spi6-data-clk-state {
5433 qup_spi7_cs: qup-spi7-cs-state {
5438 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state {
5443 qup_spi7_data_clk: qup-spi7-data-clk-state {
5449 qup_spi8_cs: qup-spi8-cs-state {
5454 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state {
5459 qup_spi8_data_clk: qup-spi8-data-clk-state {
5465 qup_spi9_cs: qup-spi9-cs-state {
5470 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state {
5475 qup_spi9_data_clk: qup-spi9-data-clk-state {
5481 qup_spi10_cs: qup-spi10-cs-state {
5486 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state {
5491 qup_spi10_data_clk: qup-spi10-data-clk-state {
5497 qup_spi11_cs: qup-spi11-cs-state {
5502 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state {
5507 qup_spi11_data_clk: qup-spi11-data-clk-state {
5513 qup_spi12_cs: qup-spi12-cs-state {
5518 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state {
5523 qup_spi12_data_clk: qup-spi12-data-clk-state {
5529 qup_spi13_cs: qup-spi13-cs-state {
5534 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state {
5539 qup_spi13_data_clk: qup-spi13-data-clk-state {
5545 qup_spi14_cs: qup-spi14-cs-state {
5550 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state {
5555 qup_spi14_data_clk: qup-spi14-data-clk-state {
5561 qup_spi15_cs: qup-spi15-cs-state {
5566 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state {
5571 qup_spi15_data_clk: qup-spi15-data-clk-state {
5577 qup_spi16_cs: qup-spi16-cs-state {
5582 qup_spi16_cs_gpio: qup-spi16-cs-gpio-state {
5587 qup_spi16_data_clk: qup-spi16-data-clk-state {
5593 qup_spi17_cs: qup-spi17-cs-state {
5598 qup_spi17_cs_gpio: qup-spi17-cs-gpio-state {
5603 qup_spi17_data_clk: qup-spi17-data-clk-state {
5609 qup_spi18_cs: qup-spi18-cs-state {
5614 qup_spi18_cs_gpio: qup-spi18-cs-gpio-state {
5619 qup_spi18_data_clk: qup-spi18-data-clk-state {
5625 qup_spi19_cs: qup-spi19-cs-state {
5630 qup_spi19_cs_gpio: qup-spi19-cs-gpio-state {
5635 qup_spi19_data_clk: qup-spi19-data-clk-state {
5641 qup_uart2_default: qup-uart2-default-state {
5646 qup_uart6_default: qup-uart6-default-state {
5651 qup_uart12_default: qup-uart12-default-state {
5656 qup_uart17_default: qup-uart17-default-state {
5661 qup_uart18_default: qup-uart18-default-state {
5666 tert_mi2s_active: tert-mi2s-active-state {
5667 sck-pins {
5670 drive-strength = <8>;
5671 bias-disable;
5674 data0-pins {
5677 drive-strength = <8>;
5678 bias-disable;
5679 output-high;
5682 ws-pins {
5685 drive-strength = <8>;
5686 output-high;
5690 sdc2_sleep_state: sdc2-sleep-state {
5691 clk-pins {
5693 drive-strength = <2>;
5694 bias-disable;
5697 cmd-pins {
5699 drive-strength = <2>;
5700 bias-pull-up;
5703 data-pins {
5705 drive-strength = <2>;
5706 bias-pull-up;
5710 pcie0_default_state: pcie0-default-state {
5711 perst-pins {
5714 drive-strength = <2>;
5715 bias-pull-down;
5718 clkreq-pins {
5721 drive-strength = <2>;
5722 bias-pull-up;
5725 wake-pins {
5728 drive-strength = <2>;
5729 bias-pull-up;
5733 pcie1_default_state: pcie1-default-state {
5734 perst-pins {
5737 drive-strength = <2>;
5738 bias-pull-down;
5741 clkreq-pins {
5744 drive-strength = <2>;
5745 bias-pull-up;
5748 wake-pins {
5751 drive-strength = <2>;
5752 bias-pull-up;
5756 pcie2_default_state: pcie2-default-state {
5757 perst-pins {
5760 drive-strength = <2>;
5761 bias-pull-down;
5764 clkreq-pins {
5767 drive-strength = <2>;
5768 bias-pull-up;
5771 wake-pins {
5774 drive-strength = <2>;
5775 bias-pull-up;
5781 compatible = "qcom,sm8250-smmu-500", "qcom,smmu-500", "arm,mmu-500";
5783 #iommu-cells = <2>;
5784 #global-interrupts = <2>;
5883 dma-coherent;
5887 compatible = "qcom,sm8250-adsp-pas";
5890 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
5895 interrupt-names = "wdog", "fatal", "ready",
5896 "handover", "stop-ack";
5899 clock-names = "xo";
5901 power-domains = <&rpmhpd RPMHPD_LCX>,
5903 power-domain-names = "lcx", "lmx";
5905 memory-region = <&adsp_mem>;
5909 qcom,smem-states = <&smp2p_adsp_out 0>;
5910 qcom,smem-state-names = "stop";
5914 glink-edge {
5915 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
5922 qcom,remote-pid = <2>;
5925 compatible = "qcom,apr-v2";
5926 qcom,glink-channels = "apr_audio_svc";
5928 #address-cells = <1>;
5929 #size-cells = <0>;
5934 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
5940 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
5942 compatible = "qcom,q6afe-dais";
5943 #address-cells = <1>;
5944 #size-cells = <0>;
5945 #sound-dai-cells = <1>;
5948 q6afecc: clock-controller {
5949 compatible = "qcom,q6afe-clocks";
5950 #clock-cells = <2>;
5957 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
5959 compatible = "qcom,q6asm-dais";
5960 #address-cells = <1>;
5961 #size-cells = <0>;
5962 #sound-dai-cells = <1>;
5970 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
5972 compatible = "qcom,q6adm-routing";
5973 #sound-dai-cells = <0>;
5980 qcom,glink-channels = "fastrpcglink-apps-dsp";
5982 qcom,non-secure-domain;
5983 #address-cells = <1>;
5984 #size-cells = <0>;
5986 compute-cb@3 {
5987 compatible = "qcom,fastrpc-compute-cb";
5992 compute-cb@4 {
5993 compatible = "qcom,fastrpc-compute-cb";
5998 compute-cb@5 {
5999 compatible = "qcom,fastrpc-compute-cb";
6007 intc: interrupt-controller@17a00000 {
6008 compatible = "arm,gic-v3";
6009 #interrupt-cells = <3>;
6010 interrupt-controller;
6017 compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt";
6024 #address-cells = <1>;
6025 #size-cells = <1>;
6027 compatible = "arm,armv7-timer-mem";
6029 clock-frequency = <19200000>;
6032 frame-number = <0>;
6040 frame-number = <1>;
6047 frame-number = <2>;
6054 frame-number = <3>;
6061 frame-number = <4>;
6068 frame-number = <5>;
6075 frame-number = <6>;
6084 compatible = "qcom,rpmh-rsc";
6088 reg-names = "drv-0", "drv-1", "drv-2";
6092 qcom,tcs-offset = <0xd00>;
6093 qcom,drv-id = <2>;
6094 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
6096 power-domains = <&CLUSTER_PD>;
6098 rpmhcc: clock-controller {
6099 compatible = "qcom,sm8250-rpmh-clk";
6100 #clock-cells = <1>;
6101 clock-names = "xo";
6105 rpmhpd: power-controller {
6106 compatible = "qcom,sm8250-rpmhpd";
6107 #power-domain-cells = <1>;
6108 operating-points-v2 = <&rpmhpd_opp_table>;
6110 rpmhpd_opp_table: opp-table {
6111 compatible = "operating-points-v2";
6114 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
6118 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
6122 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
6126 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
6130 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
6134 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
6138 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
6142 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
6146 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
6150 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
6155 apps_bcm_voter: bcm-voter {
6156 compatible = "qcom,bcm-voter";
6161 compatible = "qcom,sm8250-epss-l3", "qcom,epss-l3";
6165 clock-names = "xo", "alternate";
6167 #interconnect-cells = <1>;
6171 compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss";
6175 reg-names = "freq-domain0", "freq-domain1",
6176 "freq-domain2";
6179 clock-names = "xo", "alternate";
6183 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
6184 #freq-domain-cells = <1>;
6185 #clock-cells = <1>;
6193 compatible = "arm,armv8-timer";
6204 thermal-zones {
6205 cpu0-thermal {
6206 polling-delay-passive = <250>;
6207 polling-delay = <1000>;
6209 thermal-sensors = <&tsens0 1>;
6212 cpu0_alert0: trip-point0 {
6218 cpu0_alert1: trip-point1 {
6224 cpu0_crit: cpu-crit {
6231 cooling-maps {
6234 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6241 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6249 cpu1-thermal {
6250 polling-delay-passive = <250>;
6251 polling-delay = <1000>;
6253 thermal-sensors = <&tsens0 2>;
6256 cpu1_alert0: trip-point0 {
6262 cpu1_alert1: trip-point1 {
6268 cpu1_crit: cpu-crit {
6275 cooling-maps {
6278 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6285 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6293 cpu2-thermal {
6294 polling-delay-passive = <250>;
6295 polling-delay = <1000>;
6297 thermal-sensors = <&tsens0 3>;
6300 cpu2_alert0: trip-point0 {
6306 cpu2_alert1: trip-point1 {
6312 cpu2_crit: cpu-crit {
6319 cooling-maps {
6322 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6329 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6337 cpu3-thermal {
6338 polling-delay-passive = <250>;
6339 polling-delay = <1000>;
6341 thermal-sensors = <&tsens0 4>;
6344 cpu3_alert0: trip-point0 {
6350 cpu3_alert1: trip-point1 {
6356 cpu3_crit: cpu-crit {
6363 cooling-maps {
6366 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6373 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6381 cpu4-top-thermal {
6382 polling-delay-passive = <250>;
6383 polling-delay = <1000>;
6385 thermal-sensors = <&tsens0 7>;
6388 cpu4_top_alert0: trip-point0 {
6394 cpu4_top_alert1: trip-point1 {
6400 cpu4_top_crit: cpu-crit {
6407 cooling-maps {
6410 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6417 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6425 cpu5-top-thermal {
6426 polling-delay-passive = <250>;
6427 polling-delay = <1000>;
6429 thermal-sensors = <&tsens0 8>;
6432 cpu5_top_alert0: trip-point0 {
6438 cpu5_top_alert1: trip-point1 {
6444 cpu5_top_crit: cpu-crit {
6451 cooling-maps {
6454 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6461 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6469 cpu6-top-thermal {
6470 polling-delay-passive = <250>;
6471 polling-delay = <1000>;
6473 thermal-sensors = <&tsens0 9>;
6476 cpu6_top_alert0: trip-point0 {
6482 cpu6_top_alert1: trip-point1 {
6488 cpu6_top_crit: cpu-crit {
6495 cooling-maps {
6498 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6505 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6513 cpu7-top-thermal {
6514 polling-delay-passive = <250>;
6515 polling-delay = <1000>;
6517 thermal-sensors = <&tsens0 10>;
6520 cpu7_top_alert0: trip-point0 {
6526 cpu7_top_alert1: trip-point1 {
6532 cpu7_top_crit: cpu-crit {
6539 cooling-maps {
6542 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6549 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6557 cpu4-bottom-thermal {
6558 polling-delay-passive = <250>;
6559 polling-delay = <1000>;
6561 thermal-sensors = <&tsens0 11>;
6564 cpu4_bottom_alert0: trip-point0 {
6570 cpu4_bottom_alert1: trip-point1 {
6576 cpu4_bottom_crit: cpu-crit {
6583 cooling-maps {
6586 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6593 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6601 cpu5-bottom-thermal {
6602 polling-delay-passive = <250>;
6603 polling-delay = <1000>;
6605 thermal-sensors = <&tsens0 12>;
6608 cpu5_bottom_alert0: trip-point0 {
6614 cpu5_bottom_alert1: trip-point1 {
6620 cpu5_bottom_crit: cpu-crit {
6627 cooling-maps {
6630 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6637 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6645 cpu6-bottom-thermal {
6646 polling-delay-passive = <250>;
6647 polling-delay = <1000>;
6649 thermal-sensors = <&tsens0 13>;
6652 cpu6_bottom_alert0: trip-point0 {
6658 cpu6_bottom_alert1: trip-point1 {
6664 cpu6_bottom_crit: cpu-crit {
6671 cooling-maps {
6674 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6681 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6689 cpu7-bottom-thermal {
6690 polling-delay-passive = <250>;
6691 polling-delay = <1000>;
6693 thermal-sensors = <&tsens0 14>;
6696 cpu7_bottom_alert0: trip-point0 {
6702 cpu7_bottom_alert1: trip-point1 {
6708 cpu7_bottom_crit: cpu-crit {
6715 cooling-maps {
6718 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6725 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6733 aoss0-thermal {
6734 polling-delay-passive = <250>;
6735 polling-delay = <1000>;
6737 thermal-sensors = <&tsens0 0>;
6740 aoss0_alert0: trip-point0 {
6748 cluster0-thermal {
6749 polling-delay-passive = <250>;
6750 polling-delay = <1000>;
6752 thermal-sensors = <&tsens0 5>;
6755 cluster0_alert0: trip-point0 {
6768 cluster1-thermal {
6769 polling-delay-passive = <250>;
6770 polling-delay = <1000>;
6772 thermal-sensors = <&tsens0 6>;
6775 cluster1_alert0: trip-point0 {
6788 gpu-top-thermal {
6789 polling-delay-passive = <250>;
6790 polling-delay = <1000>;
6792 thermal-sensors = <&tsens0 15>;
6795 gpu1_alert0: trip-point0 {
6803 aoss1-thermal {
6804 polling-delay-passive = <250>;
6805 polling-delay = <1000>;
6807 thermal-sensors = <&tsens1 0>;
6810 aoss1_alert0: trip-point0 {
6818 wlan-thermal {
6819 polling-delay-passive = <250>;
6820 polling-delay = <1000>;
6822 thermal-sensors = <&tsens1 1>;
6825 wlan_alert0: trip-point0 {
6833 video-thermal {
6834 polling-delay-passive = <250>;
6835 polling-delay = <1000>;
6837 thermal-sensors = <&tsens1 2>;
6840 video_alert0: trip-point0 {
6848 mem-thermal {
6849 polling-delay-passive = <250>;
6850 polling-delay = <1000>;
6852 thermal-sensors = <&tsens1 3>;
6855 mem_alert0: trip-point0 {
6863 q6-hvx-thermal {
6864 polling-delay-passive = <250>;
6865 polling-delay = <1000>;
6867 thermal-sensors = <&tsens1 4>;
6870 q6_hvx_alert0: trip-point0 {
6878 camera-thermal {
6879 polling-delay-passive = <250>;
6880 polling-delay = <1000>;
6882 thermal-sensors = <&tsens1 5>;
6885 camera_alert0: trip-point0 {
6893 compute-thermal {
6894 polling-delay-passive = <250>;
6895 polling-delay = <1000>;
6897 thermal-sensors = <&tsens1 6>;
6900 compute_alert0: trip-point0 {
6908 npu-thermal {
6909 polling-delay-passive = <250>;
6910 polling-delay = <1000>;
6912 thermal-sensors = <&tsens1 7>;
6915 npu_alert0: trip-point0 {
6923 gpu-bottom-thermal {
6924 polling-delay-passive = <250>;
6925 polling-delay = <1000>;
6927 thermal-sensors = <&tsens1 8>;
6930 gpu2_alert0: trip-point0 {