Lines Matching +full:0 +full:x0f900000
82 #clock-cells = <0>;
90 #clock-cells = <0>;
96 #size-cells = <0>;
98 CPU0: cpu@0 {
101 reg = <0x0 0x0>;
102 clocks = <&cpufreq_hw 0>;
109 qcom,freq-domain = <&cpufreq_hw 0>;
111 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
117 cache-size = <0x20000>;
123 cache-size = <0x400000>;
132 reg = <0x0 0x100>;
133 clocks = <&cpufreq_hw 0>;
140 qcom,freq-domain = <&cpufreq_hw 0>;
142 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
148 cache-size = <0x20000>;
157 reg = <0x0 0x200>;
158 clocks = <&cpufreq_hw 0>;
165 qcom,freq-domain = <&cpufreq_hw 0>;
167 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
173 cache-size = <0x20000>;
182 reg = <0x0 0x300>;
183 clocks = <&cpufreq_hw 0>;
190 qcom,freq-domain = <&cpufreq_hw 0>;
192 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
198 cache-size = <0x20000>;
207 reg = <0x0 0x400>;
217 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
223 cache-size = <0x40000>;
232 reg = <0x0 0x500>;
242 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
248 cache-size = <0x40000>;
257 reg = <0x0 0x600>;
267 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
273 cache-size = <0x40000>;
282 reg = <0x0 0x700>;
292 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
298 cache-size = <0x80000>;
343 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
346 arm,psci-suspend-param = <0x40000004>;
353 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
356 arm,psci-suspend-param = <0x40000004>;
365 CLUSTER_SLEEP_0: cluster-sleep-0 {
367 arm,psci-suspend-param = <0x4100c244>;
674 qcom,dload-mode = <&tcsr 0x13000>;
682 reg = <0x0 0x80000000 0x0 0x0>;
695 #power-domain-cells = <0>;
701 #power-domain-cells = <0>;
707 #power-domain-cells = <0>;
713 #power-domain-cells = <0>;
719 #power-domain-cells = <0>;
725 #power-domain-cells = <0>;
731 #power-domain-cells = <0>;
737 #power-domain-cells = <0>;
743 #power-domain-cells = <0>;
773 reg = <0x0 0x80000000 0x0 0x600000>;
778 reg = <0x0 0x80700000 0x0 0x160000>;
784 reg = <0x0 0x80860000 0x0 0x20000>;
789 reg = <0x0 0x80900000 0x0 0x200000>;
794 reg = <0x0 0x80b00000 0x0 0x5300000>;
799 reg = <0x0 0x86200000 0x0 0x500000>;
804 reg = <0x0 0x86700000 0x0 0x100000>;
809 reg = <0x0 0x86800000 0x0 0x10000>;
814 reg = <0x0 0x86810000 0x0 0xa000>;
819 reg = <0x0 0x8681a000 0x0 0x2000>;
824 reg = <0x0 0x86900000 0x0 0x500000>;
829 reg = <0x0 0x86e00000 0x0 0x500000>;
834 reg = <0x0 0x87300000 0x0 0x500000>;
839 reg = <0x0 0x87800000 0x0 0x1400000>;
844 reg = <0x0 0x88c00000 0x0 0x1500000>;
849 reg = <0x0 0x8a100000 0x0 0x1d00000>;
854 reg = <0x0 0x8be00000 0x0 0x100000>;
859 reg = <0x0 0x8bf00000 0x0 0x4600000>;
879 qcom,local-pid = <0>;
903 qcom,local-pid = <0>;
927 qcom,local-pid = <0>;
942 soc: soc@0 {
945 ranges = <0 0 0 0 0x10 0>;
946 dma-ranges = <0 0 0 0 0x10 0>;
951 reg = <0x0 0x00100000 0x0 0x1f0000>;
965 reg = <0 0x00408000 0 0x1000>;
974 reg = <0 0x00784000 0 0x8ff>;
979 reg = <0x19b 0x1>;
986 reg = <0 0x00793000 0 0x1000>;
993 reg = <0 0x00800000 0 0x70000>;
1005 dma-channel-mask = <0x3f>;
1006 iommus = <&apps_smmu 0x76 0x0>;
1013 reg = <0x0 0x008c0000 0x0 0x6000>;
1019 iommus = <&apps_smmu 0x63 0x0>;
1025 reg = <0 0x00880000 0 0x4000>;
1029 pinctrl-0 = <&qup_i2c14_default>;
1031 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
1032 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
1035 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1036 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1037 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1042 #size-cells = <0>;
1048 reg = <0 0x00880000 0 0x4000>;
1052 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
1053 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
1057 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1058 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1059 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1064 #size-cells = <0>;
1070 reg = <0 0x00884000 0 0x4000>;
1074 pinctrl-0 = <&qup_i2c15_default>;
1076 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
1080 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1081 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1082 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1087 #size-cells = <0>;
1093 reg = <0 0x00884000 0 0x4000>;
1097 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
1102 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1103 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1104 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1109 #size-cells = <0>;
1115 reg = <0 0x00888000 0 0x4000>;
1119 pinctrl-0 = <&qup_i2c16_default>;
1121 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
1125 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1126 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1127 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1132 #size-cells = <0>;
1138 reg = <0 0x00888000 0 0x4000>;
1142 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1147 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1148 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1149 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1154 #size-cells = <0>;
1160 reg = <0 0x0088c000 0 0x4000>;
1164 pinctrl-0 = <&qup_i2c17_default>;
1166 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1170 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1171 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1172 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1177 #size-cells = <0>;
1183 reg = <0 0x0088c000 0 0x4000>;
1187 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
1192 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1193 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1194 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1199 #size-cells = <0>;
1205 reg = <0 0x0088c000 0 0x4000>;
1209 pinctrl-0 = <&qup_uart17_default>;
1213 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1214 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1222 reg = <0 0x00890000 0 0x4000>;
1226 pinctrl-0 = <&qup_i2c18_default>;
1228 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1232 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1233 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1234 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1239 #size-cells = <0>;
1245 reg = <0 0x00890000 0 0x4000>;
1249 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
1254 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1255 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1256 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1261 #size-cells = <0>;
1267 reg = <0 0x00890000 0 0x4000>;
1271 pinctrl-0 = <&qup_uart18_default>;
1275 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1276 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1284 reg = <0 0x00894000 0 0x4000>;
1288 pinctrl-0 = <&qup_i2c19_default>;
1290 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1294 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1295 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1296 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1301 #size-cells = <0>;
1307 reg = <0 0x00894000 0 0x4000>;
1311 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1316 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1317 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1318 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1323 #size-cells = <0>;
1330 reg = <0 0x00900000 0 0x70000>;
1345 dma-channel-mask = <0x7ff>;
1346 iommus = <&apps_smmu 0x5b6 0x0>;
1353 reg = <0x0 0x009c0000 0x0 0x6000>;
1359 iommus = <&apps_smmu 0x5a3 0x0>;
1365 reg = <0 0x00980000 0 0x4000>;
1369 pinctrl-0 = <&qup_i2c0_default>;
1371 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1372 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1375 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1376 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1377 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1382 #size-cells = <0>;
1388 reg = <0 0x00980000 0 0x4000>;
1392 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1393 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1397 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1398 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1399 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1404 #size-cells = <0>;
1410 reg = <0 0x00984000 0 0x4000>;
1414 pinctrl-0 = <&qup_i2c1_default>;
1416 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1420 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1421 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1422 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1427 #size-cells = <0>;
1433 reg = <0 0x00984000 0 0x4000>;
1437 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1442 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1443 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1444 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1449 #size-cells = <0>;
1455 reg = <0 0x00988000 0 0x4000>;
1459 pinctrl-0 = <&qup_i2c2_default>;
1461 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1465 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1466 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1467 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1472 #size-cells = <0>;
1478 reg = <0 0x00988000 0 0x4000>;
1482 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1487 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1488 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1489 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1494 #size-cells = <0>;
1500 reg = <0 0x00988000 0 0x4000>;
1504 pinctrl-0 = <&qup_uart2_default>;
1508 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1509 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1517 reg = <0 0x0098c000 0 0x4000>;
1521 pinctrl-0 = <&qup_i2c3_default>;
1523 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1527 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1528 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1529 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1534 #size-cells = <0>;
1540 reg = <0 0x0098c000 0 0x4000>;
1544 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1549 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1550 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1551 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1556 #size-cells = <0>;
1562 reg = <0 0x00990000 0 0x4000>;
1566 pinctrl-0 = <&qup_i2c4_default>;
1568 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1572 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1573 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1574 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1579 #size-cells = <0>;
1585 reg = <0 0x00990000 0 0x4000>;
1589 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1594 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1595 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1596 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1601 #size-cells = <0>;
1607 reg = <0 0x00994000 0 0x4000>;
1611 pinctrl-0 = <&qup_i2c5_default>;
1613 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1617 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1618 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1619 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1624 #size-cells = <0>;
1630 reg = <0 0x00994000 0 0x4000>;
1634 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1639 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1640 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1641 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1646 #size-cells = <0>;
1652 reg = <0 0x00998000 0 0x4000>;
1656 pinctrl-0 = <&qup_i2c6_default>;
1658 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1662 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1663 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1664 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1669 #size-cells = <0>;
1675 reg = <0 0x00998000 0 0x4000>;
1679 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1684 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1685 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1686 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1691 #size-cells = <0>;
1697 reg = <0 0x00998000 0 0x4000>;
1701 pinctrl-0 = <&qup_uart6_default>;
1705 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1706 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1714 reg = <0 0x0099c000 0 0x4000>;
1718 pinctrl-0 = <&qup_i2c7_default>;
1720 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1724 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1725 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1726 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1731 #size-cells = <0>;
1737 reg = <0 0x0099c000 0 0x4000>;
1741 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1746 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1747 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1748 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1753 #size-cells = <0>;
1760 reg = <0 0x00a00000 0 0x70000>;
1772 dma-channel-mask = <0x3f>;
1773 iommus = <&apps_smmu 0x56 0x0>;
1780 reg = <0x0 0x00ac0000 0x0 0x6000>;
1786 iommus = <&apps_smmu 0x43 0x0>;
1792 reg = <0 0x00a80000 0 0x4000>;
1796 pinctrl-0 = <&qup_i2c8_default>;
1798 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1799 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1802 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1803 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1804 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1809 #size-cells = <0>;
1815 reg = <0 0x00a80000 0 0x4000>;
1819 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1820 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1824 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1825 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1826 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1831 #size-cells = <0>;
1837 reg = <0 0x00a84000 0 0x4000>;
1841 pinctrl-0 = <&qup_i2c9_default>;
1843 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1847 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1848 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1849 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1854 #size-cells = <0>;
1860 reg = <0 0x00a84000 0 0x4000>;
1864 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1869 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1870 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1871 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1876 #size-cells = <0>;
1882 reg = <0 0x00a88000 0 0x4000>;
1886 pinctrl-0 = <&qup_i2c10_default>;
1888 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1892 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1893 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1894 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1899 #size-cells = <0>;
1905 reg = <0 0x00a88000 0 0x4000>;
1909 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1914 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1915 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1916 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1921 #size-cells = <0>;
1927 reg = <0 0x00a8c000 0 0x4000>;
1931 pinctrl-0 = <&qup_i2c11_default>;
1933 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1937 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1938 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1939 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1944 #size-cells = <0>;
1950 reg = <0 0x00a8c000 0 0x4000>;
1954 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1959 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1960 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1961 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1966 #size-cells = <0>;
1972 reg = <0 0x00a90000 0 0x4000>;
1976 pinctrl-0 = <&qup_i2c12_default>;
1978 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1982 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1983 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1984 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1989 #size-cells = <0>;
1995 reg = <0 0x00a90000 0 0x4000>;
1999 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
2004 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
2005 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
2006 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
2011 #size-cells = <0>;
2017 reg = <0x0 0x00a90000 0x0 0x4000>;
2021 pinctrl-0 = <&qup_uart12_default>;
2025 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
2026 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
2034 reg = <0 0x00a94000 0 0x4000>;
2038 pinctrl-0 = <&qup_i2c13_default>;
2040 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
2044 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
2045 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
2046 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
2051 #size-cells = <0>;
2057 reg = <0 0x00a94000 0 0x4000>;
2061 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
2066 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
2067 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
2068 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
2073 #size-cells = <0>;
2080 reg = <0 0x01500000 0 0xa580>;
2087 reg = <0 0x01620000 0 0x1c200>;
2094 reg = <0 0x0163d000 0 0x1000>;
2101 reg = <0 0x016e0000 0 0x1f180>;
2108 reg = <0 0x01700000 0 0x33000>;
2115 reg = <0 0x01733000 0 0xa180>;
2122 reg = <0 0x01740000 0 0x1f080>;
2129 reg = <0 0x01c00000 0 0x3000>,
2130 <0 0x60000000 0 0xf1d>,
2131 <0 0x60000f20 0 0xa8>,
2132 <0 0x60001000 0 0x1000>,
2133 <0 0x60100000 0 0x100000>,
2134 <0 0x01c03000 0 0x1000>;
2137 linux,pci-domain = <0>;
2138 bus-range = <0x00 0xff>;
2144 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
2145 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
2158 interrupt-map-mask = <0 0 0 0x7>;
2159 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2160 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2161 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2162 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2181 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
2182 <0x100 &apps_smmu 0x1c01 0x1>;
2196 pinctrl-0 = <&pcie0_default_state>;
2204 reg = <0 0x01c06000 0 0x1000>;
2218 #clock-cells = <0>;
2220 #phy-cells = <0>;
2233 reg = <0 0x01c08000 0 0x3000>,
2234 <0 0x40000000 0 0xf1d>,
2235 <0 0x40000f20 0 0xa8>,
2236 <0 0x40001000 0 0x1000>,
2237 <0 0x40100000 0 0x100000>,
2238 <0 0x01c0b000 0 0x1000>;
2242 bus-range = <0x00 0xff>;
2248 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
2249 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2254 interrupt-map-mask = <0 0 0 0x7>;
2255 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2256 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2257 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2258 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2282 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2283 <0x100 &apps_smmu 0x1c81 0x1>;
2297 pinctrl-0 = <&pcie1_default_state>;
2305 reg = <0 0x01c0e000 0 0x1000>;
2319 #clock-cells = <0>;
2321 #phy-cells = <0>;
2334 reg = <0 0x01c10000 0 0x3000>,
2335 <0 0x64000000 0 0xf1d>,
2336 <0 0x64000f20 0 0xa8>,
2337 <0 0x64001000 0 0x1000>,
2338 <0 0x64100000 0 0x100000>,
2339 <0 0x01c13000 0 0x1000>;
2343 bus-range = <0x00 0xff>;
2349 ranges = <0x01000000 0x0 0x00000000 0x0 0x64200000 0x0 0x100000>,
2350 <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>;
2355 interrupt-map-mask = <0 0 0 0x7>;
2356 interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2357 <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2358 <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2359 <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2383 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,
2384 <0x100 &apps_smmu 0x1d01 0x1>;
2398 pinctrl-0 = <&pcie2_default_state>;
2406 reg = <0 0x01c16000 0 0x1000>;
2420 #clock-cells = <0>;
2422 #phy-cells = <0>;
2436 reg = <0 0x01d84000 0 0x3000>;
2447 iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>;
2470 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI_CH0 0>,
2471 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
2481 /bits/ 64 <0>,
2482 /bits/ 64 <0>,
2484 /bits/ 64 <0>,
2485 /bits/ 64 <0>,
2486 /bits/ 64 <0>,
2487 /bits/ 64 <0>;
2493 /bits/ 64 <0>,
2494 /bits/ 64 <0>,
2496 /bits/ 64 <0>,
2497 /bits/ 64 <0>,
2498 /bits/ 64 <0>,
2499 /bits/ 64 <0>;
2507 reg = <0 0x01d87000 0 0x1000>;
2514 resets = <&ufs_mem_hc 0>;
2517 #phy-cells = <0>;
2524 reg = <0 0x01dc4000 0 0x24000>;
2527 qcom,ee = <0>;
2531 iommus = <&apps_smmu 0x592 0x0000>,
2532 <&apps_smmu 0x598 0x0000>,
2533 <&apps_smmu 0x599 0x0000>,
2534 <&apps_smmu 0x59f 0x0000>,
2535 <&apps_smmu 0x586 0x0011>,
2536 <&apps_smmu 0x596 0x0011>;
2541 reg = <0 0x01dfa000 0 0x6000>;
2544 iommus = <&apps_smmu 0x592 0x0000>,
2545 <&apps_smmu 0x598 0x0000>,
2546 <&apps_smmu 0x599 0x0000>,
2547 <&apps_smmu 0x59f 0x0000>,
2548 <&apps_smmu 0x586 0x0011>,
2549 <&apps_smmu 0x596 0x0011>;
2550 interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 0 &mc_virt SLAVE_EBI_CH0 0>;
2556 reg = <0x0 0x01f40000 0x0 0x40000>;
2562 reg = <0x0 0x1fc0000 0x0 0x30000>;
2567 reg = <0 0x03240000 0 0x1000>;
2577 #clock-cells = <0>;
2582 pinctrl-0 = <&wsa_swr_active>;
2588 reg = <0 0x03250000 0 0x2000>;
2597 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2598 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2599 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2600 qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>;
2604 #size-cells = <0>;
2611 reg = <0 0x03300000 0 0x30000>;
2621 reg = <0 0x03370000 0 0x1000>;
2628 #clock-cells = <0>;
2635 pinctrl-0 = <&rx_swr_active>;
2637 reg = <0 0x03200000 0 0x1000>;
2648 #clock-cells = <0>;
2654 reg = <0 0x03210000 0 0x2000>;
2661 qcom,din-ports = <0>;
2664 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2665 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>;
2666 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2667 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2668 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2669 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2670 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2671 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2672 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2676 #size-cells = <0>;
2681 pinctrl-0 = <&tx_swr_active>;
2683 reg = <0 0x03220000 0 0x1000>;
2694 #clock-cells = <0>;
2701 reg = <0 0x03230000 0 0x2000>;
2712 qcom,dout-ports = <0>;
2713 qcom,ports-sinterval-low = /bits/ 8 <0xff 0x01 0x01 0x03 0x03>;
2714 qcom,ports-offset1 = /bits/ 8 <0xff 0x01 0x00 0x02 0x00>;
2715 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x00 0x00 0x00>;
2716 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2717 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2718 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2719 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2720 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2721 qcom,ports-lane-control = /bits/ 8 <0xff 0x00 0x01 0x00 0x01>;
2724 #size-cells = <0>;
2729 reg = <0 0x03380000 0 0x40000>;
2739 reg = <0 0x033c0000 0x0 0x20000>,
2740 <0 0x03550000 0x0 0x10000>;
2743 gpio-ranges = <&lpass_tlmm 0 0 14>;
2878 reg = <0 0x03d00000 0 0x40000>;
2883 iommus = <&adreno_smmu 0 0x401>;
2904 opp-supported-hw = <0xa>;
2910 opp-supported-hw = <0xb>;
2916 opp-supported-hw = <0xf>;
2922 opp-supported-hw = <0xf>;
2928 opp-supported-hw = <0xf>;
2934 opp-supported-hw = <0xf>;
2940 opp-supported-hw = <0xf>;
2948 reg = <0 0x03d6a000 0 0x30000>,
2949 <0 0x3de0000 0 0x10000>,
2950 <0 0xb290000 0 0x10000>,
2951 <0 0xb490000 0 0x10000>;
2969 iommus = <&adreno_smmu 5 0x400>;
2987 reg = <0 0x03d90000 0 0x9000>;
3002 reg = <0 0x03da0000 0 0x10000>;
3026 reg = <0 0x05c00000 0 0x4000>;
3029 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
3047 qcom,smem-states = <&smp2p_slpi_out 0>;
3068 #size-cells = <0>;
3073 iommus = <&apps_smmu 0x0541 0x0>;
3079 iommus = <&apps_smmu 0x0542 0x0>;
3085 iommus = <&apps_smmu 0x0543 0x0>;
3094 reg = <0 0x06002000 0 0x1000>, <0 0x16280000 0 0x180000>;
3111 reg = <0 0x06004000 0 0x1000>;
3127 #size-cells = <0>;
3147 reg = <0 0x06005000 0 0x1000>;
3171 reg = <0 0x06041000 0 0x1000>;
3186 #size-cells = <0>;
3206 reg = <0 0x06042000 0 0x1000>;
3221 #size-cells = <0>;
3234 reg = <0 0x06045000 0 0x1000>;
3249 #size-cells = <0>;
3251 port@0 {
3252 reg = <0>;
3269 reg = <0 0x06046000 0 0x1000>;
3293 reg = <0 0x06048000 0 0x1000>;
3310 reg = <0 0x0684c000 0 0x1000>;
3326 arm,primecell-periphid = <0x000bb908>;
3328 reg = <0 0x06b04000 0 0x1000>;
3343 #size-cells = <0>;
3356 reg = <0 0x06b05000 0 0x1000>;
3381 reg = <0 0x06b06000 0 0x1000>;
3405 reg = <0 0x06c08000 0 0x1000>;
3421 reg = <0 0x06c0b000 0 0x1000>;
3436 #size-cells = <0>;
3449 reg = <0 0x06c2d000 0 0x1000>;
3464 #size-cells = <0>;
3477 reg = <0 0x07040000 0 0x1000>;
3496 reg = <0 0x07140000 0 0x1000>;
3515 reg = <0 0x07240000 0 0x1000>;
3534 reg = <0 0x07340000 0 0x1000>;
3553 reg = <0 0x07440000 0 0x1000>;
3572 reg = <0 0x07540000 0 0x1000>;
3591 reg = <0 0x07640000 0 0x1000>;
3610 reg = <0 0x07740000 0 0x1000>;
3629 reg = <0 0x07800000 0 0x1000>;
3644 #size-cells = <0>;
3646 port@0 {
3647 reg = <0>;
3706 reg = <0 0x07810000 0 0x1000>;
3730 reg = <0 0x08300000 0 0x10000>;
3733 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
3749 qcom,smem-states = <&smp2p_cdsp_out 0>;
3770 #size-cells = <0>;
3775 iommus = <&apps_smmu 0x1001 0x0460>;
3781 iommus = <&apps_smmu 0x1002 0x0460>;
3787 iommus = <&apps_smmu 0x1003 0x0460>;
3793 iommus = <&apps_smmu 0x1004 0x0460>;
3799 iommus = <&apps_smmu 0x1005 0x0460>;
3805 iommus = <&apps_smmu 0x1006 0x0460>;
3811 iommus = <&apps_smmu 0x1007 0x0460>;
3817 iommus = <&apps_smmu 0x1008 0x0460>;
3828 reg = <0 0x088e3000 0 0x400>;
3830 #phy-cells = <0>;
3841 reg = <0 0x088e4000 0 0x400>;
3843 #phy-cells = <0>;
3853 reg = <0 0x088e8000 0 0x3000>;
3874 #size-cells = <0>;
3876 port@0 {
3877 reg = <0>;
3895 reg = <0 0x088eb000 0 0x1000>;
3906 #clock-cells = <0>;
3907 #phy-cells = <0>;
3919 reg = <0 0x08804000 0 0x1000>;
3929 iommus = <&apps_smmu 0x4a0 0x0>;
3930 qcom,dll-config = <0x0007642c>;
3931 qcom,ddr-config = <0x80040868>;
3964 reg = <0 0x09091000 0 0x1000>;
4026 reg = <0 0x090b6400 0 0x600>;
4086 reg = <0 0x090c0000 0 0x4200>;
4093 reg = <0 0x09100000 0 0xb4000>;
4100 reg = <0 0x09990000 0 0x1600>;
4107 reg = <0 0x0a6f8800 0 0x400>;
4145 interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>,
4146 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>;
4151 reg = <0 0x0a600000 0 0xcd00>;
4153 iommus = <&apps_smmu 0x0 0x0>;
4167 reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>,
4168 <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>,
4169 <0 0x09600000 0 0x50000>;
4176 reg = <0 0x0a8f8800 0 0x400>;
4214 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>,
4215 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>;
4220 reg = <0 0x0a800000 0 0xcd00>;
4222 iommus = <&apps_smmu 0x20 0>;
4232 reg = <0 0x0aa00000 0 0x100000>;
4245 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_VENUS_CFG 0>,
4246 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI_CH0 0>;
4249 iommus = <&apps_smmu 0x2100 0x0400>;
4293 reg = <0 0x0abf0000 0 0x10000>;
4308 #size-cells = <0>;
4310 reg = <0 0x0ac4f000 0 0x1000>;
4325 pinctrl-0 = <&cci0_default>;
4331 cci0_i2c0: i2c-bus@0 {
4332 reg = <0>;
4335 #size-cells = <0>;
4342 #size-cells = <0>;
4349 #size-cells = <0>;
4351 reg = <0 0x0ac50000 0 0x1000>;
4366 pinctrl-0 = <&cci1_default>;
4372 cci1_i2c0: i2c-bus@0 {
4373 reg = <0>;
4376 #size-cells = <0>;
4383 #size-cells = <0>;
4391 reg = <0 0x0ac6a000 0 0x2000>,
4392 <0 0x0ac6c000 0 0x2000>,
4393 <0 0x0ac6e000 0 0x1000>,
4394 <0 0x0ac70000 0 0x1000>,
4395 <0 0x0ac72000 0 0x1000>,
4396 <0 0x0ac74000 0 0x1000>,
4397 <0 0x0acb4000 0 0xd000>,
4398 <0 0x0acc3000 0 0xd000>,
4399 <0 0x0acd9000 0 0x2200>,
4400 <0 0x0acdb200 0 0x2200>;
4521 iommus = <&apps_smmu 0x800 0x400>,
4522 <&apps_smmu 0x801 0x400>,
4523 <&apps_smmu 0x840 0x400>,
4524 <&apps_smmu 0x841 0x400>,
4525 <&apps_smmu 0xc00 0x400>,
4526 <&apps_smmu 0xc01 0x400>,
4527 <&apps_smmu 0xc40 0x400>,
4528 <&apps_smmu 0xc41 0x400>;
4530 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_CAMERA_CFG 0>,
4531 <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI_CH0 0>,
4532 <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI_CH0 0>,
4533 <&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI_CH0 0>;
4541 #size-cells = <0>;
4543 port@0 {
4544 reg = <0>;
4571 reg = <0 0x0ad00000 0 0x10000>;
4587 reg = <0 0x0ae00000 0 0x1000>;
4590 interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>,
4591 <&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>;
4606 iommus = <&apps_smmu 0x820 0x402>;
4616 reg = <0 0x0ae01000 0 0x8f000>,
4617 <0 0x0aeb0000 0 0x2008>;
4633 interrupts = <0>;
4637 #size-cells = <0>;
4639 port@0 {
4640 reg = <0>;
4689 reg = <0 0xae90000 0 0x200>,
4690 <0 0xae90200 0 0x200>,
4691 <0 0xae90400 0 0x600>,
4692 <0 0xae91000 0 0x400>,
4693 <0 0xae91400 0 0x400>;
4715 #sound-dai-cells = <0>;
4724 #size-cells = <0>;
4726 port@0 {
4727 reg = <0>;
4769 reg = <0 0x0ae94000 0 0x400>;
4789 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
4799 #size-cells = <0>;
4803 #size-cells = <0>;
4805 port@0 {
4806 reg = <0>;
4841 reg = <0 0x0ae94400 0 0x200>,
4842 <0 0x0ae94600 0 0x280>,
4843 <0 0x0ae94900 0 0x260>;
4849 #phy-cells = <0>;
4861 reg = <0 0x0ae96000 0 0x400>;
4881 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
4891 #size-cells = <0>;
4895 #size-cells = <0>;
4897 port@0 {
4898 reg = <0>;
4914 reg = <0 0x0ae96400 0 0x200>,
4915 <0 0x0ae96600 0 0x280>,
4916 <0 0x0ae96900 0 0x260>;
4922 #phy-cells = <0>;
4934 reg = <0 0x0af00000 0 0x10000>;
4938 <&mdss_dsi0_phy 0>,
4940 <&mdss_dsi1_phy 0>,
4958 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
4959 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
4968 reg = <0 0x0c263000 0 0x1ff>, /* TM */
4969 <0 0x0c222000 0 0x1ff>; /* SROT */
4979 reg = <0 0x0c265000 0 0x1ff>, /* TM */
4980 <0 0x0c223000 0 0x1ff>; /* SROT */
4990 reg = <0 0x0c300000 0 0x400>;
4997 #clock-cells = <0>;
5002 reg = <0 0x0c3f0000 0 0x400>;
5007 reg = <0x0 0x0c440000 0x0 0x0001100>,
5008 <0x0 0x0c600000 0x0 0x2000000>,
5009 <0x0 0x0e600000 0x0 0x0100000>,
5010 <0x0 0x0e700000 0x0 0x00a0000>,
5011 <0x0 0x0c40a000 0x0 0x0026000>;
5015 qcom,ee = <0>;
5016 qcom,channel = <0>;
5018 #size-cells = <0>;
5025 reg = <0 0x0f100000 0 0x300000>,
5026 <0 0x0f500000 0 0x300000>,
5027 <0 0x0f900000 0 0x300000>;
5034 gpio-ranges = <&tlmm 0 0 181>;
5782 reg = <0 0x15000000 0 0x100000>;
5888 reg = <0 0x17300000 0 0x100>;
5891 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
5909 qcom,smem-states = <&smp2p_adsp_out 0>;
5929 #size-cells = <0>;
5944 #size-cells = <0>;
5961 #size-cells = <0>;
5963 iommus = <&apps_smmu 0x1801 0x0>;
5973 #sound-dai-cells = <0>;
5984 #size-cells = <0>;
5989 iommus = <&apps_smmu 0x1803 0x0>;
5995 iommus = <&apps_smmu 0x1804 0x0>;
6001 iommus = <&apps_smmu 0x1805 0x0>;
6011 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
6012 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
6018 reg = <0 0x17c10000 0 0x1000>;
6020 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
6026 ranges = <0 0 0 0x20000000>;
6028 reg = <0x0 0x17c20000 0x0 0x1000>;
6032 frame-number = <0>;
6035 reg = <0x17c21000 0x1000>,
6036 <0x17c22000 0x1000>;
6042 reg = <0x17c23000 0x1000>;
6049 reg = <0x17c25000 0x1000>;
6056 reg = <0x17c27000 0x1000>;
6063 reg = <0x17c29000 0x1000>;
6070 reg = <0x17c2b000 0x1000>;
6077 reg = <0x17c2d000 0x1000>;
6085 reg = <0x0 0x18200000 0x0 0x10000>,
6086 <0x0 0x18210000 0x0 0x10000>,
6087 <0x0 0x18220000 0x0 0x10000>;
6088 reg-names = "drv-0", "drv-1", "drv-2";
6092 qcom,tcs-offset = <0xd00>;
6162 reg = <0 0x18590000 0 0x1000>;
6172 reg = <0 0x18591000 0 0x1000>,
6173 <0 0x18592000 0 0x1000>,
6174 <0 0x18593000 0 0x1000>;
6183 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
6737 thermal-sensors = <&tsens0 0>;
6807 thermal-sensors = <&tsens1 0>;